CyrIng
357b4b8c28
[ppc64] Detect the IBM POWER10 Functional Simulator
2025-03-16 14:36:23 +01:00
CyrIng
5dba49ee90
[aarch64][riscv64][ppc64] Improving DT integration to detect VM
2025-03-16 12:55:00 +01:00
CyrIng
260d8af2ff
[AArch64] Improving virtualization detection from Device Tree
2025-03-15 15:09:44 +01:00
CyrIng
0b58936203
[ppc64][riscv64] Device Tree fetching based on kernel version
2025-03-15 00:06:53 +01:00
CyrIng
e532c1c2e9
[PowerPC] Preliminary port to the ppc64le architecture
2025-03-13 16:08:30 +01:00
CyrIng
57c331e6c9
[riscv64] Adding vendor Microchip
2025-03-10 14:41:58 +01:00
CyrIng
56b2858c53
[riscv64] Attempt to read the Hart ID from device tree
2025-03-09 11:15:25 +01:00
CyrIng
b55ef76742
[riscv64] Restore PMU counter delta calculation
2025-03-09 09:57:46 +01:00
CyrIng
450189f5a4
[riscv64] mvendorid & marchid based architecture qualification
2025-03-08 17:01:47 +01:00
CyrIng
262287165f
[riscv64] Specification of SSTATUS and SCOUNTEREN registers
2025-03-05 16:59:05 +01:00
CyrIng
e69f388f0e
[riscv64] Normalize counters to work with unaccurate QEMU cycles
2025-03-04 21:35:19 +01:00
CyrIng
7704ea4ee2
[riscv64] Attempt to enable the Cycle and Instruction counters
2025-03-04 20:21:03 +01:00
CyrIng
592f85564d
[riscv64] Read the performance cycles using rdcycle
2025-03-02 15:37:17 +01:00
CyrIng
774d061f8c
[riscv64] Read the retired instructions counter using rdinstret
2025-03-01 17:17:39 +01:00
CyrIng
5c3bc58c56
[riscv64] Get the TSC from rdtime instruction
2025-02-26 19:30:51 +01:00
CyrIng
04364b8282
[riscv64] Comment out any reading of cycles
2025-02-24 02:57:13 +01:00
CyrIng
92c5e0f05f
[RISC-V] Code clean-up to debug start-up
2025-02-23 16:23:53 +01:00
CyrIng
f314201943
[Build] Changed some inline function prototypes
2025-02-23 08:05:03 +01:00
CyrIng
d28166050a
[RISC-V] Preliminary port of the riscv64 architecture
2025-02-22 11:12:48 +01:00
CyrIng
cb9fc92098
[Build] Implement amd_pci_dev_to_node_id from Kernel 6.14
2025-02-03 13:21:00 +01:00
CyrIng
48688cfb34
[AMD][Strix Point] Attempt to decode UMC and IOMMU controllers
2025-02-01 11:47:54 +01:00
CyrIng
f31383cee7
Merge branch 'jlacvdr-fix-ci-pin-build-env'
2025-01-27 21:41:54 +01:00
jlacvdr
fba7b33b8c
[CI] Pin build environment to ubuntu-22.04
2025-01-27 11:42:00 +01:00
CyrIng
f54194306e
[AMD][Raphael] Adding Ryzen 5 7400F
...
[Granite Ridge] Adding Ryzen 5 9600
2025-01-24 14:29:15 +01:00
CyrIng
8597fe1dca
Merge branch 's-stepien-dev-sstepien-warning-fix'
2025-01-24 13:54:35 +01:00
Slawomir Stepien
6b93c1d7ed
[Build] Allow changing WARNING variable from command line
...
User should be able to change the WARNING build variable during make
invocation.
This change also specifies what is the true default value for that
variable.
2025-01-20 10:38:41 +01:00
CyrIng
17a08f536a
Copyright (C) 2015-2025 CYRIL COURTIAT
2025-01-19 13:15:05 +01:00
CyrIng
ad6730c83d
Version 2 ; Experience version
2024-12-24 07:53:04 +01:00
CyrIng
902b7ee01e
[Build][x86_64] AlmaLinux 9.5 (Teal Serval) compilation fix ( #519 )
2024-12-19 19:06:26 +01:00
CyrIng
f688e95c7e
[AArch64] Checking specification of Memory Model Feature Registers
2024-12-15 11:10:01 +01:00
CyrIng
51827cdc10
[AArch64] Aggregate and display ISA features of ID_AA64ISAR3_EL1
2024-12-12 19:00:57 +01:00
CyrIng
d0ac57de0f
[AArch64] Instruction Set Attribute Register 3 ID_AA64ISAR3_EL1
2024-12-11 14:40:20 +01:00
CyrIng
d7fa7ac899
[AMD][VERMEER] Adding Ryzen 5 5600XT and 5600T processors
2024-12-11 14:33:30 +01:00
CyrIng
8eae541e8c
[UI] Fix System Registers window for a 3 digits CPU id number
2024-12-06 22:08:34 +01:00
CyrIng
a33aa70778
[AArch64] Processor Feature Register 2 AA64PFR2_EL1
2024-12-06 21:47:42 +01:00
CyrIng
b10395cd02
[Doc] SSH tip to run the UI
2024-12-06 21:45:19 +01:00
CyrIng
d73f4dc6c8
[AArch64] Display FP and SIMD bits from MVFR
...
* Added remaining `CLRBHB` and `PCDPHINT` of `ISAR2`
2024-12-04 19:47:49 +01:00
CyrIng
0ee6ea9d19
[AArch64] Display the Streaming Vector Control Register SVCR
...
* Query and export the Media and VFP Feature Registers `MVFR`
2024-12-04 13:26:40 +01:00
CyrIng
56d46c24a3
[AArch64] Display, export Floating-point Control Register FPCR
2024-12-04 01:47:17 +01:00
CyrIng
cb4983a05f
[AMD][Zen 5c] Fixed EPYC Turin-Dense series
2024-12-02 20:45:12 +01:00
CyrIng
e6072d7a39
[AArch64] Architectural Feature Access Control Register CPACR
2024-11-30 12:27:22 +01:00
CyrIng
f6e5d56e19
[AArch64] Display bits of the Hypervisor Configuration Register
2024-11-23 00:49:03 +01:00
CyrIng
6436a4851d
[AArch64] Access HCR_EL2 based on CurrentEL bits
2024-11-22 19:02:52 +01:00
CyrIng
c574ab115b
[AMD][Family 1Ah][Granite Ridge] P-State programming fix
2024-11-19 21:23:20 +01:00
CyrIng
ed5feaa4be
[AArch64] Query and JSON export Hypervisor Configuration Register
...
* `HCR_EL2` succesfully accessed in `EL1` with RK3588 (A55 + A76)
* Experimental mode required
2024-11-18 20:53:46 +01:00
CyrIng
09a1d36a92
[AMD] Reserve the BTC-NOBR aggregation to Zen2 architecture
2024-11-17 12:56:32 +01:00
CyrIng
7ee38f9284
[AMD][Family 1Ah] Merge PCI identifier lists
2024-11-17 10:44:28 +01:00
CyrIng
c75af85b5b
[Doc] Mention the AMD family 1Ah support in README
2024-11-16 13:35:40 +01:00
CyrIng
468249d27b
[CI][AArch64] Commenting out the debian-testing and alpine-latest
2024-11-16 13:19:20 +01:00
CyrIng
6b28cc2007
[AMD][Family 1Ah] Refactoring topology for CCD cluster
2024-11-13 12:12:24 +01:00
