ich777/CoreFreq
1
0
Fork 0
mirror of https://github.com/cyring/CoreFreq.git synced 2025-07-23 12:13:07 +02:00
Code Issues Packages Projects Releases Wiki Activity

[AArch64] Display the Streaming Vector Control Register SVCR

Browse Source 
* Query and export the Media and VFP Feature Registers `MVFR`
This commit is contained in:
CyrIng
2024-12-04 13:26:40 +01:00
parent 56d46c24a3
commit 0ee6ea9d19
9 changed files with 326 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
aarch64/arm_reg.h
View File

@@ -726,6 +726,55 @@ typedef union
};
} SSBS2;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
SIMDReg : 4-0,
FPSP : 8-4,
FPDP : 12-8,
FPTrap : 16-12,
FPDivide : 20-16,
FPSqrt : 24-20,
FPShVec : 28-24,
FPRound : 32-28,
RES0 : 64-32;
};
} MVFR0;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
FPFtZ : 4-0,
FPDNaN : 8-4,
SIMDLS : 12-8,
SIMDInt : 16-12,
SIMDSP : 20-16,
SIMDHP : 24-20,
FPHP : 28-24,
SIMDFMAC : 32-28,
RES0 : 64-32;
};
} MVFR1;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
SIMDMisc : 4-0,
FPMisc : 8-4,
RES0 : 32-8,
RES1 : 64-32;
};
} MVFR2;
typedef union
{ /* R82; A55; A75; A76; A76AE; A77; A78; A78AE; A78C; X1; X1C; N3; V1 */
unsigned long long value; /* Pkg:0x0000000007bfda77 */

41
aarch64/corefreq-cli-json.c
View File

@@ -732,6 +732,47 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SME_SF8DP2);
json_end_object(&s);
}
json_key(&s, "MVFR");
{
json_start_object(&s);
json_key(&s, "FP_Round");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Round);
json_key(&s, "FP_Sh_Vec");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Sh_Vec);
json_key(&s, "FP_Sqrt");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Sqrt);
json_key(&s, "FP_Divide");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Divide);
json_key(&s, "FP_Trap");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Trap);
json_key(&s, "FP_DP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_DP);
json_key(&s, "FP_SP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_SP);
json_key(&s, "FP_HP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_HP);
json_key(&s, "FP_NaN");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_NaN);
json_key(&s, "FP_FtZ");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_FtZ);
json_key(&s, "FP_Misc");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.FP_Misc);
json_key(&s, "SIMD_Reg");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Reg);
json_key(&s, "SIMD_FMA");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_FMA);
json_key(&s, "SIMD_HP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_HP);
json_key(&s, "SIMD_SP");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_SP);
json_key(&s, "SIMD_Int");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Int);
json_key(&s, "SIMD_LS");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_LS);
json_key(&s, "SIMD_Misc");
json_literal(&s, "%u", (unsigned) RO(Shm)->Proc.Features.SIMD_Misc);
json_end_object(&s);
}
json_key(&s, "MISC");
{
json_start_object(&s);

6
aarch64/corefreq-cli-rsc-en.h
View File

@@ -839,6 +839,10 @@
#define RSC_SYS_REG_EL_EXEC_CODE_EN " Executes in AArch64 or AArch32 "
#define RSC_SYS_REG_EL_SEC_CODE_EN " Secure Exception Level "
#define RSC_SYS_REG_SVCR_CODE_EN " Streaming Vector Control Register "
#define RSC_SYS_REG_SVCR_ZA_CODE_EN " SME ZA storage "
#define RSC_SYS_REG_SVCR_SM_CODE_EN " Streaming SVE mode "
#define RSC_SYS_REG_CPACR_CODE_EN " Access Control Register "
#define RSC_SYS_REG_ACR_TCP_CODE_EN " Trap Coprocessor Access Control "
#define RSC_SYS_REG_ACR_TAM_CODE_EN " Trap Activity Monitor Access "
@@ -2094,6 +2098,8 @@
"Exec\0: \0 64 \0 32 \0 \0 64 \0 32 \0 \0" \
" 64 \0 32 \0 SEC\0 \0 64 \0 32 "
#define RSC_SYS_REG_HDR_SVCR_CODE "SVCR\0 ZA \0 SM "
#define RSC_SYS_REG_HDR_CPACR_CODE \
"ACR \0 TCP\0 TAM\0 POR\0 TTA\0 SME\0 FP \0 ZEN\0 R\0ES "

4
aarch64/corefreq-cli-rsc-fr.h
View File

@@ -531,6 +531,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_SYS_REG_EL_EXEC_CODE_FR RSC_SYS_REG_EL_EXEC_CODE_EN
#define RSC_SYS_REG_EL_SEC_CODE_FR RSC_SYS_REG_EL_SEC_CODE_EN
#define RSC_SYS_REG_SVCR_CODE_FR RSC_SYS_REG_SVCR_CODE_EN
#define RSC_SYS_REG_SVCR_ZA_CODE_FR RSC_SYS_REG_SVCR_ZA_CODE_EN
#define RSC_SYS_REG_SVCR_SM_CODE_FR RSC_SYS_REG_SVCR_SM_CODE_EN
#define RSC_SYS_REG_CPACR_CODE_FR RSC_SYS_REG_CPACR_CODE_EN
#define RSC_SYS_REG_ACR_TCP_CODE_FR RSC_SYS_REG_ACR_TCP_CODE_EN
#define RSC_SYS_REG_ACR_TAM_CODE_FR RSC_SYS_REG_ACR_TAM_CODE_EN

4
aarch64/corefreq-cli-rsc.c
View File

@@ -740,6 +740,10 @@ RESOURCE_ST Resource[] = {
LDT(RSC_SYS_REG_EL),
LDT(RSC_SYS_REG_EL_EXEC),
LDT(RSC_SYS_REG_EL_SEC),
LDQ(RSC_SYS_REG_HDR_SVCR),
LDT(RSC_SYS_REG_SVCR),
LDT(RSC_SYS_REG_SVCR_ZA),
LDT(RSC_SYS_REG_SVCR_SM),
LDQ(RSC_SYS_REG_HDR_CPACR),
LDT(RSC_SYS_REG_CPACR),
LDT(RSC_SYS_REG_ACR_TCP),

4
aarch64/corefreq-cli-rsc.h
View File

@@ -563,6 +563,10 @@ enum {
RSC_SYS_REG_EL,
RSC_SYS_REG_EL_EXEC,
RSC_SYS_REG_EL_SEC,
RSC_SYS_REG_HDR_SVCR,
RSC_SYS_REG_SVCR,
RSC_SYS_REG_SVCR_ZA,
RSC_SYS_REG_SVCR_SM,
RSC_SYS_REG_HDR_CPACR,
RSC_SYS_REG_CPACR,
RSC_SYS_REG_ACR_TCP,

20
aarch64/corefreq-cli.c
View File

@@ -453,7 +453,8 @@ REASON_CODE SystemRegisters( Window *win,
};
enum AUTOMAT {
DO_END, DO_SPC, DO_CPU, DO_FLAG, DO_HCR,
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR, DO_ACR
DO_SCTLR, DO_SCTLR2, DO_EL, DO_FPSR, DO_FPCR,
DO_SVCR, DO_ACR
};
const struct SR_ST {
struct SR_HDR {
@@ -1036,9 +1037,9 @@ REASON_CODE SystemRegisters( Window *win,
[11] = {&RSC(SYS_REG_HDR_FPSR).CODE()[55],RSC(SYS_REG_FPSR_IOC).CODE()},
[12] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[13] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[15] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[16] = {RSC(SYS_REGS_SPACE).CODE(), NULL},
[14] = {&RSC(SYS_REG_HDR_SVCR).CODE()[ 0],RSC(SYS_REG_SVCR).CODE()},
[15] = {&RSC(SYS_REG_HDR_SVCR).CODE()[ 5],RSC(SYS_REG_SVCR_ZA).CODE()},
[16] = {&RSC(SYS_REG_HDR_SVCR).CODE()[10],RSC(SYS_REG_SVCR_SM).CODE()},
{NULL, NULL}
},
.flag = (struct SR_BIT[]) {
@@ -1056,9 +1057,9 @@ REASON_CODE SystemRegisters( Window *win,
[11] = {DO_FPSR, 1 , FPSR_IOC , 1 },
[12] = {DO_SPC , 1 , UNDEF_CR , 0 },
[13] = {DO_SPC , 1 , UNDEF_CR , 0 },
[14] = {DO_SPC , 1 , UNDEF_CR , 0 },
[15] = {DO_SPC , 1 , UNDEF_CR , 0 },
[16] = {DO_SPC , 1 , UNDEF_CR , 0 },
[14] = {DO_CPU , 1 , UNDEF_CR , 0 },
[15] = {DO_SVCR, RO(Shm)->Proc.Features.SME, SVCR_SMEZA, 1 },
[16] = {DO_SVCR, RO(Shm)->Proc.Features.SME, SVCR_SVEME, 1 },
{DO_END , 1 , UNDEF_CR , 0 }
}
},
@@ -1182,6 +1183,11 @@ REASON_CODE SystemRegisters( Window *win,
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.FPCR,
pFlag->pos, pFlag->len));
break;
case DO_SVCR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.SVCR,
pFlag->pos, pFlag->len));
break;
case DO_ACR:
PRT(REG, attrib[2], "%3llx ",
BITEXTRZ(RO(Shm)->Cpu[cpu].SystemRegister.CPACR,

184
aarch64/corefreqk.c
View File

@@ -524,6 +524,9 @@ static void Query_Features(void *pArg)
volatile AA64MMFR2 mmfr2;
volatile AA64PFR0 pfr0;
volatile AA64PFR1 pfr1;
volatile MVFR0 mvfr0;
volatile MVFR1 mvfr1;
volatile MVFR2 mvfr2;
iArg->Features->Info.Vendor.CRC = CRC_RESERVED;
iArg->SMT_Count = 1;
@@ -542,6 +545,9 @@ static void Query_Features(void *pArg)
"mrs %[mmfr1], id_aa64mmfr1_el1""\n\t"
"mrs %[pfr0] , id_aa64pfr0_el1""\n\t"
"mrs %[pfr1] , id_aa64pfr1_el1""\n\t"
"mrs %[mvfr0], mvfr0_el1" "\n\t"
"mrs %[mvfr1], mvfr1_el1" "\n\t"
"mrs %[mvfr2], mvfr2_el1" "\n\t"
"isb"
: [midr] "=r" (midr),
[cntfrq] "=r" (cntfrq),
@@ -554,7 +560,10 @@ static void Query_Features(void *pArg)
[mmfr0] "=r" (mmfr0),
[mmfr1] "=r" (mmfr1),
[pfr0] "=r" (pfr0),
[pfr1] "=r" (pfr1)
[pfr1] "=r" (pfr1),
[mvfr0] "=r" (mvfr0),
[mvfr1] "=r" (mvfr1),
[mvfr2] "=r" (mvfr2)
:
: "memory"
);
@@ -1553,6 +1562,179 @@ static void Query_Features(void *pArg)
iArg->Features->SME_SF8DP4 = smfr0.SF8DP4;
iArg->Features->SME_SF8DP2 = smfr0.SF8DP2;
}
switch (mvfr0.FPRound) {
case 0b0001:
iArg->Features->FP_Round = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Round = 0;
break;
}
switch (mvfr0.FPShVec) {
case 0b0001:
iArg->Features->FP_Sh_Vec = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Sh_Vec = 0;
break;
}
switch (mvfr0.FPSqrt) {
case 0b0001:
iArg->Features->FP_Sqrt = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Sqrt = 0;
break;
}
switch (mvfr0.FPDivide) {
case 0b0001:
iArg->Features->FP_Divide = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Divide = 0;
break;
}
switch (mvfr0.FPTrap) {
case 0b0001:
iArg->Features->FP_Trap = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Trap = 0;
break;
}
switch (mvfr0.FPDP) {
case 0b0010:
case 0b0001:
iArg->Features->FP_DP = 1;
break;
case 0b0000:
default:
iArg->Features->FP_DP = 0;
break;
}
switch (mvfr0.FPSP) {
case 0b0010:
case 0b0001:
iArg->Features->FP_SP = 1;
break;
case 0b0000:
default:
iArg->Features->FP_SP = 0;
break;
}
switch (mvfr1.FPHP) {
case 0b0011:
case 0b0010:
case 0b0001:
iArg->Features->FP_HP = 1;
break;
default:
case 0b0000:
iArg->Features->FP_HP = 0;
break;
}
switch (mvfr0.SIMDReg) {
case 0b0010:
case 0b0001:
iArg->Features->SIMD_Reg = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_Reg = 0;
break;
}
switch (mvfr1.SIMDFMAC) {
case 0b0001:
iArg->Features->SIMD_FMA = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_FMA = 0;
break;
}
switch (mvfr1.SIMDHP) {
case 0b0010:
case 0b0001:
iArg->Features->SIMD_HP = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_HP = 0;
break;
}
switch (mvfr1.SIMDSP) {
case 0b0001:
iArg->Features->SIMD_SP = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_SP = 0;
break;
}
switch (mvfr1.SIMDInt) {
case 0b0001:
iArg->Features->SIMD_Int = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_Int = 0;
break;
}
switch (mvfr1.SIMDLS) {
case 0b0001:
iArg->Features->SIMD_LS = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_LS = 0;
break;
}
switch (mvfr1.FPDNaN) {
case 0b0001:
iArg->Features->FP_NaN = 1;
break;
case 0b0000:
default:
iArg->Features->FP_NaN = 0;
break;
}
switch (mvfr1.FPFtZ) {
case 0b0001:
iArg->Features->FP_FtZ = 1;
break;
case 0b0000:
default:
iArg->Features->FP_FtZ = 0;
break;
}
switch (mvfr2.FPMisc) {
case 0b0100:
case 0b0011:
case 0b0010:
case 0b0001:
iArg->Features->FP_Misc = 1;
break;
case 0b0000:
default:
iArg->Features->FP_Misc = 0;
break;
}
switch (mvfr2.SIMDMisc) {
case 0b0011:
case 0b0010:
case 0b0001:
iArg->Features->SIMD_Misc = 1;
break;
case 0b0000:
default:
iArg->Features->SIMD_Misc = 0;
break;
}
/* Reset the performance features bits: present is 0b1 */
iArg->Features->PerfMon.CoreCycles = 0b0;
iArg->Features->PerfMon.InstrRetired = 0b0;

23
aarch64/coretypes.h
View File

@@ -295,6 +295,9 @@ enum SYS_REG {
FPCR_RM = 22, /* [23:22] */
FPCR_FZH = 19,
SVCR_SMEZA = 1,
SVCR_SVEME = 0,
ACR_TCPAC = 31,
ACR_TAM = 30,
ACR_E0POE = 29,
@@ -992,7 +995,25 @@ typedef struct /* BSP features. */
MTE : 17-14,
DF2 : 18-17,
PFAR : 19-18,
_Unused1_ : 64-19;
FP_Round : 20-19,
FP_Sh_Vec : 21-20,
FP_Sqrt : 22-21,
FP_Divide : 23-22,
FP_Trap : 24-23,
FP_DP : 25-24,
FP_SP : 26-25,
FP_HP : 27-26,
FP_NaN : 28-27,
FP_FtZ : 29-28,
FP_Misc : 30-29,
SIMD_Reg : 31-30,
SIMD_FMA : 32-31,
SIMD_HP : 33-32,
SIMD_SP : 34-33,
SIMD_Int : 35-34,
SIMD_LS : 36-35,
SIMD_Misc : 37-36,
_Unused1_ : 64-37;
Bit64 InvariantTSC : 8-0,
HyperThreading : 9-8,