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Author SHA1 Message Date
CyrIng
cb55c1b726 [UI] Increased max ratio in HWP condition to avoid a zero frequency 2024-11-09 09:30:40 +01:00
CyrIng
976cd051f4 [Build] Print other variables from Makefile recipe info 
CORE_COUNT
TASK_ORDER
MAX_FREQ_HZ
HWM_CHIPSET
 2024-11-09 08:49:44 +01:00
CyrIng
d4c48853e4 [AMD][V2000 Series] Adding the Ryzen Embedded V2A46 2024-11-08 20:19:03 +01:00
CyrIng
37d9359cde [AMD][Zen5/Granite Ridge] Added Ryzen 7 9800X3D processor 1.98.5 2024-11-01 08:57:26 +01:00
CyrIng
040697fab3 [AMD] Completed CPUID leaf 0x80000021 from PPR 57238 2024-11-01 08:47:08 +01:00
CyrIng
b23b4d4242 [AMD][Family 1Ah] Updated the PStateDef MSR 2024-10-27 15:24:00 +01:00
CyrIng
a1189f507c [AMD][Turin] Employed the Genoa UMC decoder 2024-10-27 13:49:09 +01:00
CyrIng
bc7d3fef10 [Intel][RPL] Added remaining PX and H processor line platforms 2024-10-27 11:59:42 +01:00
CyrIng
901f830a69 [Intel][MTL-M] Set PCI ids into Daemon 2024-10-27 11:40:39 +01:00
CyrIng
c0b78d6231 [Intel][MTL-M] Declare PCI ids to probe the IMC and TCO 2024-10-27 10:54:07 +01:00
CyrIng
82fe2e1338 [AMD][GENOA] Added a left over EPYC Embedded 9534 2024-10-23 20:59:10 +02:00
CyrIng
018ee1264f [AMD][SIENA] Added the EPYC Embedded 8004 Series 2024-10-23 20:44:44 +02:00
CyrIng
3320490ce5 [AMD][PHOENIX2] Added the unlocked for overclocking Ryzen 3 8300GE 2024-10-23 19:43:59 +02:00
CyrIng
ead29a1ade [AMD][PHOENIX2] Added the unlocked for overclocking Ryzen 5 8500GE 2024-10-23 19:36:18 +02:00
CyrIng
b6522d6c51 [AMD][Zen] Added remaining X3D processor models 2024-10-23 19:19:22 +02:00
CyrIng
e43ea906ad [AMD][Zen5] Mitigation mechanisms and Features bits 
`SBPB`,
`SRSO_NO`,
`SRSO_USR_KNL_NO`,
`ERMSB`,
`FSRS`,
`FSRC_CMPSB`,
`PREFETCHI`
 2024-10-20 15:36:32 +02:00
CyrIng
722bc2ba7b [Intel][LNL] Added PCI ids to probe any IMC and SMBUS 
[Intel][ARL] Completed with SMBUS PCI id
 2024-10-20 11:23:08 +02:00
CyrIng
a8c0930c08 [CI] Disable the unfound arm64v8/ubuntu:rolling 2024-10-19 15:05:41 +02:00
CyrIng
a6112eadbe [UI] Debugging a target clock ratio selector issue 2024-10-19 14:20:57 +02:00
CyrIng
75362d4092 [Intel][ADL-X/ADL-N] Declare PCI ids to probe the memory controller 2024-10-16 13:11:19 +02:00
CyrIng
2499c3c389 [Intel][ARL][IMC] DDR5: tWR = tWRPRE - tCWL - 10 2024-10-15 18:38:57 +02:00
CyrIng
bd528a9af4 [Intel][ARL] Declare PCI ids to probe the IMC as a MTL controller 2024-10-13 13:02:13 +02:00
CyrIng
2f2e041a4e [AMD] Supply a fallback thermal junction max to various Zen series 2024-10-12 16:58:56 +02:00
CyrIng
d484bd999a [AMD][Zen5][Zen5c] Introducing the TURIN architecture 2024-10-12 16:09:09 +02:00
CyrIng
948db75aea [AMD][Strix Point] Adding PRO series 2024-10-12 12:19:47 +02:00
CyrIng
3b9eb7d26f [Build] Makefile compliant with the -s silent option 2024-09-29 12:22:33 +02:00
CyrIng
4515f5d2ab [Build] Prevent a collision with 6.11 kernel macro WRMSRNS 1.98.4 2024-09-19 19:28:20 +02:00
CyrIng
92ff25bf9f [x86_64][Virtualization] Switch to HCF or VP_RUNTIME counters 2024-08-30 12:49:11 +02:00
CyrIng
85b1e62618 [AMD][VMR/RPL/GNR] Voltage Curve Optimizer HWM CHIPSET=AMD VCO 1.98.3 2024-08-25 13:09:07 +02:00
CyrIng
4948b33278 [AMD][Zen] Improve COF remainder calculation 2024-08-24 13:47:59 +02:00
CyrIng
203ff07b76 [AMD/Zen5] Attempt a P-State MSR spec to fix the COF calculation 2024-08-24 11:46:01 +02:00
CyrIng
0e37a13498 [Zen5/Granite Ridge] Changed the Voltage formula identifier 2024-08-19 08:59:43 +02:00
CyrIng
8ca842b164 [Intel][WDT] Based on C620 Series PCH datasheet, probe TCO devices 
* C620 Series Chipset Production SKUs (`0xa1a3`)
* C620 Series Chipset Super SKUs (`0xa223`)
1.98.2 		2024-08-12 00:35:24 +02:00
CyrIng
bd68f0407c [Intel][WDT] More TCO controllers to probe 
* Sunrise Point/H (`0xa123`)
* Cannon Lake/LP (`0x9da3`)
* Comet Lake/H (`0x06a3`)
* Ice Lake/LP (`0x34a3`)
* Tiger Lake/H (`0x43a3`)
 2024-08-11 17:19:38 +02:00
CyrIng
e735fd0fb8 [Intel][WDT] Completing devices to probe TCO 
* Elkhart Lake (`0x4b23`)
* Kaby Lake/H (`0xa2a3`)
* Cannon Lake (`0xa323`)
* Comet Lake/V (`0xa3a3`)
* Ice Lake/NG (`0x38a3`)
* Alder lake/M (`0x54a3`)
* Arrow Lake/S (`0x7f23`)
 2024-08-11 16:11:44 +02:00
CyrIng
b5a20e8e0d [Intel][WDT] Adding devices to probe TCO 
* Jasper Lake SMBus (`0x4da3`)
* Sunrise Point-LP SMBus (`0x9d23`)
* Comet Lake PCH-LP SMBus (`0x02a3`)
 2024-08-11 13:56:51 +02:00
CyrIng
293e0f953c [Intel] Grant MSR_FLEX_RATIO access to Alder Lake/H (06_9A) 
* Removed function condition to access the Flex Ratio register
 2024-08-10 14:12:45 +02:00
CyrIng
5a3c3963ba [Intel] Deny MSR_FLEX_RATIO access to Nehalem/Bloomfield(06_1A) 2024-08-08 12:12:29 +02:00
CyrIng
e8fe368fd3 [Doc] Refreshed README and Makefile 1.98.1 2024-08-06 19:01:28 +02:00
CyrIng
875c8ab936 [Intel] Feature-bits of Core Ultra architecture 2024-08-06 14:48:55 +02:00
CyrIng
68ee040022 [AMD][Zen] Inject threshold events when thermal is out of bounds 2024-08-06 11:54:56 +02:00
CyrIng
ff50d183fe [Intel][TGL][ADL][RPL] New devices to probe IMC and Watchdog 2024-08-05 13:34:43 +02:00
CyrIng
a7b45ce7bf [Intel][Raptor Lake-E] Adding the IMC probing entries 2024-08-05 04:30:08 +02:00
CyrIng
a6989b0ada [AMD] Generic Zen architectures renamed with their Family number 2024-08-05 02:40:08 +02:00
CyrIng
a1e17e88b7 [AMD] Added a generic entry for the 1A family 2024-08-04 21:39:09 +02:00
CyrIng
70a527c5cd [Build] Now leave version number in Makefile 
[Build] Pretty print the build and the clean of outputs
* Allow the `V=n` option increase the verbose level (incl. kernel)
 2024-08-04 15:10:21 +02:00
CyrIng
74b8354e03 [Intel] Grant full MSR_FLEX_RATIO access to Raptor Lake (06_B7) 2024-08-03 10:13:35 +02:00
CyrIng
2ff2690715 [Intel] Added HB DIDs of Raptor Lake-E 2024-08-03 01:20:00 +02:00
CyrIng
00d3be0617 [Intel][ADL ... MTL] Code review of IMC decoders 2024-08-03 01:19:19 +02:00
CyrIng
1614819839 [Intel][ADL] Compute DIMM Bank and Columns on both channels 2024-08-02 19:10:04 +02:00