CyrIng
347045ed17
Revert "[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98"
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This reverts commit e5a5d0c1d6
2025-05-12 15:37:08 +02:00
CyrIng
e684e642d0
[UI] Increased length of L3 cache digits in header
2025-05-12 12:12:29 +02:00
CyrIng
c2b396a215
[AMD][Zen] Now conducts Datafabric calls through Kernel PCI
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[HSMP] Provides its own lock rather than SMN' lock
2025-05-12 11:55:34 +02:00
CyrIng
22f9c460a9
[AMD][Zen] HSMP arguments index fix in CONFIG_AMD_NB build mode
2025-05-11 13:03:04 +02:00
CyrIng
acbe192ad5
[AMD][Zen] Replaced package thermal with a pointer function
2025-05-10 18:11:05 +02:00
CyrIng
43fd828bdc
[AMD][Genoa] Probe up to four memory controllers
2025-05-10 15:11:21 +02:00
CyrIng
0729f349e4
[AMD] Improved EPYC Genoa support
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* CCD and CCX topology fixed to compute the right thermal SMU address
* Increase `BIT_IO_RETRIES_COUNT` to parallelize `HSMP_RD_DIMM_PWR` calls
* Added specifics for an "Eng Sample" of Genoa architecture
2025-05-09 19:44:16 +02:00
CyrIng
93c7096e2b
[Code Review] Refactored variable names for inclusivity
2025-05-08 11:17:40 +02:00
CyrIng
511fa2fe4d
[AMD][Genoa] Accumulate the power consumed by RAM
2025-05-04 18:22:35 +02:00
CyrIng
e5a5d0c1d6
[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98
2025-05-04 07:18:23 +02:00
CyrIng
e3bb96bf85
[x86_64] Order SMBIOS DIMM list by channel
2025-05-04 06:56:49 +02:00
CyrIng
d94626d276
[IMC] Can display Twelve Channel memory controller
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* Renamed `Disabled` to `Undefined` channels
2025-05-03 17:48:32 +02:00
CyrIng
e9eed278f0
[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots
2025-05-03 16:42:40 +02:00
CyrIng
638883766b
[Kernel] VT-d: request memory region before use
2025-05-01 09:39:10 +02:00
CyrIng
adf8cbadc5
[AMD][Hawk Point] Set AddrCfg & DimmCfg addresses for Phoenix UMC
2025-04-27 11:28:24 +02:00
CyrIng
de901592a2
[AMD][Genoa] Attempt to monitor DIMM power consumption from HSMP
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* Specifications of some Zen registers
2025-04-27 10:58:53 +02:00
CyrIng
b4903129ac
[AMD][Family 1Ah] Added the HSMP for EPYC Turin
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* Check mailbox protocol is correctly functioning
* using the arithmetic addition `2 + 1 = 3`
2025-04-19 13:46:46 +02:00
CyrIng
c508b7d3f1
[CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number
2025-04-18 14:48:51 +02:00
CyrIng
063fb88127
[CLI][x86_64] Compute the SMBIOS DIMM part number (rev 2)
2025-04-18 14:06:13 +02:00
CyrIng
916546f4cb
[x86_64] Check HCF capability for MPERF/APERF MSR access in VM
2025-04-16 14:21:47 +02:00
CyrIng
7064970173
[AMD][EPYC][Genoa] Use generic voltage & power
2025-04-13 10:50:04 +02:00
CyrIng
2171321cf6
[Doc] README for Rocky Linux and Clear Linux
2025-04-12 11:21:35 +02:00
CyrIng
2cce3ed28d
[Build] Prevent module loading if detected CPU count > CORE_COUNT
2025-04-12 09:37:20 +02:00
CyrIng
6509cc4ba8
[Build] Make static the PCI list to comply with kernel frame size
2025-04-10 20:14:46 +02:00
CyrIng
f055e6acad
[Intel][MTL][ARL] Improving MC Bus and DDR speed to follow OC SOC
2025-04-09 21:55:45 +02:00
CyrIng
812f297a22
[Build] Kernel 6.15 is switching to use hrtimer_setup()
2025-04-09 09:54:20 +02:00
CyrIng
4600e91f5b
[CI] Bump to uraimo version 3
2025-04-07 13:53:25 +02:00
CyrIng
b838bf059d
[Intel][MTL][ARL] Refactored IMC decoder to query DDR clock
2025-04-07 12:57:52 +02:00
CyrIng
ef11110bb7
[UI] Display N/A when Intel processor is not HDC capable
2025-04-06 13:25:42 +02:00
CyrIng
0933a336be
[Intel] Merge branch 'Arrow_Lake'
2025-04-05 11:44:22 +02:00
CyrIng
a8489b5858
[Intel][ARL] Merged the P-core and E-core monitoring loops
2025-04-05 00:42:39 +02:00
CyrIng
7613b1bf69
[Intel][ARL] Get/Set L1_NPP_Prefetch from MSR_MISC_FEATURE_CONTROL
2025-04-04 23:42:26 +02:00
CyrIng
a63ed85cf0
[Intel] Provide monitoring functions to Arrow Lake
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* Also applying to Lunar Lake
2025-04-04 00:25:24 +02:00
CyrIng
cd9d961dd8
[Intel] Grant ODCM and PWR MGMT accesses to MTL, ARL, Lunar Lake
2025-04-03 20:50:16 +02:00
CyrIng
5c620b7f42
[Build] of_root defined since Kernel 3.19
2025-04-02 14:54:47 +02:00
CyrIng
46007a9fc8
[Intel][ARL] New features branch to test with Core Ultra 7 265K
2025-04-02 13:58:08 +02:00
CyrIng
a41692a820
[AMD] Adding "Strix Halo" and "Krackan Point" architectures
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* Adding "Fire Range" series
* Adding Ryzen Z2 series
2025-04-01 17:00:31 +02:00
CyrIng
17886cba2b
[Build] Replaced inline C functions with static or macro
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* Kernel 6.14 `node_to_amd_nb()` workaround
2025-03-31 16:49:47 +02:00
CyrIng
a44d56c315
Merge branch 'hotfix_optimizations'
2025-03-31 12:16:27 +02:00
CyrIng
f97a8b41e9
[riscv64] Fill with the Machine Architecture ID Register marchid
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[ppc64] Added source comment
2025-03-29 12:46:48 +01:00
CyrIng
c0942e22c6
[riscv64][ppc64] Improving Hybrid processor detection
2025-03-28 19:58:14 +01:00
CyrIng
9a9a9651e8
[Build] Added CONFIG_ACPI_CPPC_LIB to conditionnaly build EPP
2025-03-26 14:10:27 +01:00
CyrIng
ccbd931816
[ppc64] Fix the Carry flag asm code
2025-03-24 20:01:48 +01:00
CyrIng
1d39401900
[ppc64] The processor version register (PVR) is a 32-bit register
2025-03-23 10:58:07 +01:00
CyrIng
f300d888fc
[ppc64] Use MFXER to get the XER
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* Raise the Carry Flag
2025-03-22 14:57:35 +01:00
CyrIng
73d1856d4a
uBench: Code clean-up
2025-03-22 09:18:09 +01:00
CyrIng
f16fdf303c
[ppc64][riscv64] ASM instructions for uBench macros
2025-03-21 21:18:15 +01:00
CyrIng
d01cc84f0b
[aarch64] Checking CSSELR and CCSIDR registers in ARMv9
2025-03-19 23:24:56 +01:00
CyrIng
33b50d0a2b
[aarch64] If FEAT_CCIDX implemented read NumSets from upper reg
2025-03-19 17:26:50 +01:00
CyrIng
d54e1b8c56
[aarch64] Safely access the PMU registers
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* Detect the Android AVF hypervisor
* Comment PMC in uBench macros
2025-03-19 13:21:26 +01:00
