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• d2fd467fdf [AMD][Zen5] Introduced a UMC capabilities decoder for STX families master CyrIng 2025-07-16 04:46:04 +02:00
• edc23f20c7 [CI] Comment out the unreachable debian-10-buster CyrIng 2025-07-13 10:21:35 +02:00
• aa140f5c1c [AMD][Zen5][STX/KRK/STXH] Avoid undefined COF and Power registers CyrIng 2025-07-13 09:19:17 +02:00
• 638faa37cc [AMD] Switch Zen5/Strix families to the Raphael voltage decoder CyrIng 2025-07-10 12:04:56 +02:00
• 1a7d0751b0 [AMD][Zen5/Strix Halo] Probe Memory Controller from DID 0x12b8 CyrIng 2025-07-10 11:21:01 +02:00
• d0775f73c2 [Build] Enforce targets are not built more than necessary CyrIng 2025-07-09 18:52:27 +02:00
• a5ca660a50 [Build] Clarify Makefile help, info, and version targets CyrIng 2025-07-09 12:43:31 +02:00
• 7d00073f0e [Build][aarch64] Temperature compilation based on CONFIG_THERMAL CyrIng 2025-07-08 09:22:50 +02:00
• a9bd15efe3 [aarch64] Getting temperature from the Generic Thermal Management CyrIng 2025-07-07 16:39:47 +02:00
• 35f9a9c384 [AMD][Zen5][Strix Halo] Adding the RYZEN AI MAX 385 CyrIng 2025-06-30 23:24:12 +02:00
• 14ff2c58b7 [AMD] Add fallback TjMax for legacy CPU families CyrIng 2025-06-29 12:35:02 +02:00
• deb3da7f00 [AMD] Add missing DCU and XPROC_LEAK bitmasks on legacy processors CyrIng 2025-06-23 19:36:46 +02:00
• 396c8dc7ce [AMD][Excavator] Fix setting the scope of temperature to Package CyrIng 2025-06-23 14:57:58 +02:00
• d1a61cb80d [aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state CyrIng 2025-06-23 09:14:59 +02:00
• 78b27bb575 [Build] Support building CoreFreq binaries individually or together CyrIng 2025-06-22 13:03:15 +02:00
• 2ca0adf748 [CR] In _F4() cast complement mask to the type of bit argument CyrIng 2025-06-21 19:27:41 +02:00
• 633c8519a6 [UI] Rephrased string for the CPUID.80000001.ECX[27] feature CyrIng 2025-06-21 12:31:59 +02:00
• f618ffb4f8 [UI] Optimize POWERED() macro with branchless 3-state array lookup CyrIng 2025-06-21 10:55:45 +02:00
• 743135c206 [aarch64] Provide the state of WFI/WFE Low Power Methods CyrIng 2025-06-20 22:48:45 +02:00
• 40a47f225a [aarch64] Set the UI comment for PMULL instruction CyrIng 2025-06-16 18:36:26 +02:00
• dd9886812e [aarch64] Registers requiring a safe access guard (TID3) CyrIng 2025-06-14 13:27:49 +02:00
• efb383dd5a [aarch64] Drop Experimental guard to safely read ID_AA64MMFR3_EL1 CyrIng 2025-06-14 08:43:01 +02:00
• f16141f14c [aarch64] Display detected Interconnect Technology in UI CyrIng 2025-06-13 19:07:41 +02:00
• 92e070b098 [aarch64] Query Cache Coherent Network|Interconnect via DT CyrIng 2025-06-11 14:56:46 +02:00
• cf4269f0fe [aarch64] Adding multiple Processors and Architectures * Cortex-A320, Cortex-A520, Cortex-A720AE, Cortex-A725, Cortex-R82AE, Cortex-X925, Neoverse N3, Neoverse V3, Neoverse V3AE * ARMv8.1-A, ARMv8.8-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A CyrIng 2025-06-10 22:02:43 +02:00
• 0f682fef43 [aarch64] Assign DSU-RTL version according to detected ARM arch. CyrIng 2025-06-09 21:48:10 +02:00
• 63b9b9c8f4 [aarch64] Improve detection of Mesh interconnect via DT/ACPI CyrIng 2025-06-09 16:15:41 +02:00
• cbc2c206f0 [aarch64] Query CMN either from DeviceTree either from ACPI CyrIng 2025-06-08 16:03:51 +02:00
• 2d078106ad [aarch64] JSON export DSU, CMN, CCI, CCN CyrIng 2025-06-07 21:00:10 +02:00
• 4cdca0e8f1 [aarch64] Display the presence of the DynamIQ Shared Unit (DSU) CyrIng 2025-06-07 16:29:25 +02:00
• a0dd03153f [aarch64] Added SMT and big.LITTLE labels in the UI footer CyrIng 2025-06-07 15:16:58 +02:00
• 3a7c7033f2 [Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16 2.0.7 CyrIng 2025-06-05 20:46:55 +02:00
• b6223385b9 [AMD] Decodes voltages of Phoenix families using Rembrandt SVI 2.0.6 CyrIng 2025-06-04 12:59:45 +02:00
• c2e28ed3ee [AMD][Raphael] Attempt to read the SoC voltage CyrIng 2025-05-31 11:46:19 +02:00
• 90d4825ad0 [Kernel][6.15] Fix missing cpufreq_get_policy and asm/amd/nb.h CyrIng 2025-05-31 10:05:27 +02:00
• 2c03ceab46 [AMD][Raphael] Don't probe the HSMP on Desktop/Mobile/Embedded CyrIng 2025-05-30 08:31:18 +02:00
• dfac22ae8a [Doc] Obfuscate support email format in README and CLI usage CyrIng 2025-05-29 09:12:38 +02:00
• 0974aceba3 [Doc] Added command line usage instructions to the README CyrIng 2025-05-29 08:53:41 +02:00
• 6b7ea15142 [aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables CyrIng 2025-05-28 15:17:58 +02:00
• 6b176cd026 [Kernel] Use VM_DONTEXPAND in mmap() for stability and isolation CyrIng 2025-05-28 07:01:03 +02:00
• 989036f384 [Intel] Added the Bartlett Lake/S entry * Clearwater Forest architecture name fix CyrIng 2025-05-26 13:44:53 +02:00
• 5ec7b7c743 [AMD][Genoa] Attempt to read SOC voltage * Apply monitoring interval in RAM consumption calculation 2.0.5 CyrIng 2025-05-24 11:55:12 +02:00
• 094c2f3c27 [Kernel] If version is >= 6.0 then call SMU via CONFIG_AMD_NB Ryzen 9950X issue #548 CyrIng 2025-05-22 20:22:39 +02:00
• a3b978a2d3 [Code Review] Make module parameters load-time only (#547) CyrIng 2025-05-22 19:19:09 +02:00
• 6a99cfb4b4 [x86_64] Add lock prefix to bit ops for cross-package atomicity CyrIng 2025-05-20 21:54:11 +02:00
• 2569ef0518 [aarch64][riscv64][ppc64] Improving the CPU topology to detect BSP CyrIng 2025-05-19 20:50:18 +02:00
• e7deead548 [Code Review] Intel Core Ultra: Registers name and address updated CyrIng 2025-05-18 12:30:34 +02:00
• c3704a245a [Intel][ADL/N] Adding "Twin Lake" and "Amston Lake" codenames CyrIng 2025-05-16 23:04:51 +02:00
• 398dc12544 [AMD][Zen] Count DIMM ranks from the enabled chip select 2.0.3 CyrIng 2025-05-14 14:33:59 +02:00
• fcc0e0f70e [AMD][Zen][UMC] Computes DIMM ranks based on DDR type CyrIng 2025-05-12 17:13:28 +02:00
• 347045ed17 Revert "[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98" CyrIng 2025-05-12 15:37:08 +02:00
• e684e642d0 [UI] Increased length of L3 cache digits in header CyrIng 2025-05-12 12:12:29 +02:00
• c2b396a215 [AMD][Zen] Now conducts Datafabric calls through Kernel PCI [HSMP] Provides its own lock rather than SMN' lock CyrIng 2025-05-12 11:55:34 +02:00
• 22f9c460a9 [AMD][Zen] HSMP arguments index fix in CONFIG_AMD_NB build mode CyrIng 2025-05-11 13:03:04 +02:00
• acbe192ad5 [AMD][Zen] Replaced package thermal with a pointer function CyrIng 2025-05-10 18:11:05 +02:00
• 43fd828bdc [AMD][Genoa] Probe up to four memory controllers CyrIng 2025-05-10 15:11:21 +02:00
• 0729f349e4 [AMD] Improved EPYC Genoa support * CCD and CCX topology fixed to compute the right thermal SMU address * Increase BIT_IO_RETRIES_COUNT to parallelize HSMP_RD_DIMM_PWR calls * Added specifics for an "Eng Sample" of Genoa architecture CyrIng 2025-05-09 19:44:16 +02:00
• 93c7096e2b [Code Review] Refactored variable names for inclusivity CyrIng 2025-05-08 11:17:40 +02:00
• 511fa2fe4d [AMD][Genoa] Accumulate the power consumed by RAM CyrIng 2025-05-04 18:22:35 +02:00
• e5a5d0c1d6 [AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98 CyrIng 2025-05-04 07:18:23 +02:00
• e3bb96bf85 [x86_64] Order SMBIOS DIMM list by channel CyrIng 2025-05-04 06:56:49 +02:00
• d94626d276 [IMC] Can display Twelve Channel memory controller * Renamed Disabled to Undefined channels CyrIng 2025-05-03 17:48:32 +02:00
• e9eed278f0 [x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots CyrIng 2025-05-03 16:42:40 +02:00
• 638883766b [Kernel] VT-d: request memory region before use CyrIng 2025-05-01 09:39:10 +02:00
• adf8cbadc5 [AMD][Hawk Point] Set AddrCfg & DimmCfg addresses for Phoenix UMC CyrIng 2025-04-27 11:28:24 +02:00
• de901592a2 [AMD][Genoa] Attempt to monitor DIMM power consumption from HSMP * Specifications of some Zen registers CyrIng 2025-04-27 10:58:53 +02:00
• b4903129ac [AMD][Family 1Ah] Added the HSMP for EPYC Turin * Check mailbox protocol is correctly functioning * using the arithmetic addition 2 + 1 = 3 CyrIng 2025-04-19 13:46:46 +02:00
• c508b7d3f1 [CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number CyrIng 2025-04-18 14:48:51 +02:00
• 063fb88127 [CLI][x86_64] Compute the SMBIOS DIMM part number (rev 2) CyrIng 2025-04-18 14:06:13 +02:00
• 916546f4cb [x86_64] Check HCF capability for MPERF/APERF MSR access in VM CyrIng 2025-04-16 14:21:47 +02:00
• 7064970173 [AMD][EPYC][Genoa] Use generic voltage & power CyrIng 2025-04-13 10:50:04 +02:00
• 2171321cf6 [Doc] README for Rocky Linux and Clear Linux CyrIng 2025-04-12 11:21:35 +02:00
• 2cce3ed28d [Build] Prevent module loading if detected CPU count > CORE_COUNT CyrIng 2025-04-12 09:37:20 +02:00
• 6509cc4ba8 [Build] Make static the PCI list to comply with kernel frame size CyrIng 2025-04-10 20:14:46 +02:00
• f055e6acad [Intel][MTL][ARL] Improving MC Bus and DDR speed to follow OC SOC CyrIng 2025-04-09 21:55:45 +02:00
• 812f297a22 [Build] Kernel 6.15 is switching to use hrtimer_setup() CyrIng 2025-04-09 09:54:20 +02:00
• 4600e91f5b [CI] Bump to uraimo version 3 CyrIng 2025-04-07 13:53:25 +02:00
• b838bf059d [Intel][MTL][ARL] Refactored IMC decoder to query DDR clock CyrIng 2025-04-07 12:57:52 +02:00
• ef11110bb7 [UI] Display N/A when Intel processor is not HDC capable CyrIng 2025-04-06 13:25:42 +02:00
• 0933a336be [Intel] Merge branch 'Arrow_Lake' CyrIng 2025-04-05 11:44:22 +02:00
• a8489b5858 [Intel][ARL] Merged the P-core and E-core monitoring loops CyrIng 2025-04-05 00:42:39 +02:00
• 7613b1bf69 [Intel][ARL] Get/Set L1_NPP_Prefetch from MSR_MISC_FEATURE_CONTROL CyrIng 2025-04-04 23:42:26 +02:00
• a63ed85cf0 [Intel] Provide monitoring functions to Arrow Lake * Also applying to Lunar Lake CyrIng 2025-04-04 00:25:24 +02:00
• cd9d961dd8 [Intel] Grant ODCM and PWR MGMT accesses to MTL, ARL, Lunar Lake CyrIng 2025-04-03 20:50:16 +02:00
• 5c620b7f42 [Build] of_root defined since Kernel 3.19 CyrIng 2025-04-02 14:54:47 +02:00
• 46007a9fc8 [Intel][ARL] New features branch to test with Core Ultra 7 265K CyrIng 2025-04-02 13:58:08 +02:00
• a41692a820 [AMD] Adding "Strix Halo" and "Krackan Point" architectures * Adding "Fire Range" series * Adding Ryzen Z2 series CyrIng 2025-04-01 17:00:31 +02:00
• 17886cba2b [Build] Replaced inline C functions with static or macro * Kernel 6.14 node_to_amd_nb() workaround CyrIng 2025-03-31 16:49:47 +02:00
• a44d56c315 Merge branch 'hotfix_optimizations' CyrIng 2025-03-31 12:16:27 +02:00
• f97a8b41e9 [riscv64] Fill with the Machine Architecture ID Register marchid [ppc64] Added source comment CyrIng 2025-03-29 12:46:48 +01:00
• c0942e22c6 [riscv64][ppc64] Improving Hybrid processor detection CyrIng 2025-03-28 19:58:14 +01:00
• 9a9a9651e8 [Build] Added CONFIG_ACPI_CPPC_LIB to conditionnaly build EPP CyrIng 2025-03-26 14:10:27 +01:00
• ccbd931816 [ppc64] Fix the Carry flag asm code CyrIng 2025-03-24 20:01:48 +01:00
• 1d39401900 [ppc64] The processor version register (PVR) is a 32-bit register CyrIng 2025-03-23 10:58:07 +01:00
• f300d888fc [ppc64] Use MFXER to get the XER * Raise the Carry Flag CyrIng 2025-03-22 14:57:35 +01:00
• 73d1856d4a uBench: Code clean-up CyrIng 2025-03-22 09:18:09 +01:00
• f16fdf303c [ppc64][riscv64] ASM instructions for uBench macros CyrIng 2025-03-21 21:18:15 +01:00
• d01cc84f0b [aarch64] Checking CSSELR and CCSIDR registers in ARMv9 CyrIng 2025-03-19 23:24:56 +01:00
• 33b50d0a2b [aarch64] If FEAT_CCIDX implemented read NumSets from upper reg CyrIng 2025-03-19 17:26:50 +01:00
• d54e1b8c56 [aarch64] Safely access the PMU registers * Detect the Android AVF hypervisor * Comment PMC in uBench macros CyrIng 2025-03-19 13:21:26 +01:00