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[AArch64] Processor Feature Register 2 AA64PFR2_EL1

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CyrIng
2024-12-06 21:47:42 +01:00
parent b10395cd02
commit a33aa70778
8 changed files with 134 additions and 4 deletions
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8
aarch64/arm_reg.h
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@@ -10,6 +10,7 @@
#define ID_AA64MMFR3_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011)
#define ID_AA64SMFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101)
#define ID_AA64ZFR0_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100)
#define ID_AA64PFR2_EL1 sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b010)
#define SCTLR2_EL1 sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011)
#define MRS_SSBS2 sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110)
#define MRS_PAN sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011)
@@ -19,6 +20,7 @@
#define MRS_ALLINT sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b000)
#define MRS_PM sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b001)
#define MRS_SVCR sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b010)
#define MRS_FPMR sys_reg(0b11, 0b011, 0b0100, 0b0100, 0b010)
#define AMCGCR_EL0 sys_reg(0b11, 0b011, 0b1101, 0b0010, 0b010)
#define CLUSTERCFR_EL1 sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b000)
#define CLUSTERIDR_EL1 sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b001)
@@ -653,9 +655,11 @@ typedef union
MTEPERM : 4-0,
MTESTOREONLY : 8-4,
MTEFAR : 12-8,
RES0 : 32-12,
RES0 : 16-12,
UINJ : 20-16,
RES1 : 32-20,
FPMR : 36-32,
RES1 : 64-36;
RES2 : 64-36;
};
} AA64PFR2;

5
aarch64/corefreq-cli-rsc-en.h
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@@ -958,11 +958,15 @@
#define RSC_FEATURES_DIT_CODE_EN "Data Independent Timing"
#define RSC_FEATURES_EXS_CODE_EN "Context Synchronization & Exception Handling"
#define RSC_FEATURES_FGT_CODE_EN "Fine-Grained Trap controls"
#define RSC_FEATURES_FPMR_CODE_EN "Floating-point Mode Register"
#define RSC_FEATURES_PFAR_CODE_EN "Physical Fault Address Registers"
#define RSC_FEATURES_GCS_CODE_EN "Guarded Control Stack"
#define RSC_FEATURES_GIC_CODE_EN "Generic Interrupt Controller"
#define RSC_FEATURES_MPAM_CODE_EN "Memory Partitioning and Monitoring"
#define RSC_FEATURES_MTE_CODE_EN "Memory Tagging Extension"
#define RSC_FEATURES_MTE_FAR_CODE_EN "Reporting Tag Check Fault"
#define RSC_FEATURES_MTE_PERM_CODE_EN "Allocation tag access permissions"
#define RSC_FEATURES_MTE_STOREONLY_CODE_EN "Store-only Tag checking"
#define RSC_FEATURES_NMI_CODE_EN "Non Maskable Interrupt"
#define RSC_FEATURES_PA_CODE_EN "Physical Address range"
#define RSC_FEATURES_PAN_CODE_EN "Privileged Access Never"
@@ -974,6 +978,7 @@
#define RSC_FEATURES_TME_CODE_EN "Transactional Memory Extension"
#define RSC_FEATURES_TSC_CODE_EN "Time Stamp Counter"
#define RSC_FEATURES_UAO_CODE_EN "User Access Override"
#define RSC_FEATURES_UINJ_CODE_EN "Injection of Undefined Instruction"
#define RSC_FEATURES_VA_CODE_EN "Virtual Address range"
#define RSC_FEATURES_VHE_CODE_EN "Virtualization Host Extensions"
#define RSC_FEAT_SECTION_MECH_CODE_EN "Mitigation mechanisms"

13
aarch64/corefreq-cli-rsc-fr.h
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@@ -640,6 +640,7 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_FEATURES_FGT_CODE_FR \
"Contr""\xb4""les de Pi""\xa8""ges ""\xa0"" Granularit""\xa9"" Fine"
#define RSC_FEATURES_FPMR_CODE_FR "Registre de mode de la virgule flottante"
#define RSC_FEATURES_PFAR_CODE_FR \
"Registres de D""\xa9""faut d'Adresse Physique"
@@ -650,11 +651,18 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
"Contr""\xb4""leur d'interruption g""\xa9""n""\xa9""rique"
#define RSC_FEATURES_MTE_CODE_FR \
"Extension de marquage de m""\xa9""moire"
"Extension de marquage de la m""\xa9""moire"
#define RSC_FEATURES_MPAM_CODE_FR \
"Partitionnement et supervision de la m""\xa9""moire"
#define RSC_FEATURES_MTE_FAR_CODE_FR "Signaler Tag Check Fault"
#define RSC_FEATURES_MTE_PERM_CODE_FR \
"Droits d'acc""\xa8""s aux balises d'allocation"
#define RSC_FEATURES_MTE_STOREONLY_CODE_FR \
"V""\xa9""rification de la balise Store-only"
#define RSC_FEATURES_NMI_CODE_FR "Interruption non masquable"
#define RSC_FEATURES_PA_CODE_FR "Plage d'Adressage Physique"
#define RSC_FEATURES_PAN_CODE_FR "Aucun privil""\xa8""ge d'acc""\xa8""s"
@@ -676,6 +684,9 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_FEATURES_UAO_CODE_FR \
"Surcharge de l'acc""\xa8""s utilisateur"
#define RSC_FEATURES_UINJ_CODE_FR \
"Injection d'instructions non d""\xa9""finies"
#define RSC_FEATURES_VA_CODE_FR "Plage d'adressage virtuel"
#define RSC_FEATURES_VHE_CODE_FR \
"Extensions d'H""\xb4""te de Virtualisation"

5
aarch64/corefreq-cli-rsc.c
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@@ -941,11 +941,15 @@ RESOURCE_ST Resource[] = {
LDT(RSC_FEATURES_DIT),
LDT(RSC_FEATURES_EXS),
LDT(RSC_FEATURES_FGT),
LDT(RSC_FEATURES_FPMR),
LDT(RSC_FEATURES_PFAR),
LDT(RSC_FEATURES_GCS),
LDT(RSC_FEATURES_GIC),
LDT(RSC_FEATURES_MPAM),
LDT(RSC_FEATURES_MTE),
LDT(RSC_FEATURES_MTE_FAR),
LDT(RSC_FEATURES_MTE_PERM),
LDT(RSC_FEATURES_MTE_STOREONLY),
LDT(RSC_FEATURES_NMI),
LDT(RSC_FEATURES_PA),
LDT(RSC_FEATURES_PAN),
@@ -957,6 +961,7 @@ RESOURCE_ST Resource[] = {
LDT(RSC_FEATURES_TME),
LDT(RSC_FEATURES_TSC),
LDT(RSC_FEATURES_UAO),
LDT(RSC_FEATURES_UINJ),
LDT(RSC_FEATURES_VA),
LDT(RSC_FEATURES_VHE),
LDT(RSC_FEAT_SECTION_MECH),

5
aarch64/corefreq-cli-rsc.h
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@@ -764,11 +764,15 @@ enum {
RSC_FEATURES_DIT,
RSC_FEATURES_EXS,
RSC_FEATURES_FGT,
RSC_FEATURES_FPMR,
RSC_FEATURES_PFAR,
RSC_FEATURES_GCS,
RSC_FEATURES_GIC,
RSC_FEATURES_MPAM,
RSC_FEATURES_MTE,
RSC_FEATURES_MTE_FAR,
RSC_FEATURES_MTE_PERM,
RSC_FEATURES_MTE_STOREONLY,
RSC_FEATURES_NMI,
RSC_FEATURES_PA,
RSC_FEATURES_PAN,
@@ -780,6 +784,7 @@ enum {
RSC_FEATURES_TME,
RSC_FEATURES_TSC,
RSC_FEATURES_UAO,
RSC_FEATURES_UINJ,
RSC_FEATURES_VA,
RSC_FEATURES_VHE,
RSC_FEAT_SECTION_MECH,

41
aarch64/corefreq-cli.c
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@@ -2732,6 +2732,14 @@ REASON_CODE SysInfoFeatures( Window *win,
width - 19 - RSZ(FEATURES_FGT),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.FPMR == 1,
attr_Feat,
2, "%s%.*sFPMR [%7s]", RSC(FEATURES_FPMR).CODE(),
width - 19 - RSZ(FEATURES_FPMR),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.PFAR == 1,
@@ -2781,6 +2789,31 @@ REASON_CODE SysInfoFeatures( Window *win,
RSC(FEATURES_MTE).CODE(), width - 21 - RSZ(FEATURES_MTE),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.MTE_FAR == 1,
attr_Feat,
3, "%s%.*sTAGGED_FAR [%7s]", RSC(FEATURES_MTE_FAR).CODE(),
width - (OutFunc == NULL ? 28:26) - RSZ(FEATURES_MTE_FAR),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.MTE_PERM == 1,
attr_Feat,
3, "%s%.*sPERM [%7s]", RSC(FEATURES_MTE_PERM).CODE(),
width - (OutFunc == NULL ? 22:20) - RSZ(FEATURES_MTE_PERM),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.MTE_STOREONLY == 1,
attr_Feat,
3, "%s%.*sSTOREONLY [%7s]",
RSC(FEATURES_MTE_STOREONLY).CODE(),
width - (OutFunc == NULL ? 27:25) - RSZ(FEATURES_MTE_STOREONLY),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.NMI == 1,
@@ -2874,6 +2907,14 @@ REASON_CODE SysInfoFeatures( Window *win,
width - 18 - RSZ(FEATURES_UAO),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.UINJ == 1,
attr_Feat,
2, "%s%.*sUINJ [%7s]", RSC(FEATURES_UINJ).CODE(),
width - 19 - RSZ(FEATURES_UINJ),
NULL
},
{
NULL,
RO(Shm)->Proc.Features.VARange <= 0b10,

54
aarch64/corefreqk.c
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@@ -524,6 +524,7 @@ static void Query_Features(void *pArg)
volatile AA64MMFR2 mmfr2;
volatile AA64PFR0 pfr0;
volatile AA64PFR1 pfr1;
volatile AA64PFR2 pfr2;
volatile MVFR0 mvfr0;
volatile MVFR1 mvfr1;
volatile MVFR2 mvfr2;
@@ -1424,6 +1425,55 @@ static void Query_Features(void *pArg)
iArg->Features->PFAR = 0;
break;
}
pfr2.value = SysRegRead(ID_AA64PFR2_EL1);
switch(pfr2.FPMR) {
case 0b0001:
iArg->Features->FPMR = 1;
break;
case 0b0000:
default:
iArg->Features->FPMR = 0;
break;
}
switch(pfr2.UINJ) {
case 0b0001:
iArg->Features->UINJ = 1;
break;
case 0b0000:
default:
iArg->Features->UINJ = 0;
break;
}
switch(pfr2.MTEFAR) {
case 0b0001:
iArg->Features->MTE_FAR = 1;
break;
case 0b0000:
default:
iArg->Features->MTE_FAR = 0;
break;
}
switch(pfr2.MTESTOREONLY) {
case 0b0001:
iArg->Features->MTE_STOREONLY = 1;
break;
case 0b0000:
default:
iArg->Features->MTE_STOREONLY = 0;
break;
}
switch(pfr2.MTEPERM) {
case 0b0001:
iArg->Features->MTE_PERM = 1;
break;
case 0b0000:
default:
iArg->Features->MTE_PERM = 0;
break;
}
if (iArg->Features->SVE | iArg->Features->SME)
{
volatile AA64ZFR0 zfr0 = {.value = SysRegRead(ID_AA64ZFR0_EL1)};
@@ -2812,6 +2862,10 @@ static void SystemRegisters(CORE_RO *Core)
:
: "cc", "memory"
);
if (PUBLIC(RO(Proc))->Features.FPMR) {
volatile unsigned long long fpmr = SysRegRead(MRS_FPMR);
UNUSED(fpmr); /*TODO*/
}
BITSET_CC(LOCKLESS, PUBLIC(RO(Proc))->CR_Mask, Core->Bind);
}

7
aarch64/coretypes.h
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@@ -1015,7 +1015,12 @@ typedef struct /* BSP features. */
SIMD_Int : 37-36,
SIMD_LS : 38-37,
SIMD_Misc : 39-38,
_Unused1_ : 64-39;
FPMR : 40-39,
UINJ : 41-40,
MTE_FAR : 42-41,
MTE_STOREONLY : 43-42,
MTE_PERM : 44-43,
_Unused1_ : 64-44;
Bit64 InvariantTSC : 8-0,
HyperThreading : 9-8,