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Author SHA1 Message Date
CyrIng
54a044fdfa [Intel][ADL] Process channels differently depending on DDR4 or DDR5 2024-08-02 17:48:00 +02:00
CyrIng
e662297c8f [Intel][ADL] Cherry-pick the MC Virtual Channel Count 2024-08-02 17:22:49 +02:00
CyrIng
6401e7d2bc [Intel] 12th to 14th generation IMC decoder refactoring 2024-08-02 09:33:02 +02:00
CyrIng
0516c27578 [Intel][ADL ... MTL] Adding Memory Controller Virtual Channel Count 
There are two instances of MC, one per memory slice.
 Each controller is capable of supporting up to four channels of
 LPDDR4x and LPDDR5/x, two channels of DDR5 and one channel of DDR4
 2024-08-01 13:05:39 +02:00
CyrIng
a049516707 [Intel][ADL ... MTL] Channel count as a function of DDPCD DDR_TYPE 
`DDPCD`: Two DIMMs Per Channel Enable
`DDR_TYPE`: DDR4 for 1 channel ; DDR5,LPDDR5,LPDDR4 for 2 channels
 2024-07-31 13:42:56 +02:00
CyrIng
fdb74e7c1f [Intel][ADL ... MTL] Keep all enabled memory controllers 2024-07-31 12:11:59 +02:00
CyrIng
36adf0e855 [Intel][12th ++] Compute tWR quantity as a function of DDR version 2024-07-30 13:32:50 +02:00
CyrIng
0db6f0a18d [Build] CPU-Freq build against Linux Kernel version 6.11 2024-07-30 11:17:41 +02:00
CyrIng
9024a4d577 [AMD] Configure TjMax for multiple Ryzen and Threadripper 2024-07-30 02:31:34 +02:00
CyrIng
0308f9bb3c [CR] Optimize AMD temperature filtering function 2024-07-29 17:03:01 +02:00
CyrIng
6ab42d059f [AMD][Zen5] Introducing the Eldora architecture aka "Granite Ridge" 2024-07-27 14:31:21 +02:00
CyrIng
0075d57311 [AMD][Zen5] Adding entries for Strix Point 2024-07-26 14:25:26 +02:00
CyrIng
5aefb1b6c9 [Build] Change dkms configuration to install into /usr/bin/ 1.98.0 2024-07-24 02:48:28 +02:00
CyrIng
1804887cc7 [Intel][Raptor Lake] Adding the HB DID of i7-14700K' IMC 2024-07-23 09:05:06 +02:00
CyrIng
a03489feb3 [Build] solved from Fedora using RHEL MINOR version number 99 2024-07-20 12:38:30 +02:00
CyrIng
c258c1aca6 [AArch64] Optimizing the Vcore seek 2024-07-17 14:41:03 +02:00
CyrIng
53176beef7 [AMD][Zen4][Raphael] Adding the EPYC 4004 Series 2024-07-13 13:21:11 +02:00
CyrIng
cad12cead2 [AMD][Zen4] Clarify Hawk Point and Phoenix-Refresh architectures 2024-07-13 07:00:10 +02:00
CyrIng
9235fb32ec [AArch64] Workaround to Package discrete voltage: the highest Vcore 2024-07-09 20:13:58 +02:00
CyrIng
4c4e5c77b5 [CR] Fixed some compilation warnings 2024-07-09 19:11:15 +02:00
CyrIng
c07a2e2b04 [AArch64] Improving computation of Euclidean division 2024-07-09 05:52:24 +02:00
CyrIng
c0367b9325 [AArch64] Adjust frequency division in CNTFRQ and PMU counters 2024-07-08 18:37:14 +02:00
CyrIng
6dce6262ee [AArch64] Scale a frequency factor from the interval 2024-07-07 13:06:49 +02:00
CyrIng
a69dff0048 [AArch64] Refactoring the frequency ratios for decimal precision 2024-07-07 01:06:00 +02:00
CyrIng
2ded4e40fb [AMD][Family 19h] New voltage formula assigned to model 61h 
* Vcore activated
* Voltage SoC deactivated
 2024-06-30 15:16:07 +02:00
CyrIng
c0d1a68497 [AArch64] Compile dev_pm_opp_put if Kernel greater or equal 4.11 2024-06-29 22:01:59 +02:00
CyrIng
89ba739379 [AArch64] Get the voltage core of CPUs from OPP 2024-06-29 21:43:32 +02:00
CyrIng
43b96ae67e [AMD][Zen] Prevent the calculation of negative temperature (#496) 2024-06-25 00:39:29 +02:00
CyrIng
f7b0eacbd5 [Family 18h] Hygon C86 7375 
[AMD] Fixed some typos
 2024-06-24 19:54:25 +02:00
CyrIng
927ae0b9dd [Intel] Mitigation mechanism: GDS_NO; RFDS_NO; MONITOR_MITG_NO 
* Intel SDM Documentation Changes
 2024-06-23 12:52:47 +02:00
CyrIng
fc3fa800cb [AMD][Family 19h] PStateDef specification: Adding VID[8] bit 32 
* Specification of MSR `HW_PSTATE_STATUS`
 2024-06-22 19:39:34 +02:00
CyrIng
7c8d354aee [CR] Fix memory allocation in kernel pages for the SysGate 2024-06-16 16:13:39 +02:00
CyrIng
e6d383a5ac [Build] Workaround to musl change in basename (#494) 2024-06-16 12:51:26 +02:00
CyrIng
8ce563e331 [CLI] Display the state of the Memory Management Unit (MMU) 2024-06-15 18:06:10 +02:00
CyrIng
9a82942ccd [Kernel] Created C2U_Enable as a parameter alias of C1U_Enable 2024-06-15 15:31:48 +02:00
CyrIng
d58f420aae [CLI] State of Instruction Cache Unit I$ and Data Cache Unit D$ 2024-06-15 09:45:04 +02:00
CyrIng
5b9dc1124a [Doc] UI_RULER_MINIMUM & UI_RULER_MAXIMUM Makefile macros 2024-06-09 18:11:54 +02:00
CyrIng
9b644fd509 [CLI] UI_RULER_MINIMUM & UI_RULER_MAXIMUM building constraints 2024-06-09 11:30:31 +02:00
CyrIng
332dbdac52 Revert "[CLI] Responsive ruler to architectural context" 
This reverts commit 4bc38d696f.
 2024-06-08 22:47:50 +02:00
CyrIng
c462e2f351 [x86_64] AMD Boost and P-States redesigned 2024-06-08 21:30:40 +02:00
CyrIng
71deb150ab [Intel][MTL] Fix CMD Stretch bit range width 2024-06-08 08:04:38 +02:00
CyrIng
b8a6c5e850 [UI] Hardening missing console/terminal size 2024-06-08 06:50:11 +02:00
CyrIng
3e136b3cb2 [AArch64] Build with Redhat RHEL version 9 2024-06-07 21:13:13 +02:00
CyrIng
4bc38d696f [CLI] Responsive ruler to architectural context 2024-06-06 08:16:37 +02:00
CyrIng
f622261545 [Intel] Added method CLOCK_FLEX_MAX with Xeon's Nehalem & Core 2 
* Grants full `MSR_FLEX_RATIO` access to tested architectures:
- Alder Lake/S
- Tiger Lake/U
- Westmere/Gulftown
 2024-06-02 16:40:40 +02:00
CyrIng
db15a83fb8 [Intel] Provides the overclocking bins with unlocked processors 2024-06-01 22:53:48 +02:00
CyrIng
dbc0e1efb3 [Intel] Query the Overclocking bit (OC) from Capabilities 2024-06-01 02:32:59 +02:00
CyrIng
cf26a206d5 [CLI] Make HDCP meaning string shorter 2024-05-31 08:59:26 +02:00
CyrIng
18d3229183 [Intel] Adding technologies: VMD, HDCP, IPU and VPU 
* Volume Management Device
* High-Bandwidth Digital Content Protection
* Image Processing Unit
* Vision Processing Unit
 2024-05-29 23:15:33 +02:00
CyrIng
23a01f498c [Intel] Gaussian & Neural Accelerator - GNA technology 
* Renamed Gemini Lake structures
 2024-05-29 16:00:56 +02:00