[RISC-V] Preliminary port of the riscv64 architecture

riscv64/bitasm.h

@@ -0,0 +1,845 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#define FEAT_MESSAGE(_msg)		_Pragma(#_msg)
+#define FEAT_MSG(_msg)			FEAT_MESSAGE(message(#_msg))
+
+enum {
+	SYNC	=  0,
+	SYNC0	= 10,
+	SYNC1	= 11,
+	BURN	= 31,
+	COMP0	= 40,
+	COMP1	= 41,
+	NTFY0	= 50,
+	NTFY1	= 51,
+	NTFY	= 63
+};
+
+#define BIT_MASK_SYNC							\
+	0b0000000000000000000000000000000000000000000000000000110000000000LLU
+
+#define BIT_MASK_COMP							\
+	0b0000000000000000000000110000000000000000000000000000000000000000LLU
+
+#define BIT_MASK_NTFY							\
+	0b0000000000001100000000000000000000000000000000000000000000000000LLU
+
+#define MAXCOUNTER(M, m)	((M) > (m) ? (M) : (m))
+#define MINCOUNTER(m, M)	((m) < (M) ? (m) : (M))
+
+#define CORE_COUNT_MASK(_cc)	(_cc - 1)
+#define CORE_WORD_TOP(_cc)	(CORE_COUNT_MASK(_cc) >> 6)
+#define CORE_WORD_MOD(_cc_,_offset_) ((_offset_ & CORE_COUNT_MASK(_cc_)) & 0x3f)
+#define CORE_WORD_POS(_cc_,_offset_) ((_offset_ & CORE_COUNT_MASK(_cc_)) >> 6)
+
+typedef unsigned long long int	Bit1024[16];
+typedef unsigned long long int	Bit512[8];
+typedef unsigned long long int	Bit256[4];
+typedef unsigned long long int	Bit128[2];
+typedef unsigned long long int	Bit64;
+typedef unsigned int		Bit32;
+
+#define BitT2(_cc)		Bit##_cc
+#define BitT1(_cc)		BitT2(_cc)
+#define BitCC			BitT1(CORE_COUNT)
+
+#if (CORE_COUNT == 64)
+#define InitCC(_val)		(_val)
+#else
+#define InitCC(_val)		{[0 ... CORE_WORD_TOP(CORE_COUNT) - 1] = _val}
+#endif
+
+#define LOCKLESS LOCK_LESS
+#define BUS_LOCK FULL_LOCK
+
+#define BARRIER(_option)						\
+__asm__ volatile							\
+(									\
+	"fence iorw	, iorw"			"\n\t"			\
+	"fence.i"							\
+	:								\
+	:								\
+	: "memory"							\
+)
+
+#define WBINVD()							\
+__asm__ volatile							\
+(									\
+	"fence.i"							\
+	:								\
+	:								\
+	: "memory"							\
+)
+
+#define SERIALIZE()							\
+__asm__ volatile							\
+(									\
+	"fence.i"							\
+	:								\
+	:								\
+	: "memory"							\
+)
+
+#define RDTSC64(_mem64) 						\
+__asm__ volatile							\
+(									\
+	"csrr	%0	, mcycle"					\
+	: "=r" (_mem64) 						\
+	:								\
+	: "cc", "memory"						\
+)
+
+#define ASM_RDTSC(_reg) 						\
+	"# Read variant TSC."			"\n\t"			\
+	"csrr	" #_reg ",	mcycle" 	"\n\t"
+
+#define ASM_CODE_RDPMC(_ctr, _reg)					\
+	"# Read PMU counter."			"\n\t"			\
+	"csrr	" #_reg ", " #_ctr		"\n\t"			\
+
+#define ASM_RDPMC(_ctr, _reg) ASM_CODE_RDPMC(_ctr, _reg)
+
+#define RDPMC(_ctr, _reg, _mem) 					\
+__asm__ volatile							\
+(									\
+	ASM_CODE_RDPMC(_ctr, _reg)					\
+	"# Store values into memory."		"\n\t"			\
+	"sd	" #_reg ",	%0"					\
+	: "=m" (_mem)							\
+	:								\
+	: "%" #_reg"", 							\
+	  "cc", "memory"						\
+)
+
+#define ASM_RDTSC_PMCx1(_reg0, _reg1,					\
+			_tsc_inst, mem_tsc,				\
+			_ctr1, _mem1)					\
+__asm__ volatile							\
+(									\
+	_tsc_inst(_reg0)						\
+	ASM_RDPMC(_ctr1, _reg1) 					\
+	"# Store values into memory."		"\n\t"			\
+	"sd	" #_reg0 ",	%0"		"\n\t"			\
+	"sd	" #_reg1 ",	%1"					\
+	: "=m" (mem_tsc),	"=m" (_mem1)				\
+	:								\
+	: "%" #_reg0""	,	"%" #_reg1"",				\
+	  "cc", "memory"						\
+)
+
+#define RDTSC_PMCx1(mem_tsc, ...)					\
+ASM_RDTSC_PMCx1(x14, x15, ASM_RDTSC, mem_tsc, __VA_ARGS__)
+
+#define	_BITSET_PRE_INST_FULL_LOCK					\
+	"1:"					"\n\t"			\
+		"lr.d	x31, [%[addr]]" 	"\n\t"
+
+#define	_BITSET_PRE_INST_LOCK_LESS					\
+		"lr.d	x31, [%[addr]]" 	"\n\t"
+
+#define	_BITSET_COMMON_INST						\
+/*		"tst	x11, x12"		"\n\t"			\
+		"cset	w10, ne"		"\n\t"			\
+		"strb	w10, %[ret]"		"\n\t"			\
+		"orr	x11, x11, x12"		"\n\t"*/
+
+#define	_BITSET_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define	_BITSET_POST_INST_LOCK_LESS					\
+/*		"str	x11, [%[addr]]"*/
+
+#define	_BITSET_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%w10", "%x11", "%x12"
+
+#define	_BITSET_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%w10", "%x11", "%x12"
+
+#define _BITSET_GPR(_lock, _base, _offset)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[offset]"	"\n\t"			\
+		_BITSET_PRE_INST_##_lock				\
+		_BITSET_COMMON_INST					\
+		_BITSET_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [offset] "r" (_offset)				\
+		_BITSET_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BITSET_IMM(_lock, _base, _imm6)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[imm6]"	"\n\t"			\
+		_BITSET_PRE_INST_##_lock				\
+		_BITSET_COMMON_INST					\
+		_BITSET_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [imm6] "i" (_imm6)					\
+		_BITSET_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BITCLR_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITCLR_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITCLR_COMMON_INST						\
+/*		"tst	x11, x12"		"\n\t"			\
+		"cset	w10, ne"		"\n\t"			\
+		"strb	w10, %[ret]"		"\n\t"			\
+		"bic	x11, x11, x12"		"\n\t"*/
+
+#define _BITCLR_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITCLR_POST_INST_LOCK_LESS					\
+/*		"str	x11, [%[addr]]"*/
+
+#define _BITCLR_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%w10", "%x11", "%x12"
+
+#define _BITCLR_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%w10", "%x11", "%x12"
+
+#define _BITCLR_GPR(_lock, _base, _offset)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[offset]"	"\n\t"			\
+		_BITCLR_PRE_INST_##_lock				\
+		_BITCLR_COMMON_INST					\
+		_BITCLR_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [offset] "r" (_offset)				\
+		_BITCLR_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BITCLR_IMM(_lock, _base, _imm6)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[imm6]"	"\n\t"			\
+		_BITCLR_PRE_INST_##_lock				\
+		_BITCLR_COMMON_INST					\
+		_BITCLR_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [imm6] "i" (_imm6)					\
+		_BITCLR_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BIT_TEST_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BIT_TEST_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BIT_TEST_COMMON_INST						\
+/*		"tst	x11, x12"		"\n\t"			\
+		"cset	w10, ne"		"\n\t"			\
+		"strb	w10, %[ret]"		"\n\t"*/
+
+#define _BIT_TEST_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BIT_TEST_POST_INST_LOCK_LESS					\
+		"#	NOP"
+
+#define _BIT_TEST_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%w10", "%x11", "%x12"
+
+#define _BIT_TEST_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%w10", "%x11", "%x12"
+
+#define _BIT_TEST_GPR(_lock, _base, _offset)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[offset]"	"\n\t"			\
+		_BIT_TEST_PRE_INST_##_lock				\
+		_BIT_TEST_COMMON_INST					\
+		_BIT_TEST_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [offset] "r" (_offset)				\
+		_BIT_TEST_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BIT_TEST_IMM(_lock, _base, _imm6)				\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		"mov	x12, #1"		"\n\t"			\
+		"lsl	x12, x12, %[imm6]"	"\n\t"			\
+		_BIT_TEST_PRE_INST_##_lock				\
+		_BIT_TEST_COMMON_INST					\
+		_BIT_TEST_POST_INST_##_lock				\
+		: [ret] "=m" (_ret)					\
+		: [addr] "r" (&_base),					\
+		  [imm6] "i" (_imm6)					\
+		_BIT_TEST_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define _BITWISEAND_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEAND_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEAND_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITWISEAND_POST_INST_LOCK_LESS 				\
+		"#	NOP"
+
+#define _BITWISEAND_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%x10", "%x11"
+
+#define _BITWISEAND_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%x10", "%x11"
+
+#define _BITWISEAND(_lock, _opl, _opr)					\
+({									\
+	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+									\
+/*	__asm__ volatile						\
+	(								\
+		_BITWISEAND_PRE_INST_##_lock				\
+		"and	x10, x11, %[opr]"	"\n\t"			\
+		"str	x10, %[dest]"		"\n\t"			\
+		 _BITWISEAND_POST_INST_##_lock				\
+		: [dest] "=m" (_dest)					\
+		: [addr] "r" (&_opl),					\
+		  [opr]  "Lr" (_opr)					\
+		_BITWISEAND_CLOBBERS_##_lock				\
+	);*/								\
+	_dest;								\
+})
+
+#define _BITWISEOR_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEOR_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEOR_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITWISEOR_POST_INST_LOCK_LESS					\
+		"#	NOP"
+
+#define _BITWISEOR_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%x10", "%x11"
+
+#define _BITWISEOR_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%x10", "%x11"
+
+#define _BITWISEOR(_lock, _opl, _opr)					\
+({									\
+	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+									\
+/*	__asm__ volatile						\
+	(								\
+		_BITWISEOR_PRE_INST_##_lock				\
+		"orr	x10, x11, %[opr]"	"\n\t"			\
+		"str	x10, %[dest]"		"\n\t"			\
+		_BITWISEOR_POST_INST_##_lock				\
+		: [dest] "=m" (_dest)					\
+		: [addr] "r" (&_opl),					\
+		  [opr]  "Lr" (_opr)					\
+		_BITWISEOR_CLOBBERS_##_lock				\
+	);*/								\
+	_dest;								\
+})
+
+#define _BITWISEXOR_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEXOR_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISEXOR_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITWISEXOR_POST_INST_LOCK_LESS					\
+		"#	NOP"
+
+#define _BITWISEXOR_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%x10", "%x11"
+
+#define _BITWISEXOR_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%x10", "%x11"
+
+#define _BITWISEXOR(_lock, _opl, _opr)					\
+({									\
+	volatile Bit64 _dest __attribute__ ((aligned (8)));		\
+									\
+/*	__asm__ volatile						\
+	(								\
+		_BITWISEXOR_PRE_INST_##_lock				\
+		"eor	x10, x11, %[opr]"	"\n\t"			\
+		"str	x10, %[dest]"		"\n\t"			\
+		_BITWISEXOR_POST_INST_##_lock				\
+		: [dest] "=m" (_dest)					\
+		: [addr] "r" (&_opl),					\
+		  [opr]  "Lr" (_opr)					\
+		_BITWISEXOR_CLOBBERS_##_lock				\
+	);*/								\
+	_dest;								\
+})
+
+#define BITSET(_lock, _base, _offset)					\
+(									\
+	__builtin_constant_p(_offset) ? 				\
+		_BITSET_IMM(_lock, _base, _offset)			\
+	:	_BITSET_GPR(_lock, _base, _offset)			\
+)
+
+#define BITCLR(_lock, _base, _offset)					\
+(									\
+	__builtin_constant_p(_offset) ? 				\
+		_BITCLR_IMM(_lock, _base, _offset)			\
+	:	_BITCLR_GPR(_lock, _base, _offset)			\
+)
+
+#define BITVAL_3xPARAM(_lock, _base, _offset)				\
+(									\
+	__builtin_constant_p(_offset) ? 				\
+		_BIT_TEST_IMM(_lock, _base, _offset)			\
+	:	_BIT_TEST_GPR(_lock, _base, _offset)			\
+)
+
+#define BITVAL_2xPARAM(_base, _offset)					\
+(									\
+	BITVAL_3xPARAM(LOCKLESS, _base, _offset)			\
+)
+
+#define BITVAL_DISPATCH( _1, _2, _3, BITVAL_CURSOR, ... )		\
+	BITVAL_CURSOR
+
+#define BITVAL(...)							\
+	BITVAL_DISPATCH(__VA_ARGS__,	BITVAL_3xPARAM, /*3*/		\
+					BITVAL_2xPARAM, /*2*/		\
+					NULL)		/*1*/		\
+							( __VA_ARGS__ )
+
+#define BITCPL(_src)							\
+({									\
+	unsigned long long _dest;					\
+									\
+	__asm__ volatile						\
+	(								\
+		"neg	%x[dest], %x[src]"				\
+		: [dest] "=rQ" (_dest)					\
+		: [src] "Lr" (_src)					\
+		: "cc", "memory"					\
+	);								\
+	_dest;								\
+})
+
+#define BITWISEAND(_lock, _opl, _opr)	_BITWISEAND(_lock, _opl, _opr)
+#define BITWISEOR(_lock, _opl, _opr)	_BITWISEOR(_lock, _opl, _opr)
+#define BITWISEXOR(_lock, _opl, _opr)	_BITWISEXOR(_lock, _opl, _opr)
+
+#define _BITSTOR_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	xzr, [%[addr]]" 	"\n\t"*/
+
+#define _BITSTOR_PRE_INST_LOCK_LESS					\
+		"#	NOP"			"\n\t"
+
+#define _BITSTOR_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, %[src], [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITSTOR_POST_INST_LOCK_LESS					\
+/*		"str	%[src], [%[addr]]"*/
+
+#define _BITSTOR_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9"
+
+#define _BITSTOR_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory"
+
+#define _BITSTOR(_lock, _dest, _src)					\
+({									\
+/*	__asm__ volatile						\
+	(								\
+		_BITSTOR_PRE_INST_##_lock				\
+		_BITSTOR_POST_INST_##_lock				\
+		:							\
+		: [addr] "r" (&_dest),					\
+		  [src] "r" (_src)					\
+		_BITSTOR_CLOBBERS_##_lock				\
+	);*/								\
+})
+
+#define BITSTOR(_lock, _dest, _src)					\
+	_BITSTOR(_lock, _dest, _src)
+
+#define BITBSF(_base, _index)						\
+({									\
+	register unsigned char _ret;					\
+	if (_base) {							\
+		_index = 0;						\
+		while (BITVAL(_base, _index) == 0) {			\
+			if (_index < (8 * sizeof(_base)) - 1) {		\
+				_index = _index + 1;			\
+			} else {					\
+				break;					\
+			}						\
+		}							\
+		_ret = 0;						\
+	} else {							\
+		_index = 0;						\
+		_ret = 1;						\
+	}								\
+	_ret;								\
+})
+
+#define BITBSR(_base, _index)						\
+({									\
+	register unsigned char _ret;					\
+	if (_base) {							\
+		_index = (8 * sizeof(_base)) - 1;			\
+		while (BITVAL(_base, _index) == 0) {			\
+			if (_index > 0) {				\
+				_index = _index - 1;			\
+			} else {					\
+				break;					\
+			}						\
+		}							\
+		_ret = 0;						\
+	} else {							\
+		_index = 0;						\
+		_ret = 1;						\
+	}								\
+	_ret;								\
+})
+
+#define BITEXTRZ(_src, _offset, _length)				\
+({									\
+	unsigned long long _dest = ((1 << _length) - 1) 		\
+				 & (_src >> _offset);			\
+	_dest;								\
+})
+
+#define _BITWISESET_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISESET_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISESET_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, x11, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITWISESET_POST_INST_LOCK_LESS					\
+/*		"str	x11, [%[addr]]"*/
+
+#define _BITWISESET_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%x11"
+
+#define _BITWISESET_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%x11"
+
+#define _BITWISESET(_lock, _opl, _opr)					\
+({									\
+/*	__asm__ volatile						\
+	(								\
+		_BITWISESET_PRE_INST_##_lock				\
+		"orr	x11, x11, %[opr]"	"\n\t"			\
+		_BITWISESET_POST_INST_##_lock				\
+		:							\
+		: [addr] "r" (&_opl),					\
+		  [opr]  "Lr" (_opr)					\
+		_BITWISESET_CLOBBERS_##_lock				\
+	);*/								\
+})
+
+#define BITWISESET(_lock, _opl, _opr)					\
+	_BITWISESET(_lock, _opl, _opr)
+
+#define _BITWISECLR_PRE_INST_FULL_LOCK					\
+/*	"1:"					"\n\t"			\
+		"ldxr	xzr, [%[addr]]" 	"\n\t"*/
+
+#define _BITWISECLR_PRE_INST_LOCK_LESS					\
+		"#	NOP"			"\n\t"
+
+#define _BITWISECLR_POST_INST_FULL_LOCK					\
+/*		"stxr	w9, xzr, [%[addr]]"	"\n\t"			\
+		"cbnz	w9, 1b" 		"\n\t"			\
+		"dmb	ish"*/
+
+#define _BITWISECLR_POST_INST_LOCK_LESS					\
+/*		"str	xzr, [%[addr]]"*/
+
+#define _BITWISECLR_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9"
+
+#define _BITWISECLR_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory"
+
+#define _BITWISECLR(_lock, _dest)					\
+({									\
+	__asm__ volatile						\
+	(								\
+		_BITWISECLR_PRE_INST_##_lock				\
+		_BITWISECLR_POST_INST_##_lock				\
+		:							\
+		: [addr] "r" (&_dest)					\
+		_BITWISECLR_CLOBBERS_##_lock				\
+	);								\
+})
+
+#define BITWISECLR(_lock, _dest)					\
+	_BITWISECLR(_lock, _dest)
+
+#if (CORE_COUNT == 64)
+#define BITSET_CC(_lock, _base, _offset) BITSET(_lock, _base, _offset)
+#else
+#define BITSET_CC(_lock, _base, _offset)				\
+(									\
+	BITSET(_lock,	_base[ CORE_WORD_TOP(CORE_COUNT)		\
+				- CORE_WORD_POS(CORE_COUNT, _offset) ] ,\
+			CORE_WORD_MOD(CORE_COUNT, _offset) )		\
+)
+#endif
+
+#if (CORE_COUNT == 64)
+#define BITCLR_CC(_lock, _base, _offset) BITCLR(_lock, _base, _offset)
+#else
+#define BITCLR_CC(_lock, _base, _offset)				\
+(									\
+	BITCLR(_lock,	_base[ CORE_WORD_TOP(CORE_COUNT)		\
+				- CORE_WORD_POS(CORE_COUNT, _offset) ] ,\
+			CORE_WORD_MOD(CORE_COUNT, _offset) )		\
+)
+#endif
+
+#if (CORE_COUNT == 64)
+#define BITVAL_CC(_base, _offset) BITVAL(_base, _offset)
+#else
+#define BITVAL_CC(_base, _offset)					\
+(									\
+	BITVAL(_base[CORE_WORD_TOP(CORE_COUNT)				\
+		- CORE_WORD_POS(CORE_COUNT, _offset)],			\
+		CORE_WORD_MOD(CORE_COUNT, _offset) )			\
+)
+#endif
+
+#if (CORE_COUNT == 64)
+#define BITWISEAND_CC(_lock, _opl, _opr) _BITWISEAND(_lock, _opl, _opr)
+#else
+#define BITWISEAND_CC(_lock, _opl, _opr)				\
+({									\
+	volatile Bit64 _ret __attribute__ ((aligned (8))) = 0;		\
+	unsigned int cw = 0;						\
+	do {								\
+		_ret |= _BITWISEAND(_lock, _opl[cw], _opr[cw]) ;	\
+	} while (++cw <= CORE_WORD_TOP(CORE_COUNT));			\
+	_ret;								\
+})
+#endif
+
+#if (CORE_COUNT == 64)
+#define BITSTOR_CC(_lock, _dest, _src) _BITSTOR(_lock, _dest, _src)
+#else
+#define BITSTOR_CC(_lock, _dest, _src)					\
+({									\
+	unsigned int cw = 0;						\
+	do {								\
+		_BITSTOR(_lock, _dest[cw], _src[cw]);			\
+	} while (++cw <= CORE_WORD_TOP(CORE_COUNT));			\
+})
+#endif
+
+#define _BITCMP_PRE_INST_FULL_LOCK					\
+/*	"1:"						"\n\t"		\
+		"ldxr	x11,	[%[addr]]"		"\n\t"*/
+
+#define _BITCMP_PRE_INST_LOCK_LESS					\
+/*		"ldr	x11,	[%[addr]]"		"\n\t"*/
+
+#define _BITCMP_POST_INST_FULL_LOCK					\
+/*		"stxr	w9,	x11, [%[addr]]" 	"\n\t"		\
+		"cbnz	w9,	1b"			"\n\t"		\
+		"dmb	ish"*/
+
+#define _BITCMP_POST_INST_LOCK_LESS					\
+		"#	NOP"
+
+#define _BITCMP_CLOBBERS_FULL_LOCK					\
+		: "cc", "memory", "%w9", "%w10", "%x11"
+
+#define _BITCMP_CLOBBERS_LOCK_LESS					\
+		: "cc", "memory", "%w10", "%x11"
+
+#define _BITCMP(_lock, _opl, _opr)					\
+({									\
+	volatile unsigned char _ret;					\
+									\
+/*	__asm__ volatile						\
+	(								\
+		_BITCMP_PRE_INST_##_lock				\
+		"cmp	x11,	%[opr]" 		"\n\t"		\
+		"cset	w10,	eq"			"\n\t"		\
+		"strb	w10,	%[ret]" 		"\n\t"		\
+		_BITCMP_POST_INST_##_lock				\
+		: [ret] "=m"	(_ret)					\
+		: [addr] "r"	(&_opl), 				\
+		  [opr]	"Lr"	(_opr)					\
+		_BITCMP_CLOBBERS_##_lock				\
+	);*/								\
+	_ret;								\
+})
+
+#define BITZERO(_lock, _src)						\
+	_BITCMP(_lock, _src, 0)
+
+#if (CORE_COUNT == 64)
+#define BITCMP_CC(_lock, _opl, _opr) _BITCMP(_lock, _opl, _opr)
+#else
+#define BITCMP_CC(_lock, _opl, _opr)					\
+({									\
+	unsigned char ret = 1;						\
+	unsigned int cw = 0;						\
+	do {								\
+		ret &= _BITCMP(_lock, _opl[cw], _opr[cw]);		\
+	} while (++cw <= CORE_WORD_TOP(CORE_COUNT));			\
+	ret;								\
+})
+#endif
+
+/* Micro-benchmark. Prerequisites: CPU affinity, RDTSC[P] optionnaly RDPMC */
+#if defined(UBENCH) && UBENCH == 1
+
+#define UBENCH_DECLARE()						\
+static unsigned long long uBenchCounter[2][4] __attribute__((aligned(8)))=\
+{									\
+/* TSC*/{0,		0,		0,		0},		\
+/*INST*/{0,		0,		0,		0}		\
+/*	[0]DELTA,	[1]PREV,	[2]LAST,	[3]OVERHEAD  */ \
+};									\
+									\
+inline static void UBENCH_RDCOUNTER_VOID(unsigned int idx) {}		\
+									\
+inline static void UBENCH_With_RDTSC_No_RDPMC(unsigned int idx) 	\
+{									\
+	RDTSC64(uBenchCounter[0][idx]) ;	SERIALIZE();		\
+}									\
+									\
+inline static void UBENCH_With_RDTSCP_RDPMC(unsigned int idx)		\
+{									\
+	RDTSCP_PMCx1(	uBenchCounter[0][idx],				\
+			0x40000000,					\
+			uBenchCounter[1][idx]) ;			\
+}									\
+									\
+									\
+inline static void UBENCH_With_RDTSC_RDPMC(unsigned int idx)		\
+{									\
+	RDTSC_PMCx1(	uBenchCounter[0][idx],				\
+			0x40000000,					\
+			uBenchCounter[1][idx]) ;			\
+}									\
+									\
+static void (*UBENCH_RDCOUNTER)(unsigned int) = UBENCH_RDCOUNTER_VOID;
+
+#define UBENCH_COMPUTE()						\
+({									\
+	uBenchCounter[0][0] = uBenchCounter[0][2] - uBenchCounter[0][1];\
+	uBenchCounter[1][0] = uBenchCounter[1][2] - uBenchCounter[1][1];\
+	uBenchCounter[0][0] -= uBenchCounter[0][3];			\
+	uBenchCounter[1][0] -= uBenchCounter[1][3];			\
+})
+
+#define UBENCH_METRIC(metric) (uBenchCounter[metric][0])
+
+#define UBENCH_SETUP(withRDTSCP , withRDPMC)				\
+({									\
+	void (*MatrixCallFunc[2][2])(unsigned int) = {			\
+		{UBENCH_With_RDTSC_No_RDPMC, UBENCH_With_RDTSC_RDPMC},	\
+		{UBENCH_With_RDTSCP_No_RDPMC,UBENCH_With_RDTSCP_RDPMC}	\
+	};								\
+	UBENCH_RDCOUNTER = MatrixCallFunc[withRDTSCP][withRDPMC];	\
+									\
+	UBENCH_RDCOUNTER(0);						\
+	UBENCH_RDCOUNTER(3);						\
+									\
+	uBenchCounter[0][0] = uBenchCounter[0][3]- uBenchCounter[0][0]; \
+	uBenchCounter[1][0] = uBenchCounter[1][3]- uBenchCounter[1][0]; \
+	uBenchCounter[0][3] = uBenchCounter[0][0];			\
+	uBenchCounter[1][3] = uBenchCounter[1][0];			\
+})
+
+#else /* UBENCH == 1 */
+
+#define UBENCH_DECLARE()			/* UBENCH_DECLARE()	*/
+#define UBENCH_RDCOUNTER(idx)			/* UBENCH_RDCOUNTER()	*/
+#define UBENCH_COMPUTE()			/* UBENCH_COMPUTE()	*/
+#define UBENCH_METRIC(metric)			/* UBENCH_METRIC()	*/
+#define UBENCH_SETUP(withTSCP , withPMC)	/* UBENCH_SETUP()	*/
+
+#endif /* UBENCH == 1 */

riscv64/corefreq-api.h

@@ -0,0 +1,409 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#define DRV_DEVNAME	"corefreqk"
+#define DRV_FILENAME	"/dev/"DRV_DEVNAME
+
+#define ID_RO_VMA_PROC	(CORE_COUNT + 0)
+#define ID_RW_VMA_PROC	(CORE_COUNT + ID_RO_VMA_PROC)
+#define ID_RO_VMA_GATE	(CORE_COUNT + ID_RW_VMA_PROC)
+#define ID_RO_VMA_CORE	(CORE_COUNT + ID_RO_VMA_GATE)
+#define ID_RW_VMA_CORE	(CORE_COUNT + ID_RO_VMA_CORE)
+#define ID_ANY_VMA_JAIL (CORE_COUNT + ID_RW_VMA_CORE)
+
+#define WAKEUP_RATIO	4
+#define LOOP_MIN_MS	100
+#define LOOP_MAX_MS	((1000 - 1) * WAKEUP_RATIO)
+#define LOOP_DEF_MS	1000
+#define TICK_DEF_MS	2000
+
+typedef struct
+{
+	struct {
+		unsigned int	PN	: 12-0,
+				BSP	: 32-12;
+	};
+	signed int		MPID,
+				CoreID,
+				ThreadID,
+				PackageID;
+	struct CLUSTER_ST	Cluster;
+	struct CACHE_INFO
+	{
+		union CCSIDR
+		{
+			unsigned long long	value;
+			struct
+			{
+				unsigned long long
+				LineSz		:  3-0,
+				Assoc		: 13-3,
+				Set		: 28-13,
+				WrAlloc 	: 29-28,
+				RdAlloc 	: 30-29,
+				WrBack		: 31-30,
+				WrThrough	: 32-31,
+				RES0		: 64-32;
+			};
+		} ccsid;
+		unsigned int	Size;
+	} Cache[CACHE_MAX_LEVEL];
+} CACHE_TOPOLOGY;
+
+typedef struct
+{
+	THERMAL_PARAM			Param;
+	unsigned int			Sensor;
+	signed int			VID;
+	struct {
+		enum THERM_PWR_EVENTS	Events[eDIM];
+	};
+	HWP_CAPABILITIES		HWP_Capabilities;
+	HWP_INTERRUPT			HWP_Interrupt;
+	HWP_REQUEST			HWP_Request;
+	struct ACPI_CPPC_STRUCT {
+		unsigned short		Highest,
+					Guaranteed,
+					Efficient,
+					Lowest,
+					Minimum,
+					Maximum,
+					Desired,
+					Energy;
+	} ACPI_CPPC;
+} POWER_THERMAL;
+
+/*				ACPI/OSPM
+
+	Highest Performance ... .------,
+				|######|
+				|######|
+	Nominal Performance ... |------|  ..
+				|//////|    \
+				|//////|    :
+				|//////|    :
+				|//////|    :
+				|//////|    --- Guaranteed Performance
+Lowest Nonlinear Performance .. --------    :	Allowed Range
+				|OOOOOO|    :
+				|OOOOOO|    :
+				|OOOOOO|    :
+	Lowest Performance .... --------  ../
+				|++++++|
+				|++++++|
+				|++++++|
+			0 ..... `------'
+*/
+
+typedef struct
+{
+	Bit64				OffLine __attribute__ ((aligned (8)));
+
+	struct
+	{
+		unsigned long long	TSC;
+	} Overhead __attribute__ ((aligned (8)));
+
+	struct
+	{
+		unsigned long long	INST;
+		struct
+		{
+		unsigned long long
+				UCC,
+				URC;
+		}			C0;
+		unsigned long long
+					C3,
+					C6,
+					C7,
+					TSC;
+
+		unsigned long long	C1;
+
+		struct
+		{
+		unsigned long long	ACCU;
+		} Power;
+	} Counter[2] __attribute__ ((aligned (8)));
+
+	struct
+	{
+	unsigned long long
+				C1,
+				C2,
+				C3,
+				C4,
+				C5,
+				C6,
+				C7;
+	} VPMC __attribute__ ((aligned (8)));
+
+	struct
+	{
+		unsigned long long
+					INST;
+		struct
+		{
+		unsigned long long
+				UCC,
+				URC;
+		}			C0;
+		unsigned long long
+					C3,
+					C6,
+					C7,
+					TSC,
+					C1;
+
+		struct
+		{
+		unsigned long long	ACCU;
+		} Power;
+
+		unsigned int		SMI;
+	} Delta __attribute__ ((aligned (8)));
+
+	POWER_THERMAL			PowerThermal;
+	THERMAL_POINT			ThermalPoint;
+
+	struct
+	{
+		unsigned int		SMI;
+		struct {
+			unsigned int
+					LOCAL,
+					UNKNOWN,
+					PCISERR,
+					IOCHECK;
+		}			NMI;
+	} Interrupt;
+
+	struct
+	{
+		struct {
+		unsigned long long
+					CfgLock :  1-0,  /* Core	*/
+					IORedir :  2-1,  /* Core	*/
+					SCTLRX	:  3-2,  /* Thread	*/
+					Unused	: 32-3,
+					Revision: 64-32;
+		};
+		unsigned short int	CStateLimit;
+		unsigned short int	CStateBaseAddr; /* Any I/O BAR	*/
+	} Query;
+
+	CACHE_TOPOLOGY			T;
+
+	struct {
+		Bit64			FLAGS	__attribute__ ((aligned (8)));
+		Bit64			HCR	__attribute__ ((aligned (8)));
+		Bit64			SCTLR	__attribute__ ((aligned (8)));
+		Bit64			SCTLR2	__attribute__ ((aligned (8)));
+		Bit64			EL	__attribute__ ((aligned (8)));
+		Bit64			FPSR	__attribute__ ((aligned (8)));
+		Bit64			FPCR	__attribute__ ((aligned (8)));
+		Bit64			SVCR	__attribute__ ((aligned (8)));
+		Bit64			CPACR	__attribute__ ((aligned (8)));
+	} SystemRegister;
+
+	unsigned int			Bind;
+
+	CLOCK				Clock;
+
+	COF_ST				Boost[BOOST(SIZE)];
+
+	COF_ST				Ratio;
+} CORE_RO;
+
+typedef struct
+{
+	struct	/* 64-byte cache line size.				*/
+	{
+		Bit64			V,
+					_pad[7];
+	} Sync __attribute__ ((aligned (8)));
+
+} CORE_RW;
+
+typedef struct
+{
+	struct {
+		union {
+		} DIMM[MC_MAX_DIMM];
+	} Channel[MC_MAX_CHA];
+
+	union {
+	} MaxDIMMs;
+
+	unsigned short		SlotCount, ChannelCount;
+} MC_REGISTERS;
+
+typedef struct
+{
+} BUS_REGISTERS;
+
+
+typedef struct {
+		int		taskCount;
+		TASK_MCB	taskList[TASK_LIMIT];
+
+		unsigned int	kernelVersionNumber;
+
+		char		sysname[MAX_UTS_LEN],
+				release[MAX_UTS_LEN],
+				version[MAX_UTS_LEN],
+				machine[MAX_UTS_LEN];
+} SYSGATE_RO; /*		RO Pages				*/
+
+#define CHIP_MAX_PCI	24
+
+typedef struct
+{
+	struct
+	{
+	    unsigned long long	PCLK; /* Contextual Clock [TSC|UCLK|MCLK] */
+	  struct {
+	    unsigned long long	PC02,
+				PC03,
+				PC04,
+				PC06,
+				PC07,
+				PC08,
+				PC09,
+				PC10;
+	  };
+	    unsigned long long	MC6;
+
+	  struct {
+	    unsigned long long	FC0; /* Uncore fixed counter #0 	*/
+	  } Uncore;
+
+	  struct {
+	    unsigned long long	ACCU[PWR_DOMAIN(SIZE)];
+	  } Power;
+	} Counter[2] __attribute__ ((aligned (8)));
+
+	struct
+	{
+	    unsigned long long	PCLK;
+	  struct {
+	    unsigned long long	PC02,
+				PC03,
+				PC04,
+				PC06,
+				PC07,
+				PC08,
+				PC09,
+				PC10;
+	  };
+	    unsigned long long	MC6;
+
+	  struct {
+	    unsigned long long	FC0;
+	  } Uncore;
+	} Delta __attribute__ ((aligned (8)));
+
+	FEATURES		Features;
+
+	BitCC			CR_Mask 	__attribute__ ((aligned (16)));
+	BitCC			HWP_Mask __attribute__ ((aligned (16)));
+	BitCC			SPEC_CTRL_Mask	__attribute__ ((aligned (16)));
+
+	enum THERMAL_FORMULAS	thermalFormula;
+	enum VOLTAGE_FORMULAS	voltageFormula;
+	enum POWER_FORMULAS	powerFormula;
+
+	unsigned int		SleepInterval,
+				tickReset,
+				tickStep;
+
+	struct {
+		unsigned int	Count,
+				OnLine;
+	} CPU;
+
+	SERVICE_PROC		Service;
+
+	signed int		ArchID;
+
+	struct {
+		CLUSTERCFR	ClusterCfg;
+		CLUSTERIDR	ClusterRev;
+
+		unsigned int	Boost[UNCORE_BOOST(SIZE)];
+		BUS_REGISTERS	Bus;
+		MC_REGISTERS	MC[MC_MAX_CTRL];
+		unsigned short	CtrlCount;
+	    struct CHIP_ST {
+		unsigned short	VID, DID;
+	    } Chip[CHIP_MAX_PCI];
+	} Uncore;
+
+	struct {
+		THERMAL_PARAM	Param;
+		unsigned int	Sensor;
+	    struct {
+		signed int	CPU, SOC;
+	    } VID;
+
+	enum THERM_PWR_EVENTS	Events[eDIM];
+
+	    struct {
+		unsigned short	Minimum,
+				Maximum;
+	    } ACPI_CPPC;
+	} PowerThermal;
+
+	THERMAL_POINT		ThermalPoint;
+
+	struct {
+		struct {
+			size_t	Size;
+			int	Order;
+		} ReqMem;
+	} Gate;
+
+	OS_DRIVER		OS;
+
+	struct {
+		Bit64		NMI;
+		signed int	AutoClock,
+				Experimental,
+				HotPlug,
+				PCI;
+		KERNEL_DRIVER	Driver;
+	} Registration;
+
+	enum HYPERVISOR 	HypervisorID;
+	char			Architecture[CODENAME_LEN];
+
+	SMBIOS_ST		SMB;
+
+	FOOTPRINT		FootPrint;
+} PROC_RO; /*			RO Pages				*/
+
+typedef struct
+{
+	struct
+	{
+	  struct {
+	    unsigned long long	ACCU[PWR_DOMAIN(SIZE)];
+	  } Power;
+	} Delta __attribute__ ((aligned (8)));
+
+	BitCC			HWP		__attribute__ ((aligned (16)));
+	BitCC			VM		__attribute__ ((aligned (16)));
+	BitCC			CLRBHB		__attribute__ ((aligned (16)));
+	BitCC			CSV2_1		__attribute__ ((aligned (16)));
+	BitCC			CSV2_2		__attribute__ ((aligned (16)));
+	BitCC			CSV2_3		__attribute__ ((aligned (16)));
+	BitCC			CSV3		__attribute__ ((aligned (16)));
+	BitCC			SSBS		__attribute__ ((aligned (16)));
+	struct {
+		Bit64		Signal	__attribute__ ((aligned (8)));
+	} OS;
+} PROC_RW; /*			RW Pages				*/

riscv64/corefreq-cli-extra.c

@@ -0,0 +1,219 @@
+/*
+ * CoreFreq (C) 2015-2025 CYRIL COURTIAT
+ * Contributors: Andrew Gurinovich ; CyrIng
+ * Licenses: GPL2
+ *
+ * Some ideas taken from https://github.com/cesanta/frozen/ 
+ * under Apache 2.0 license
+ */
+
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <ctype.h>
+#include <string.h>
+#include <assert.h>
+
+#include "corefreq-cli-extra.h"
+
+#define UNUSED(expr) do { (void)(expr); } while (0)
+
+/*				--[ JSON toolkit ]--			*/
+struct json_state;
+
+enum JSON_STATE {
+	DEFAULT, IN_ARRAY, IN_ARRAY2, IN_OBJECT, IN_OBJECT2
+};
+
+int json_writer_stdout(struct json_state * state, const char *str, size_t len)
+{
+	UNUSED(state);
+	return fwrite(str, len, 1, stdout);
+}
+
+size_t get_utf8_char_len(unsigned char ch)
+{
+	if ((ch & 0x80) == 0)
+		return 1;
+	switch (ch & 0xf0) {
+	case 0xf0:
+		return 4;
+	case 0xe0:
+		return 3;
+	default:
+		return 2;
+	}
+}
+
+/* This routine does NOT handle unicode finely - everything above 0x7f should
+ * be \u0000 encoded, but this requires us to be utf8 capable. Check the
+ * following tiny libraries(for future improvement):
+ * https://github.com/git/git/blob/master/utf8.c
+ * https://github.com/JeffBezanson/cutef8/blob/master/utf8.c
+ * https://github.com/sheredom/utf8.h
+ * https://github.com/JuliaStrings/utf8proc
+ */
+
+int json_escape(struct json_state *state, const char *p, size_t len)
+{
+	size_t i, cl;
+	const char *hex_digits = "0123456789abcdef";
+	const char *specials = "btnvfr";
+	int n = 0;
+
+    for (i = 0; i < len; i++) {
+	unsigned char ch = ((unsigned char *) p)[i];
+	if (ch == '"' || ch == '\\') {
+		n += state->write(state, "\\", 1);
+		n += state->write(state, p + i, 1);
+	} else if (ch >= '\b' && ch <= '\r') {
+		n += state->write(state, "\\", 1);
+		n += state->write(state, &specials[ch - '\b'], 1);
+	} else if (isprint(ch)) {
+		n += state->write(state, p + i, 1);
+	} else if ((cl = get_utf8_char_len(ch)) == 1) {
+		n += state->write(state, "\\u00", 4);
+		n += state->write(state, &hex_digits[(ch >> 4) % 0xf], 1);
+		n += state->write(state, &hex_digits[ch % 0xf], 1);
+	} else {
+		n += state->write(state, p + i, cl);
+		i += cl - 1;
+	}
+    }
+	return n;
+}
+
+void json_start_object(struct json_state *state)
+{
+	assert(state->depth < JSON_MAX_DEPTH);
+	/* TODO: assert(state->nested_state[state->depth] != IN_OBJECT); */
+	if (state->nested_state[state->depth] == IN_ARRAY2 ) {
+		state->write(state, ", {", 3);
+	} else {
+		state->write(state, "{", 1);
+	}
+	if (state->nested_state[state->depth] == IN_ARRAY) {
+		state->nested_state[state->depth] = IN_ARRAY2;
+	}
+	if (state->nested_state[state->depth] == IN_OBJECT) {
+		state->nested_state[state->depth] = IN_OBJECT2;
+	}
+	state->nested_state[++state->depth] = IN_OBJECT;
+}
+
+void json_end_object(struct json_state *state)
+{
+	assert(state->depth >= 0);
+	assert(state->nested_state[state->depth] == \
+		IN_OBJECT || state->nested_state[state->depth] == IN_OBJECT2);
+
+	state->write(state, "}", 1);
+	state->nested_state[state->depth--] = DEFAULT;
+}
+
+void json_start_arr(struct json_state *state)
+{
+	assert(state->depth < JSON_MAX_DEPTH);
+
+	if (state->nested_state[state->depth] == IN_ARRAY2) {
+		state->write(state, ", [", 3);
+	} else {
+		state->write(state, "[", 1);
+	}
+	if (state->nested_state[state->depth] == IN_ARRAY) {
+		state->nested_state[state->depth] = IN_ARRAY2;
+	}
+	if (state->nested_state[state->depth] == IN_OBJECT) {
+		state->nested_state[state->depth] = IN_OBJECT2;
+	}
+	state->nested_state[++state->depth] = IN_ARRAY;
+}
+
+void json_end_arr(struct json_state *state)
+{
+	assert(state->depth >= 0);
+	assert(state->nested_state[state->depth] == \
+		IN_ARRAY || state->nested_state[state->depth] == IN_ARRAY2);
+
+	state->write(state, "]", 1);
+	state->nested_state[state->depth--] = DEFAULT;
+}
+
+void json_key(struct json_state *state, char * key)
+{
+	assert(state->nested_state[state->depth] == \
+		IN_OBJECT || state->nested_state[state->depth] == IN_OBJECT2);
+
+	if (state->nested_state[state->depth] == IN_OBJECT2) {
+		state->write(state, ", ", 1);
+	}
+	state->write(state, "\"", 1);
+	json_escape(state, key, strlen(key));
+	state->write(state, "\":", 2);
+}
+
+void json_string(struct json_state *state, char * value)
+{
+	assert(state->nested_state[state->depth] != DEFAULT);
+
+	if (state->nested_state[state->depth] == IN_ARRAY2) {
+		state->write(state, ", ", 2);
+	}
+	if (state->nested_state[state->depth] == IN_ARRAY) {
+		state->nested_state[state->depth] = IN_ARRAY2;
+	}
+	if (state->nested_state[state->depth] == IN_OBJECT) {
+		state->nested_state[state->depth] = IN_OBJECT2;
+	}
+	state->write(state, "\"", 1);
+	json_escape(state, value, strlen(value));
+	state->write(state, "\"", 1);
+}
+
+void json_literal(struct json_state *state, char * format, ...)
+{
+	assert(state->nested_state[state->depth] != DEFAULT);
+
+	if (state->nested_state[state->depth] == IN_ARRAY2) {
+		state->write(state, ", ", 2);
+	}
+	if (state->nested_state[state->depth] == IN_ARRAY) {
+		state->nested_state[state->depth] = IN_ARRAY2;
+	}
+	if (state->nested_state[state->depth] == IN_OBJECT) {
+		state->nested_state[state->depth] = IN_OBJECT2;
+	}
+	va_list args;
+	va_start(args, format);
+	char buf[JSON_MAX_VALUE];
+	const int rc = vsprintf(buf, format, args);
+	const size_t bufsz = rc > 0 ? (size_t) rc : 0;
+	state->write(state, buf, bufsz);
+	va_end(args);
+}
+
+/*				--[ UTF toolkit ]--			*/
+
+void ISO_8859_To_Unicode(unsigned char *pIn, unsigned char *pOut)
+{
+	while ( (*pIn) != '\0' ) {
+		if ( (*pIn) > 0x7f ) {
+			switch ( (*pIn) ) {
+			case 0xc0 ... 0xff:	/* To UTF-8 Ctrl:C3 */
+				(*pOut) = (*pIn) ^ 0x40;
+				break;
+			case 0xa0 ... 0xbf:	/* To UTF-8 Ctrl:C2 */
+				(*pOut) = (*pIn) ^ 0x60;
+				break;
+			default:
+				(*pOut) = 0x20;
+				break;
+			}
+		} else {
+			(*pOut) = (*pIn);
+		}
+		pIn++;
+		pOut++;
+	}
+	(*pOut) = '\0';
+}

riscv64/corefreq-cli-extra.h

@@ -0,0 +1,30 @@
+/*
+ * CoreFreq (C) 2015-2025 CYRIL COURTIAT
+ * Contributors: Andrew Gurinovich ; CyrIng
+ * Licenses: GPL2
+ *
+ * Some ideas taken from github.com/cesanta/frozen
+ * under Apache 2.0 license
+ */
+
+#define JSON_MAX_DEPTH 32
+#define JSON_MAX_VALUE 4096
+
+struct json_state {
+	int (*write)(struct json_state* state, const char *str, size_t len);
+	unsigned char nested_state[JSON_MAX_DEPTH];
+	unsigned char depth;
+};
+
+extern int json_writer_stdout(	struct json_state * state,
+				const char *str,
+				size_t len) ;
+extern void json_start_object(struct json_state *state) ;
+extern void json_end_object(struct json_state *state) ;
+extern void json_start_arr(struct json_state *state) ;
+extern void json_end_arr(struct json_state *state) ;
+extern void json_key(struct json_state *state, char * key) ;
+extern void json_string(struct json_state *state, char * value) ;
+extern void json_literal(struct json_state *state, char * format, ...) ;
+
+extern void ISO_8859_To_Unicode(unsigned char*, unsigned char*) ;

riscv64/corefreq-cli-json.h

@@ -0,0 +1,7 @@
+/*
+ * CoreFreq (C) 2015-2025 CYRIL COURTIAT
+ * Contributors: Andrew Gurinovich ; CyrIng
+ * Licenses: GPL2
+ */
+
+extern void JsonSysInfo(RO(SHM_STRUCT)*) ;

riscv64/corefreq-cli.h

@@ -0,0 +1,724 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#define CLEAR_EVENT_MASK	0x000000000000007eLLU
+
+#define CLOCK_SOURCE_MASK	0x000000000000000fLLU
+
+#define TRACK_TASK		0x0200000000000000LLU
+#define TRACK_MASK		0x00000000007fffffLLU
+
+#define CPU_ONLINE		0x0000080000000000LLU
+#define CPU_OFFLINE		0x0000100000000000LLU
+#define CPU_STATE_MASK		0x0000180000000000LLU
+#define CPU_SELECT		0x0000200000000000LLU
+#define CPU_MASK		0x00000000000000ffLLU
+#define RATIO_MASK		0x000000000000ffffLLU
+
+#define BOXKEY_CSTATE_MASK	0x00000000000000f0LLU
+
+#define BOXKEY_TURBO_CLOCK	0x00010000
+#define BOXKEY_TURBO_CLOCK_NC	0x00020000LLU
+
+#define BOXKEY_RATIO_CLOCK	0x00040000
+#define BOXKEY_RATIO_CLOCK_OR	0x00080000LLU
+
+#define BOXKEY_CFGTDP_CLOCK	0x00220000
+#define BOXKEY_CFGTDP_CLOCK_OR	0x00200000LLU
+
+#define BOXKEY_UNCORE_CLOCK	0x00400000
+#define BOXKEY_UNCORE_CLOCK_OR	0x00800000LLU
+
+#define BOXKEY_RATIO_SELECT_OR	0x08000000LLU
+
+#define CLOCKMOD_RATIO_MASK	0x0000ffff
+
+#define OPS_RECORDER_MASK	0x00000000000000f0LLU
+
+#define SMBIOS_STRING_INDEX	0x0010000000000000
+#define SMBIOS_STRING_MASK	0x00000000000000ffLLU
+
+#define BOXKEY_EVT_OR		0x3000000000020001LLU
+#define BOXKEY_TDP_OR		0x3000000000021100LLU
+#define BOXKEY_PLX_OP		0x3000000000021200LLU
+#define BOXKEY_PL1_OR		(BOXKEY_PLX_OP | (0x8 << PL1))
+#define BOXKEY_PL2_OR		(BOXKEY_PLX_OP | (0x8 << PL2))
+
+#define BOXKEY_TDP_MASK 	0x0000000000000007LLU
+
+#define BOXKEY_TDC_OR		0x3000000000021400LLU
+#define BOXKEY_TDC_MASK 	0x3000000000021410LLU
+
+
+#define BOXKEY_THM_OR		0x3000000000021800LLU
+#define BOXKEY_THM_OP	 	0x3000000000021810LLU
+
+#define BOXKEY_TW_OR		0x3000000000024100LLU
+#define BOXKEY_TW_OP		0x3000000000024200LLU
+
+#define BOXKEY_ROUTE_MASK	0x00000000000000f0LLU
+
+enum KEY_ENUM {
+	SORTBY_STATE		= 0x0100000000000009LLU + F_STATE,
+	SORTBY_RTIME		= 0x0100000000000009LLU + F_RTIME,
+	SORTBY_UTIME		= 0x0100000000000009LLU + F_UTIME,
+	SORTBY_STIME		= 0x0100000000000009LLU + F_STIME,
+	SORTBY_PID		= 0x0100000000000009LLU + F_PID,
+	SORTBY_COMM		= 0x0100000000000009LLU + F_COMM,
+
+	OPS_INTERVAL		= 0x1000000000001000LLU,
+	OPS_INTERVAL_100	= 0x1000000000001001LLU,
+	OPS_INTERVAL_150	= 0x1000000000001011LLU,
+	OPS_INTERVAL_250	= 0x1000000000001021LLU,
+	OPS_INTERVAL_500	= 0x1000000000001031LLU,
+	OPS_INTERVAL_750	= 0x1000000000001041LLU,
+	OPS_INTERVAL_1000	= 0x1000000000001051LLU,
+	OPS_INTERVAL_1500	= 0x1000000000001061LLU,
+	OPS_INTERVAL_2000	= 0x1000000000001071LLU,
+	OPS_INTERVAL_2500	= 0x1000000000001081LLU,
+	OPS_INTERVAL_3000	= 0x1000000000001091LLU,
+	OPS_AUTOCLOCK		= 0x1000000000002000LLU,
+	OPS_AUTOCLOCK_OFF	= 0x1000000000002001LLU,
+	OPS_AUTOCLOCK_ON	= 0x1000000000002002LLU,
+	OPS_EXPERIMENTAL	= 0x1000000000004000LLU,
+	OPS_EXPERIMENTAL_OFF	= 0x1000000000004001LLU,
+	OPS_EXPERIMENTAL_ON	= 0x1000000000004002LLU,
+	OPS_INTERRUPTS		= 0x1000000000008000LLU,
+	OPS_INTERRUPTS_OFF	= 0x1000000000008001LLU,
+	OPS_INTERRUPTS_ON	= 0x1000000000008002LLU,
+	OPS_CPU_IDLE		= 0x1000000000008010LLU,
+	OPS_CPU_IDLE_OFF	= 0x1000000000008011LLU,
+	OPS_CPU_IDLE_ON 	= 0x1000000000008012LLU,
+	OPS_CPU_FREQ		= 0x1000000000008020LLU,
+	OPS_CPU_FREQ_OFF	= 0x1000000000008021LLU,
+	OPS_CPU_FREQ_ON 	= 0x1000000000008022LLU,
+	OPS_GOVERNOR		= 0x1000000000008040LLU,
+	OPS_GOVERNOR_OFF	= 0x1000000000008041LLU,
+	OPS_GOVERNOR_ON 	= 0x1000000000008042LLU,
+	OPS_CLOCK_SOURCE	= 0x1000000000008080LLU,
+	OPS_CLOCK_SOURCE_1	= 0x1000000000008081LLU,
+	OPS_CLOCK_SOURCE_2	= 0x1000000000008082LLU,
+	OPS_CLOCK_SOURCE_3	= 0x1000000000008083LLU,
+	OPS_CLOCK_SOURCE_4	= 0x1000000000008084LLU,
+	OPS_CLOCK_SOURCE_5	= 0x1000000000008085LLU,
+	OPS_CLOCK_SOURCE_6	= 0x1000000000008086LLU,
+	OPS_CLOCK_SOURCE_7	= 0x1000000000008087LLU,
+	OPS_CLOCK_SOURCE_SEL	= 0x100000000000808dLLU,
+	OPS_CLOCK_SOURCE_OFF	= 0x100000000000808eLLU,
+	OPS_CLOCK_SOURCE_ON	= 0x100000000000808fLLU,
+	OPS_IDLE_ROUTE		= 0x1000000000008100LLU,
+	OPS_ROUTE_DFLT		= OPS_IDLE_ROUTE | 1 | ( ROUTE_DEFAULT	<< 4 ),
+	OPS_ROUTE_IO		= OPS_IDLE_ROUTE | 1 | ( ROUTE_IO	<< 4 ),
+	OPS_ROUTE_HALT		= OPS_IDLE_ROUTE | 1 | ( ROUTE_HALT	<< 4 ),
+	OPS_ROUTE_MWAIT 	= OPS_IDLE_ROUTE | 1 | ( ROUTE_MWAIT	<< 4 ),
+	OPS_RECORDER		= 0x1000000000010000LLU,
+	OPS_RECORDER_RESET	= 0x1000000000010010LLU,
+	OPS_RECORDER_X002	= 0x1000000000010020LLU,
+	OPS_RECORDER_X010	= 0x1000000000010030LLU,
+	OPS_RECORDER_X020	= 0x1000000000010040LLU,
+	OPS_RECORDER_X060	= 0x1000000000010050LLU,
+	OPS_RECORDER_X090	= 0x1000000000010060LLU,
+	OPS_RECORDER_X120	= 0x1000000000010070LLU,
+	OPS_RECORDER_X240	= 0x1000000000010080LLU,
+	OPS_THERMAL_SCOPE	= 0x1000000000020000LLU,
+	OPS_VOLTAGE_SCOPE	= 0x1000000000021000LLU,
+	OPS_POWER_SCOPE 	= 0x1000000000022000LLU,
+	OPS_THERMAL_SCOPE_NONE	= OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_NONE),
+	OPS_THERMAL_SCOPE_SMT	= OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_SMT),
+	OPS_THERMAL_SCOPE_CORE	= OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_CORE),
+	OPS_THERMAL_SCOPE_PKG	= OPS_THERMAL_SCOPE|(7 ^ FORMULA_SCOPE_PKG),
+	OPS_VOLTAGE_SCOPE_NONE	= OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_NONE),
+	OPS_VOLTAGE_SCOPE_SMT	= OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_SMT),
+	OPS_VOLTAGE_SCOPE_CORE	= OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_CORE),
+	OPS_VOLTAGE_SCOPE_PKG	= OPS_VOLTAGE_SCOPE|(7 ^ FORMULA_SCOPE_PKG),
+	OPS_POWER_SCOPE_NONE	= OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_NONE),
+	OPS_POWER_SCOPE_SMT	= OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_SMT),
+	OPS_POWER_SCOPE_CORE	= OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_CORE),
+	OPS_POWER_SCOPE_PKG	= OPS_POWER_SCOPE | (7 ^ FORMULA_SCOPE_PKG),
+
+	BOXKEY_HWP		= 0x3000000000004020LLU,
+	BOXKEY_HWP_ON		= 0x3000000000004021LLU,
+	BOXKEY_HWP_EPP		= 0x3000000000004040LLU,
+	BOXKEY_HWP_EPP_MIN	= 0x3000000000004041LLU,
+	BOXKEY_HWP_EPP_020	= 0x3000000000004042LLU,
+	BOXKEY_HWP_EPP_040	= 0x3000000000004043LLU,
+	BOXKEY_HWP_EPP_060	= 0x3000000000004044LLU,
+	BOXKEY_HWP_EPP_MED	= 0x3000000000004045LLU,
+	BOXKEY_HWP_EPP_0A0	= 0x3000000000004046LLU,
+	BOXKEY_HWP_EPP_PWR	= 0x3000000000004047LLU,
+	BOXKEY_HWP_EPP_0E0	= 0x3000000000004048LLU,
+	BOXKEY_HWP_EPP_MAX	= 0x3000000000004049LLU,
+	BOXKEY_FMW_CPPC		= 0x3000000000004025LLU,
+	BOXKEY_FMW_CPPC_OFF	= 0x3000000000004027LLU,
+
+	BOXKEY_TOOLS_MACHINE	= 0x3000000000010000LLU,
+	BOXKEY_TOOLS_ATOMIC	= 0x3000000000010010LLU,
+	BOXKEY_TOOLS_CRC32	= 0x3000000000010020LLU,
+	BOXKEY_TOOLS_CONIC	= 0x3000000000011000LLU,
+	BOXKEY_TOOLS_CONIC0	= 0x3000000000011401LLU,
+	BOXKEY_TOOLS_CONIC1	= 0x3000000000011411LLU,
+	BOXKEY_TOOLS_CONIC2	= 0x3000000000011421LLU,
+	BOXKEY_TOOLS_CONIC3	= 0x3000000000011431LLU,
+	BOXKEY_TOOLS_CONIC4	= 0x3000000000011441LLU,
+	BOXKEY_TOOLS_CONIC5	= 0x3000000000011451LLU,
+	BOXKEY_TOOLS_TURBO_RND	= 0x3000000000012001LLU,
+	BOXKEY_TOOLS_TURBO_RR	= 0x3000000000012011LLU,
+	BOXKEY_TOOLS_TURBO_CPU	= 0x3000000000012021LLU,
+	BOXKEY_TOOLS_MONTE_CARLO= 0x3000000000012041LLU,
+
+	BOXKEY_LANG_ENGLISH	= 0x3000000000014021LLU,
+	BOXKEY_LANG_FRENCH	= 0x3000000000014022LLU,
+	BOXKEY_THEME_DFLT	= 0x3000000000014081LLU,
+	BOXKEY_THEME_USR1	= 0x3000000000014082LLU,
+	BOXKEY_THEME_USR2	= 0x3000000000014083LLU,
+
+	BOXKEY_LIMIT_IDLE_STATE = 0x3000000000014800LLU,
+	BOXKEY_LIMIT_IDLE_ST00	= 0x3000000000014801LLU,
+	BOXKEY_LIMIT_IDLE_ST01	= 0x3000000000014811LLU,
+	BOXKEY_LIMIT_IDLE_ST02	= 0x3000000000014821LLU,
+	BOXKEY_LIMIT_IDLE_ST03	= 0x3000000000014831LLU,
+	BOXKEY_LIMIT_IDLE_ST04	= 0x3000000000014841LLU,
+	BOXKEY_LIMIT_IDLE_ST05	= 0x3000000000014851LLU,
+	BOXKEY_LIMIT_IDLE_ST06	= 0x3000000000014861LLU,
+	BOXKEY_LIMIT_IDLE_ST07	= 0x3000000000014871LLU,
+	BOXKEY_LIMIT_IDLE_ST08	= 0x3000000000014881LLU,
+	BOXKEY_LIMIT_IDLE_ST09	= 0x3000000000014891LLU,
+	BOXKEY_LIMIT_IDLE_ST10	= 0x30000000000148a1LLU,
+
+	BOXKEY_CLR_ALL_EVENTS	= BOXKEY_EVT_OR ^ 0x1,
+	BOXKEY_CLR_THM_SENSOR	= BOXKEY_EVT_OR | (LSHIFT_THERMAL_LOG	<< 1),
+	BOXKEY_CLR_PROCHOT_LOG	= BOXKEY_EVT_OR | (LSHIFT_PROCHOT_LOG	<< 1),
+	BOXKEY_CLR_THM_CRIT	= BOXKEY_EVT_OR | (LSHIFT_CRITIC_LOG	<< 1),
+	BOXKEY_CLR_THM_THOLD1	= BOXKEY_EVT_OR | (LSHIFT_THOLD1_LOG	<< 1),
+	BOXKEY_CLR_THM_THOLD2	= BOXKEY_EVT_OR | (LSHIFT_THOLD2_LOG	<< 1),
+	BOXKEY_CLR_PWR_LIMIT	= BOXKEY_EVT_OR | (LSHIFT_POWER_LIMIT	<< 1),
+	BOXKEY_CLR_CUR_LIMIT	= BOXKEY_EVT_OR | (LSHIFT_CURRENT_LIMIT << 1),
+	BOXKEY_CLR_X_DOMAIN	= BOXKEY_EVT_OR | (LSHIFT_CROSS_DOMAIN	<< 1),
+	BOXKEY_CLR_CORE_HOT	= BOXKEY_EVT_OR | (LSHIFT_CORE_HOT_LOG	<< 1),
+	BOXKEY_CLR_CORE_THM	= BOXKEY_EVT_OR | (LSHIFT_CORE_THM_LOG	<< 1),
+	BOXKEY_CLR_CORE_RES	= BOXKEY_EVT_OR | (LSHIFT_CORE_RES_LOG	<< 1),
+	BOXKEY_CLR_CORE_AVG	= BOXKEY_EVT_OR | (LSHIFT_CORE_AVG_LOG	<< 1),
+	BOXKEY_CLR_CORE_VRT	= BOXKEY_EVT_OR | (LSHIFT_CORE_VRT_LOG	<< 1),
+	BOXKEY_CLR_CORE_TDC	= BOXKEY_EVT_OR | (LSHIFT_CORE_TDC_LOG	<< 1),
+	BOXKEY_CLR_CORE_PL1	= BOXKEY_EVT_OR | (LSHIFT_CORE_PL1_LOG	<< 1),
+	BOXKEY_CLR_CORE_PL2	= BOXKEY_EVT_OR | (LSHIFT_CORE_PL2_LOG	<< 1),
+	BOXKEY_CLR_CORE_EDP	= BOXKEY_EVT_OR | (LSHIFT_CORE_EDP_LOG	<< 1),
+	BOXKEY_CLR_CORE_BST	= BOXKEY_EVT_OR | (LSHIFT_CORE_BST_LOG	<< 1),
+	BOXKEY_CLR_CORE_ATT	= BOXKEY_EVT_OR | (LSHIFT_CORE_ATT_LOG	<< 1),
+	BOXKEY_CLR_CORE_TVB	= BOXKEY_EVT_OR | (LSHIFT_CORE_TVB_LOG	<< 1),
+	BOXKEY_CLR_GFX_HOT	= BOXKEY_EVT_OR | (LSHIFT_GFX_HOT_LOG	<< 1),
+	BOXKEY_CLR_GFX_THM	= BOXKEY_EVT_OR | (LSHIFT_GFX_THM_LOG	<< 1),
+	BOXKEY_CLR_GFX_AVG	= BOXKEY_EVT_OR | (LSHIFT_GFX_AVG_LOG	<< 1),
+	BOXKEY_CLR_GFX_VRT	= BOXKEY_EVT_OR | (LSHIFT_GFX_VRT_LOG	<< 1),
+	BOXKEY_CLR_GFX_TDC	= BOXKEY_EVT_OR | (LSHIFT_GFX_TDC_LOG	<< 1),
+	BOXKEY_CLR_GFX_PL1	= BOXKEY_EVT_OR | (LSHIFT_GFX_PL1_LOG	<< 1),
+	BOXKEY_CLR_GFX_PL2	= BOXKEY_EVT_OR | (LSHIFT_GFX_PL2_LOG	<< 1),
+	BOXKEY_CLR_GFX_EDP	= BOXKEY_EVT_OR | (LSHIFT_GFX_EDP_LOG	<< 1),
+	BOXKEY_CLR_GFX_EFF	= BOXKEY_EVT_OR | (LSHIFT_GFX_EFF_LOG	<< 1),
+	BOXKEY_CLR_RING_HOT	= BOXKEY_EVT_OR | (LSHIFT_RING_HOT_LOG	<< 1),
+	BOXKEY_CLR_RING_THM	= BOXKEY_EVT_OR | (LSHIFT_RING_THM_LOG	<< 1),
+	BOXKEY_CLR_RING_AVG	= BOXKEY_EVT_OR | (LSHIFT_RING_AVG_LOG	<< 1),
+	BOXKEY_CLR_RING_VRT	= BOXKEY_EVT_OR | (LSHIFT_RING_VRT_LOG	<< 1),
+	BOXKEY_CLR_RING_TDC	= BOXKEY_EVT_OR | (LSHIFT_RING_TDC_LOG	<< 1),
+	BOXKEY_CLR_RING_PL1	= BOXKEY_EVT_OR | (LSHIFT_RING_PL1_LOG	<< 1),
+	BOXKEY_CLR_RING_PL2	= BOXKEY_EVT_OR | (LSHIFT_RING_PL2_LOG	<< 1),
+	BOXKEY_CLR_RING_EDP	= BOXKEY_EVT_OR | (LSHIFT_RING_EDP_LOG	<< 1),
+
+	BOXKEY_TDP_PKG		= BOXKEY_TDP_OR | (PWR_DOMAIN(PKG)	<< 5),
+	BOXKEY_TDP_CORES	= BOXKEY_TDP_OR | (PWR_DOMAIN(CORES)	<< 5),
+	BOXKEY_TDP_UNCORE	= BOXKEY_TDP_OR | (PWR_DOMAIN(UNCORE)	<< 5),
+	BOXKEY_TDP_RAM		= BOXKEY_TDP_OR | (PWR_DOMAIN(RAM)	<< 5),
+	BOXKEY_TDP_PLATFORM	= BOXKEY_TDP_OR | (PWR_DOMAIN(PLATFORM) << 5),
+
+	BOXKEY_TW1_PKG		= BOXKEY_TW_OR | (PWR_DOMAIN(PKG)     << 5)|PL1,
+	BOXKEY_TW1_CORES	= BOXKEY_TW_OR | (PWR_DOMAIN(CORES)   << 5)|PL1,
+	BOXKEY_TW1_UNCORE	= BOXKEY_TW_OR | (PWR_DOMAIN(UNCORE)  << 5)|PL1,
+	BOXKEY_TW1_RAM		= BOXKEY_TW_OR | (PWR_DOMAIN(RAM)     << 5)|PL1,
+	BOXKEY_TW1_PLATFORM	= BOXKEY_TW_OR | (PWR_DOMAIN(PLATFORM)<< 5)|PL1,
+	BOXKEY_TW2_PKG		= BOXKEY_TW_OR | (PWR_DOMAIN(PKG)     << 5)|PL2,
+	BOXKEY_TW2_CORES	= BOXKEY_TW_OR | (PWR_DOMAIN(CORES)   << 5)|PL2,
+	BOXKEY_TW2_UNCORE	= BOXKEY_TW_OR | (PWR_DOMAIN(UNCORE)  << 5)|PL2,
+	BOXKEY_TW2_RAM		= BOXKEY_TW_OR | (PWR_DOMAIN(RAM)     << 5)|PL2,
+	BOXKEY_TW2_PLATFORM	= BOXKEY_TW_OR | (PWR_DOMAIN(PLATFORM)<< 5)|PL2,
+
+	BOXKEY_TDC		= BOXKEY_TDC_OR,
+
+	BOXKEY_THM		= BOXKEY_THM_OR,
+
+	BOXKEY_TURBO_CLOCK_1C	= ((BOXKEY_TURBO_CLOCK_NC |  1) << 32),
+	BOXKEY_TURBO_CLOCK_2C	= ((BOXKEY_TURBO_CLOCK_NC |  2) << 32),
+	BOXKEY_TURBO_CLOCK_3C	= ((BOXKEY_TURBO_CLOCK_NC |  3) << 32),
+	BOXKEY_TURBO_CLOCK_4C	= ((BOXKEY_TURBO_CLOCK_NC |  4) << 32),
+	BOXKEY_TURBO_CLOCK_5C	= ((BOXKEY_TURBO_CLOCK_NC |  5) << 32),
+	BOXKEY_TURBO_CLOCK_6C	= ((BOXKEY_TURBO_CLOCK_NC |  6) << 32),
+	BOXKEY_TURBO_CLOCK_7C	= ((BOXKEY_TURBO_CLOCK_NC |  7) << 32),
+	BOXKEY_TURBO_CLOCK_8C	= ((BOXKEY_TURBO_CLOCK_NC |  8) << 32),
+	BOXKEY_TURBO_CLOCK_9C	= ((BOXKEY_TURBO_CLOCK_NC |  9) << 32),
+	BOXKEY_TURBO_CLOCK_10C	= ((BOXKEY_TURBO_CLOCK_NC | 10) << 32),
+	BOXKEY_TURBO_CLOCK_11C	= ((BOXKEY_TURBO_CLOCK_NC | 11) << 32),
+	BOXKEY_TURBO_CLOCK_12C	= ((BOXKEY_TURBO_CLOCK_NC | 12) << 32),
+	BOXKEY_TURBO_CLOCK_13C	= ((BOXKEY_TURBO_CLOCK_NC | 13) << 32),
+	BOXKEY_TURBO_CLOCK_14C	= ((BOXKEY_TURBO_CLOCK_NC | 14) << 32),
+	BOXKEY_TURBO_CLOCK_15C	= ((BOXKEY_TURBO_CLOCK_NC | 15) << 32),
+	BOXKEY_TURBO_CLOCK_16C	= ((BOXKEY_TURBO_CLOCK_NC | 16) << 32),
+	BOXKEY_TURBO_CLOCK_17C	= ((BOXKEY_TURBO_CLOCK_NC | 17) << 32),
+	BOXKEY_TURBO_CLOCK_18C	= ((BOXKEY_TURBO_CLOCK_NC | 18) << 32),
+
+	BOXKEY_RATIO_CLOCK_TGT	= ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_TGT) << 32),
+	BOXKEY_RATIO_CLOCK_MAX	= ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MAX) << 32),
+	BOXKEY_RATIO_CLOCK_MIN	= ((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_MIN) << 32),
+    BOXKEY_RATIO_CLOCK_HWP_TGT =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_TGT)<<32),
+    BOXKEY_RATIO_CLOCK_HWP_MAX =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MAX)<<32),
+    BOXKEY_RATIO_CLOCK_HWP_MIN =((BOXKEY_RATIO_CLOCK_OR|CLOCK_MOD_HWP_MIN)<<32),
+
+	BOXKEY_RATIO_ACTIVATION =((BOXKEY_CFGTDP_CLOCK_OR|CLOCK_MOD_ACT) << 32),
+
+	BOXKEY_UNCORE_CLOCK_MAX =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MAX) << 32),
+	BOXKEY_UNCORE_CLOCK_MIN =((BOXKEY_UNCORE_CLOCK_OR|CLOCK_MOD_MIN) << 32)
+};
+
+#if defined(FEAT_DBG) && (FEAT_DBG >= 9) && (FEAT_DBG < 100)
+#define CHECK_DUPLICATE_KEY(_val)		\
+int CheckDuplicateKey(void)			\
+{	enum KEY_ENUM _key = _val;		\
+	switch (_key) { 			\
+	case SORTBY_STATE:			\
+	case SORTBY_RTIME:			\
+	case SORTBY_UTIME:			\
+	case SORTBY_STIME:			\
+	case SORTBY_PID:			\
+	case SORTBY_COMM:			\
+						\
+	case OPS_INTERVAL:			\
+	case OPS_INTERVAL_100:			\
+	case OPS_INTERVAL_150:			\
+	case OPS_INTERVAL_250:			\
+	case OPS_INTERVAL_500:			\
+	case OPS_INTERVAL_750:			\
+	case OPS_INTERVAL_1000: 		\
+	case OPS_INTERVAL_1500: 		\
+	case OPS_INTERVAL_2000: 		\
+	case OPS_INTERVAL_2500: 		\
+	case OPS_INTERVAL_3000: 		\
+	case OPS_AUTOCLOCK:			\
+	case OPS_AUTOCLOCK_OFF: 		\
+	case OPS_AUTOCLOCK_ON:			\
+	case OPS_EXPERIMENTAL:			\
+	case OPS_EXPERIMENTAL_OFF:		\
+	case OPS_EXPERIMENTAL_ON:		\
+	case OPS_INTERRUPTS:			\
+	case OPS_INTERRUPTS_OFF:		\
+	case OPS_INTERRUPTS_ON: 		\
+	case OPS_CPU_IDLE:			\
+	case OPS_CPU_IDLE_OFF:			\
+	case OPS_CPU_IDLE_ON:			\
+	case OPS_CPU_FREQ:			\
+	case OPS_CPU_FREQ_OFF:			\
+	case OPS_CPU_FREQ_ON:			\
+	case OPS_GOVERNOR:			\
+	case OPS_GOVERNOR_OFF:			\
+	case OPS_GOVERNOR_ON:			\
+	case OPS_CLOCK_SOURCE:			\
+	case OPS_CLOCK_SOURCE_1:		\
+	case OPS_CLOCK_SOURCE_2:		\
+	case OPS_CLOCK_SOURCE_3:		\
+	case OPS_CLOCK_SOURCE_4:		\
+	case OPS_CLOCK_SOURCE_5:		\
+	case OPS_CLOCK_SOURCE_6:		\
+	case OPS_CLOCK_SOURCE_7:		\
+	case OPS_CLOCK_SOURCE_SEL:		\
+	case OPS_CLOCK_SOURCE_OFF:		\
+	case OPS_CLOCK_SOURCE_ON:		\
+	case OPS_IDLE_ROUTE:			\
+	case OPS_ROUTE_DFLT:			\
+	case OPS_ROUTE_IO:			\
+	case OPS_ROUTE_HALT:			\
+	case OPS_ROUTE_MWAIT:			\
+	case OPS_RECORDER:			\
+	case OPS_RECORDER_RESET:		\
+	case OPS_RECORDER_X002: 		\
+	case OPS_RECORDER_X010: 		\
+	case OPS_RECORDER_X020: 		\
+	case OPS_RECORDER_X060: 		\
+	case OPS_RECORDER_X090: 		\
+	case OPS_RECORDER_X120: 		\
+	case OPS_RECORDER_X240: 		\
+	case OPS_THERMAL_SCOPE: 		\
+	case OPS_VOLTAGE_SCOPE: 		\
+	case OPS_POWER_SCOPE:			\
+	case OPS_THERMAL_SCOPE_NONE:		\
+	case OPS_THERMAL_SCOPE_SMT:		\
+	case OPS_THERMAL_SCOPE_CORE:		\
+	case OPS_THERMAL_SCOPE_PKG:		\
+	case OPS_VOLTAGE_SCOPE_NONE:		\
+	case OPS_VOLTAGE_SCOPE_SMT:		\
+	case OPS_VOLTAGE_SCOPE_CORE:		\
+	case OPS_VOLTAGE_SCOPE_PKG:		\
+	case OPS_POWER_SCOPE_NONE:		\
+	case OPS_POWER_SCOPE_SMT:		\
+	case OPS_POWER_SCOPE_CORE:		\
+	case OPS_POWER_SCOPE_PKG:		\
+	case BOXKEY_HWP:			\
+	case BOXKEY_HWP_ON:			\
+	case BOXKEY_HWP_EPP:			\
+	case BOXKEY_HWP_EPP_MIN:		\
+	case BOXKEY_HWP_EPP_020:		\
+	case BOXKEY_HWP_EPP_040:		\
+	case BOXKEY_HWP_EPP_060:		\
+	case BOXKEY_HWP_EPP_MED:		\
+	case BOXKEY_HWP_EPP_0A0:		\
+	case BOXKEY_HWP_EPP_PWR:		\
+	case BOXKEY_HWP_EPP_0E0:		\
+	case BOXKEY_HWP_EPP_MAX:		\
+	case BOXKEY_FMW_CPPC:			\
+	case BOXKEY_FMW_CPPC_OFF:		\
+						\
+	case BOXKEY_TOOLS_MACHINE:		\
+	case BOXKEY_TOOLS_ATOMIC:		\
+	case BOXKEY_TOOLS_CRC32:		\
+	case BOXKEY_TOOLS_CONIC:		\
+	case BOXKEY_TOOLS_CONIC0:		\
+	case BOXKEY_TOOLS_CONIC1:		\
+	case BOXKEY_TOOLS_CONIC2:		\
+	case BOXKEY_TOOLS_CONIC3:		\
+	case BOXKEY_TOOLS_CONIC4:		\
+	case BOXKEY_TOOLS_CONIC5:		\
+	case BOXKEY_TOOLS_TURBO_RND:		\
+	case BOXKEY_TOOLS_TURBO_RR:		\
+	case BOXKEY_TOOLS_TURBO_CPU:		\
+	case BOXKEY_TOOLS_MONTE_CARLO:		\
+						\
+	case BOXKEY_LANG_ENGLISH:		\
+	case BOXKEY_LANG_FRENCH:		\
+	case BOXKEY_THEME_DFLT: 		\
+	case BOXKEY_THEME_USR1: 		\
+	case BOXKEY_THEME_USR2: 		\
+						\
+	case BOXKEY_LIMIT_IDLE_STATE:		\
+	case BOXKEY_LIMIT_IDLE_ST00:		\
+	case BOXKEY_LIMIT_IDLE_ST01:		\
+	case BOXKEY_LIMIT_IDLE_ST02:		\
+	case BOXKEY_LIMIT_IDLE_ST03:		\
+	case BOXKEY_LIMIT_IDLE_ST04:		\
+	case BOXKEY_LIMIT_IDLE_ST05:		\
+	case BOXKEY_LIMIT_IDLE_ST06:		\
+	case BOXKEY_LIMIT_IDLE_ST07:		\
+	case BOXKEY_LIMIT_IDLE_ST08:		\
+	case BOXKEY_LIMIT_IDLE_ST09:		\
+	case BOXKEY_LIMIT_IDLE_ST10:		\
+						\
+	case BOXKEY_CLR_ALL_EVENTS:		\
+	case BOXKEY_CLR_THM_SENSOR:		\
+	case BOXKEY_CLR_PROCHOT_LOG:		\
+	case BOXKEY_CLR_THM_CRIT:		\
+	case BOXKEY_CLR_THM_THOLD1:		\
+	case BOXKEY_CLR_THM_THOLD2:		\
+	case BOXKEY_CLR_PWR_LIMIT:		\
+	case BOXKEY_CLR_CUR_LIMIT:		\
+	case BOXKEY_CLR_X_DOMAIN:		\
+	case BOXKEY_CLR_CORE_HOT:		\
+	case BOXKEY_CLR_CORE_THM:		\
+	case BOXKEY_CLR_CORE_RES:		\
+	case BOXKEY_CLR_CORE_AVG:		\
+	case BOXKEY_CLR_CORE_VRT:		\
+	case BOXKEY_CLR_CORE_TDC:		\
+	case BOXKEY_CLR_CORE_PL1:		\
+	case BOXKEY_CLR_CORE_PL2:		\
+	case BOXKEY_CLR_CORE_EDP:		\
+	case BOXKEY_CLR_CORE_BST:		\
+	case BOXKEY_CLR_CORE_ATT:		\
+	case BOXKEY_CLR_CORE_TVB:		\
+	case BOXKEY_CLR_GFX_HOT:		\
+	case BOXKEY_CLR_GFX_THM:		\
+	case BOXKEY_CLR_GFX_AVG:		\
+	case BOXKEY_CLR_GFX_VRT:		\
+	case BOXKEY_CLR_GFX_TDC:		\
+	case BOXKEY_CLR_GFX_PL1:		\
+	case BOXKEY_CLR_GFX_PL2:		\
+	case BOXKEY_CLR_GFX_EDP:		\
+	case BOXKEY_CLR_GFX_EFF:		\
+	case BOXKEY_CLR_RING_HOT:		\
+	case BOXKEY_CLR_RING_THM:		\
+	case BOXKEY_CLR_RING_AVG:		\
+	case BOXKEY_CLR_RING_VRT:		\
+	case BOXKEY_CLR_RING_TDC:		\
+	case BOXKEY_CLR_RING_PL1:		\
+	case BOXKEY_CLR_RING_PL2:		\
+	case BOXKEY_CLR_RING_EDP:		\
+						\
+	case BOXKEY_TDP_PKG:			\
+	case BOXKEY_TDP_CORES:			\
+	case BOXKEY_TDP_UNCORE: 		\
+	case BOXKEY_TDP_RAM:			\
+	case BOXKEY_TDP_PLATFORM:		\
+						\
+	case BOXKEY_TW1_PKG:			\
+	case BOXKEY_TW1_CORES:			\
+	case BOXKEY_TW1_UNCORE: 		\
+	case BOXKEY_TW1_RAM:			\
+	case BOXKEY_TW1_PLATFORM:		\
+	case BOXKEY_TW2_PKG:			\
+	case BOXKEY_TW2_CORES:			\
+	case BOXKEY_TW2_UNCORE:			\
+	case BOXKEY_TW2_RAM:			\
+	case BOXKEY_TW2_PLATFORM:		\
+						\
+	case BOXKEY_TDC:			\
+						\
+	case BOXKEY_THM:			\
+						\
+	case BOXKEY_TURBO_CLOCK_1C:		\
+	case BOXKEY_TURBO_CLOCK_2C:		\
+	case BOXKEY_TURBO_CLOCK_3C:		\
+	case BOXKEY_TURBO_CLOCK_4C:		\
+	case BOXKEY_TURBO_CLOCK_5C:		\
+	case BOXKEY_TURBO_CLOCK_6C:		\
+	case BOXKEY_TURBO_CLOCK_7C:		\
+	case BOXKEY_TURBO_CLOCK_8C:		\
+	case BOXKEY_TURBO_CLOCK_9C:		\
+	case BOXKEY_TURBO_CLOCK_10C:		\
+	case BOXKEY_TURBO_CLOCK_11C:		\
+	case BOXKEY_TURBO_CLOCK_12C:		\
+	case BOXKEY_TURBO_CLOCK_13C:		\
+	case BOXKEY_TURBO_CLOCK_14C:		\
+	case BOXKEY_TURBO_CLOCK_15C:		\
+	case BOXKEY_TURBO_CLOCK_16C:		\
+	case BOXKEY_TURBO_CLOCK_17C:		\
+	case BOXKEY_TURBO_CLOCK_18C:		\
+						\
+	case BOXKEY_RATIO_CLOCK_TGT:		\
+	case BOXKEY_RATIO_CLOCK_MAX:		\
+	case BOXKEY_RATIO_CLOCK_MIN:		\
+	case BOXKEY_RATIO_CLOCK_HWP_TGT:	\
+	case BOXKEY_RATIO_CLOCK_HWP_MAX:	\
+	case BOXKEY_RATIO_CLOCK_HWP_MIN:	\
+						\
+	case BOXKEY_RATIO_ACTIVATION:		\
+						\
+	case BOXKEY_UNCORE_CLOCK_MAX:		\
+	case BOXKEY_UNCORE_CLOCK_MIN:		\
+		return 0;			\
+	}					\
+	return -1;				\
+}
+#else
+#define CHECK_DUPLICATE_KEY(_val)
+#endif /* FEAT_DBG */
+
+#define POWERED(bit)	( (bit) ? (char*) RSC(PRESENT).CODE()		\
+				: (char*) RSC(MISSING).CODE() )
+
+#define ENABLED(bit)	( (bit) ? (char*) RSC(ON).CODE()		\
+				: (char*) RSC(OFF).CODE() )
+
+#define MARGIN_WIDTH	2
+#define MARGIN_HEIGHT	1
+#define INTER_WIDTH	3
+#define INTER_HEIGHT	(3 + 1)
+#define LEADING_LEFT	(MIN_WIDTH / (MARGIN_WIDTH + (4 * INTER_WIDTH)))
+#define LEADING_TOP	1
+
+#define LOAD_LEAD	4
+
+typedef struct {
+	Coordinate	origin;
+	CUINT		length;
+	ATTRIBUTE	*attr;
+	ASCII		*code;
+} LAYER_DECL_ST;
+
+#define LayerDeclare(_ID, _len, _col, _row, _var)			\
+	LAYER_DECL_ST _var = {						\
+			.origin = {					\
+				.col = _col,				\
+				.row = _row				\
+		},							\
+			.length = _len,					\
+			.attr = RSC(_ID).ATTR(),			\
+			.code = RSC(_ID).CODE() 			\
+	}
+
+typedef char HBCLK[11 + 1];
+
+enum DISPOSAL {
+	D_MAINVIEW,
+	D_DASHBOARD,
+	D_ASCIITEST
+};
+
+#define DISPOSAL_SIZE	(1 + D_ASCIITEST)
+
+enum VIEW {
+	V_FREQ,
+	V_INST,
+	V_CYCLES,
+	V_CSTATES,
+	V_PACKAGE,
+	V_TASKS,
+	V_INTR,
+	V_SENSORS,
+	V_VOLTAGE,
+	V_ENERGY,
+	V_SLICE,
+	V_CUSTOM
+};
+
+#define VIEW_SIZE	(1 + V_CUSTOM)
+
+typedef void (*DISPOSAL_FUNC)(Layer*);
+
+typedef CUINT (*VIEW_FUNC)(Layer*, const unsigned int, CUINT);
+
+#define CELL_ARGS	Window *win,					\
+			unsigned long long key, 			\
+			ATTRIBUTE *attrib,				\
+			ASCII *item,					\
+			unsigned int *cellPadding
+
+typedef TGrid* (*CELL_FUNC)(CELL_ARGS);
+typedef void (*CPU_ITEM_CALLBACK)(unsigned int, ASCII*);
+typedef void (*PKG_ITEM_CALLBACK)(ASCII*);
+typedef void (*UPDATE_CALLBACK)(TGrid*, DATA_TYPE[]);
+
+#define RENDER_OK	0x000
+#define RENDER_KO	0x010
+#define RENDER_OFF	0x100
+
+#define RECORDER_DEFAULT 30
+
+#define RECORDER_COMPUTE(_recorder, _interval)				\
+({									\
+	_recorder.Reset = (	(_recorder.Ratios[_recorder.Select]	\
+				* RECORDER_DEFAULT			\
+				* 1000) / _interval );			\
+})
+
+#define RECORDER_SECONDS(_tick, _interval)				\
+	((_interval * _tick) / 1000)
+
+#if defined(UBENCH) && UBENCH == 1
+  #define Draw_uBenchmark(layer)					\
+  ({									\
+    if (Draw.Flag.uBench) {						\
+	int len = snprintf(Buffer, 20+1, "%llu", UBENCH_METRIC(0));	\
+	if (len > 0)							\
+		LayerFillAt(	layer, 0, 0, len, Buffer,		\
+				RSC(UI).ATTR()[UI_LAYOUT_UBENCH] );	\
+    }									\
+  })
+#else
+  #define Draw_uBenchmark(layer) {}
+#endif /* UBENCH */
+
+struct SETTING_ST {
+	unsigned int
+	fahrCels:  1-0, /* 0:Celsius || 1:Fahrenheit	*/
+	jouleWatt: 2-1, /* 0:Joule || 1:Watt		*/
+	secret	:  3-2, /* 0:Show || 1:Hide Secret Data */
+	_padding: 32-3;
+};
+
+struct RULER_ST {
+	double		Minimum,
+			Maximum,
+			Median;
+
+	unsigned int	Top[BOOST(SIZE)],
+			Uniq[BOOST(SIZE)],
+			Count;
+    struct TOPOF {
+	unsigned int	Top;
+	enum RATIO_BOOST Boost;
+    } TopOf;
+};
+
+struct DRAW_ST {
+    struct {
+    #ifndef NO_HEADER
+	double		TopAvg;
+    #endif
+    #ifndef NO_FOOTER
+	unsigned long	FreeRAM;
+	int		procCount;
+    #endif
+    } Cache;
+    struct {
+	unsigned int
+		layout	:  1-0 ,	/* Draw layout			*/
+		clear	:  2-1 ,	/* Clear screen 		*/
+		height	:  3-2 ,	/* Valid height 		*/
+		width	:  4-3 ,	/* Valid width			*/
+		daemon	:  5-4 ,	/* Draw dynamic 		*/
+		taskVal :  6-5 ,	/* Display task's value 	*/
+		avgOrPC :  7-6 ,	/* C-states average || % pkg states */
+		clkOrLd :  8-7 ,	/* Relative freq. || % load	*/
+	    #if defined(UBENCH) && UBENCH == 1
+		uBench	:  9-8 ,	/* Display UI micro-benchmark	*/
+	    #endif
+		_padding: 32-9 ;
+    } Flag;
+	enum VIEW	View;
+	enum DISPOSAL	Disposal;
+	SCREEN_SIZE	Size;
+    struct {
+		CUINT	MinHeight;
+		CUINT	MaxRows;
+		CUINT	LoadWidth;
+    #ifndef NO_FOOTER
+	struct {
+	    struct {
+		CUINT	Hot[2];
+	    } VoltTemp;
+	    struct {
+		CUINT	Count,
+			Free,
+			Total;
+	    } TaskMem;
+	} Footer;
+    #endif
+    } Area;
+	unsigned int	iClock,
+			cpuScroll,
+			Load;
+    struct {
+	unsigned int	Memory;
+    } Unit;
+	enum SMB_STRING SmbIndex;
+	enum THEMES	Theme;
+    #ifndef NO_UPPER
+	BitCC		garbage;
+    #endif /* NO_UPPER */
+};
+
+struct RECORDER_ST {
+	unsigned int	Reset,
+			Select,
+			Ratios[];
+};
+
+#define HOT_LOG_EVENT_FILTER (	EVENT_PROCHOT_LOG	\
+			|	EVENT_CRITIC_LOG	\
+			|	EVENT_CORE_HOT_LOG	\
+			|	EVENT_GFX_HOT_LOG	\
+			|	EVENT_RING_HOT_LOG	)
+
+#define HOT_STS_EVENT_FILTER (	EVENT_THERMAL_STS	\
+			|	EVENT_PROCHOT_STS	\
+			|	EVENT_CRITIC_TMP	\
+			|	EVENT_THOLD1_STS	\
+			|	EVENT_THOLD2_STS	\
+			|	EVENT_CORE_THM_STS	\
+			|	EVENT_CORE_HOT_STS	\
+			|	EVENT_GFX_THM_STS	\
+			|	EVENT_GFX_HOT_STS	\
+			|	EVENT_RING_THM_STS	\
+			|	EVENT_RING_HOT_STS	)
+
+#define STATUS_EVENT_FILTER (	EVENT_THERMAL_STS	\
+			|	EVENT_PROCHOT_STS	\
+			|	EVENT_CRITIC_TMP	\
+			|	EVENT_THOLD1_STS	\
+			|	EVENT_THOLD2_STS	)

riscv64/corefreq-ui.h

@@ -0,0 +1,974 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#ifdef NO_HEADER
+	#define TOP_HEADER_ROW	0
+#else
+	#define TOP_HEADER_ROW	3
+#endif
+
+#ifdef NO_FOOTER
+	#define TOP_FOOTER_ROW	0
+#else
+	#define TOP_FOOTER_ROW	2
+#endif
+
+#ifdef NO_UPPER
+	#define ADD_UPPER	0
+#else
+	#define ADD_UPPER	1
+#endif
+
+#ifdef NO_LOWER
+	#define ADD_LOWER	0
+#else
+	#define ADD_LOWER	1
+#endif
+
+#define TOP_SEPARATOR	(ADD_UPPER + (2 * ADD_LOWER))
+
+#define MAX_HEIGHT	((2 * CORE_COUNT)				\
+			+ 3	/*	HEADER_ROW	*/		\
+			+ 3	/*	SEPARATOR	*/		\
+			+ 2	/*	FOOTER_ROW	*/)
+
+#define MIN_HEIGHT	24
+
+#define MAX_WIDTH	320
+#define MIN_WIDTH	80
+
+#define CUMAX(M, m)	((M) > (m) ? (M) : (m))
+#define CUMIN(m, M)	((m) < (M) ? (m) : (M))
+
+typedef unsigned short int	CUINT;
+typedef signed short int	CSINT;
+
+/* VT100 requirements.							*/
+#define SCP	"\033[s"
+#define RCP	"\033[u"
+#define HIDE	"\033[?25l"
+#define SHOW	"\033[?25h"
+#define RESET	"\033c"
+#define SCR1	"\033[?47h"
+#define SCR0	"\033[?47l"
+#define CLS	"\033[J"
+#define CUH	"\033[H"
+#define CUP(col, row) "\033["#row";"#col"H"
+#define _LF	"\x0a"
+#define _FF	"\x0c"
+
+enum PALETTE {
+	_BLACK,
+	_RED,
+	_GREEN,
+	_YELLOW,
+	_BLUE,
+	_MAGENTA,
+	_CYAN,
+	_WHITE
+};
+
+#define BLACK	0
+#define RED	1
+#define GREEN	2
+#define YELLOW	3
+#define BLUE	4
+#define MAGENTA 5
+#define CYAN	6
+#define WHITE	7
+
+#define _COLOR(_mod, _fg, _bg) "\033["#_mod";3"#_fg";4"#_bg"m"
+#define COLOR(mod, fg, bg) _COLOR(mod, fg, bg)
+
+#define AoK	COLOR(0, WHITE, BLACK)
+#define DoK	COLOR(1, BLACK, BLACK)
+#define RoK	COLOR(1, RED, BLACK)
+#define GoK	COLOR(1, GREEN, BLACK)
+#define YoK	COLOR(1, YELLOW, BLACK)
+#define BoK	COLOR(1, BLUE, BLACK)
+#define MoK	COLOR(1, MAGENTA, BLACK)
+#define CoK	COLOR(1, CYAN, BLACK)
+#define WoK	COLOR(1, WHITE, BLACK)
+
+#define HSPACE	"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "	\
+		"        ""        ""        ""        ""        "
+
+#define HBAR	"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"	\
+		"||||||||""||||||||""||||||||""||||||||""||||||||"
+
+#define HLINE	"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"	\
+		"--------""--------""--------""--------""--------"
+
+typedef union {
+	unsigned long long key;
+	unsigned char code[8];
+} SCANKEY;
+
+#define SCANKEY_VOID		0x8000000000000000
+#define SCANKEY_NULL		0x0000000000000000
+#define SCANKEY_TAB		0x0000000000000009
+#define SCANKEY_ENTER		0x000000000000000a
+#define SCANKEY_ESC		0x000000000000001b
+#define SCANKEY_UP		0x0000000000415b1b
+#define SCANKEY_DOWN		0x0000000000425b1b
+#define SCANKEY_RIGHT		0x0000000000435b1b
+#define SCANKEY_LEFT		0x0000000000445b1b
+#define SCANKEY_HOME		0x0000000000485b1b
+#define SCANKEY_END		0x0000000000465b1b
+#define SCANKEY_F1		0x0000000000504f1b
+#define SCANKEY_F2		0x0000000000514f1b
+#define SCANKEY_F3		0x0000000000524f1b
+#define SCANKEY_F4		0x0000000000534f1b
+#define SCANKEY_F10		0x0000007e31325b1b
+#define SCANKEY_SHIFT_TAB	0x00000000005a5b1b
+#define SCANKEY_PGUP		0x000000007e355b1b
+#define SCANKEY_PGDW		0x000000007e365b1b
+#define SCANKEY_EXCL		0x0000000000000021
+#define SCANKEY_HASH		0x0000000000000023
+#define SCANKEY_DOLLAR		0x0000000000000024
+#define SCANKEY_PERCENT 	0x0000000000000025
+#define SCANKEY_AST		0x000000000000002a
+#define SCANKEY_PLUS		0x000000000000002b
+#define SCANKEY_MINUS		0x000000000000002d
+#define SCANKEY_DOT		0x000000000000002e
+#define SCANKEY_SHIFT_UP	0x000041323b315b1b
+#define SCANKEY_SHIFT_DOWN	0x000042323b315b1b
+#define SCANKEY_SHIFT_RIGHT	0x000043323b315b1b
+#define SCANKEY_SHIFT_LEFT	0x000044323b315b1b
+#define SCANKEY_ALT_UP		0x000041333b315b1b
+#define SCANKEY_ALT_DOWN	0x000042333b315b1b
+#define SCANKEY_SHIFT_a 	0x0000000000000041
+#define SCANKEY_SHIFT_b 	0x0000000000000042
+#define SCANKEY_SHIFT_c 	0x0000000000000043
+#define SCANKEY_SHIFT_d 	0x0000000000000044
+#define SCANKEY_SHIFT_e 	0x0000000000000045
+#define SCANKEY_SHIFT_f 	0x0000000000000046
+#define SCANKEY_SHIFT_g 	0x0000000000000047
+#define SCANKEY_SHIFT_h 	0x0000000000000048
+#define SCANKEY_SHIFT_i 	0x0000000000000049
+#define SCANKEY_SHIFT_l 	0x000000000000004c
+#define SCANKEY_SHIFT_m 	0x000000000000004d
+#define SCANKEY_SHIFT_n 	0x000000000000004e
+#define SCANKEY_SHIFT_o 	0x000000000000004f
+#define SCANKEY_SHIFT_q 	0x0000000000000051
+#define SCANKEY_SHIFT_r 	0x0000000000000052
+#define SCANKEY_SHIFT_s 	0x0000000000000053
+#define SCANKEY_SHIFT_t 	0x0000000000000054
+#define SCANKEY_SHIFT_v 	0x0000000000000056
+#define SCANKEY_SHIFT_w 	0x0000000000000057
+#define SCANKEY_SHIFT_x 	0x0000000000000058
+#define SCANKEY_SHIFT_y 	0x0000000000000059
+#define SCANKEY_CTRL_p		0x0000000000000010
+#define SCANKEY_CTRL_u		0x0000000000000015
+#define SCANKEY_CTRL_x		0x0000000000000018
+#define SCANKEY_ALT_SHIFT_s	0x00000000000093c3
+#define SCANKEY_ALT_SHIFT_x	0x00000000000098c3
+#define SCANKEY_ALT_p		0x000000000000b0c3
+#define SCANKEY_ALT_s		0x000000000000b3c3
+#define SCANKEY_ALT_x		0x000000000000b8c3
+#define SCANKEY_CTRL_ALT_x 	0x00000000000098c2
+#define SCANKEY_a		0x0000000000000061
+#define SCANKEY_b		0x0000000000000062
+#define SCANKEY_c		0x0000000000000063
+#define SCANKEY_d		0x0000000000000064
+#define SCANKEY_e		0x0000000000000065
+#define SCANKEY_f		0x0000000000000066
+#define SCANKEY_g		0x0000000000000067
+#define SCANKEY_h		0x0000000000000068
+#define SCANKEY_i		0x0000000000000069
+#define SCANKEY_k		0x000000000000006b
+#define SCANKEY_l		0x000000000000006c
+#define SCANKEY_m		0x000000000000006d
+#define SCANKEY_n		0x000000000000006e
+#define SCANKEY_o		0x000000000000006f
+#define SCANKEY_p		0x0000000000000070
+#define SCANKEY_q		0x0000000000000071
+#define SCANKEY_r		0x0000000000000072
+#define SCANKEY_s		0x0000000000000073
+#define SCANKEY_t		0x0000000000000074
+#define SCANKEY_u		0x0000000000000075
+#define SCANKEY_v		0x0000000000000076
+#define SCANKEY_w		0x0000000000000077
+#define SCANKEY_x		0x0000000000000078
+#define SCANKEY_y		0x0000000000000079
+#define SCANKEY_z		0x000000000000007a
+#define SCANKEY_OPEN_BRACE	0x000000000000007b
+#define SCANKEY_CLOSE_BRACE	0x000000000000007d
+
+#define SCANCON_HOME		0x000000007e315b1b
+#define SCANCON_END		0x000000007e345b1b
+#define SCANCON_F1		0x00000000415b5b1b
+#define SCANCON_F2		0x00000000425b5b1b
+#define SCANCON_F3		0x00000000435b5b1b
+#define SCANCON_F4		0x00000000445b5b1b
+#define SCANCON_SHIFT_TAB	0x000000000000091b
+#define SCANCON_ALT_p		0x000000000000701b
+#define SCANCON_ALT_s		0x000000000000731b
+#define SCANCON_ALT_x		0x000000000000781b
+#define SCANCON_CTRL_ALT_x 	0x000000000000181b
+
+#define SCANSYM_HOME		0x000000007e375b1b
+#define SCANSYM_END		0x000000007e385b1b
+#define SCANSYM_F1		0x0000007e31315b1b
+#define SCANSYM_F2		0x0000007e32315b1b
+#define SCANSYM_F3		0x0000007e33315b1b
+#define SCANSYM_F4		0x0000007e34315b1b
+#define SCANSYM_SHIFT_UP	0x0000000000615b1b
+#define SCANSYM_SHIFT_DOWN	0x0000000000625b1b
+#define SCANSYM_SHIFT_RIGHT	0x0000000000635b1b
+#define SCANSYM_SHIFT_LEFT	0x0000000000645b1b
+#define SCANSYM_ALT_UP		0x00000000415b1b1b
+#define SCANSYM_ALT_DOWN	0x00000000425b1b1b
+
+typedef struct {
+	int	width,
+		height;
+} SCREEN_SIZE;
+
+typedef struct {
+	CUINT	col,
+		row;
+} Coordinate;
+
+typedef struct {
+	CSINT	horz,
+		vert;
+} CoordShift;
+
+typedef struct {
+	CUINT	wth,
+		hth;
+} CoordSize;
+
+typedef union {
+	unsigned char	value;
+	struct {
+	unsigned char	fg:  3-0,
+			un:  4-3,
+			bg:  7-4,
+			bf:  8-7;
+	};
+} ATTRIBUTE;
+
+#define MakeAttr(_fg, _un, _bg, _bf)					\
+	({ATTRIBUTE _attr={.fg = _fg,.un = _un,.bg = _bg,.bf = _bf}; _attr;})
+
+#define HDK	{.fg = BLACK,	.bg = BLACK,	.bf = 1}
+#define HRK	{.fg = RED,	.bg = BLACK,	.bf = 1}
+#define HGK	{.fg = GREEN,	.bg = BLACK,	.bf = 1}
+#define HYK	{.fg = YELLOW,	.bg = BLACK,	.bf = 1}
+#define HBK	{.fg = BLUE,	.bg = BLACK,	.bf = 1}
+#define HMK	{.fg = MAGENTA, .bg = BLACK,	.bf = 1}
+#define HCK	{.fg = CYAN,	.bg = BLACK,	.bf = 1}
+#define HWK	{.fg = WHITE,	.bg = BLACK,	.bf = 1}
+#define HKB	{.fg = BLACK,	.bg = BLUE,	.bf = 1}
+#define HWB	{.fg = WHITE,	.bg = BLUE,	.bf = 1}
+#define HKM	{.fg = BLACK,	.bg = MAGENTA,	.bf = 1}
+#define HWC	{.fg = WHITE,	.bg = CYAN,	.bf = 1}
+#define HKW	{.fg = BLACK,	.bg = WHITE,	.bf = 1}
+#define HRW	{.fg = RED,	.bg = WHITE,	.bf = 1}
+#define HYW	{.fg = YELLOW,	.bg = WHITE,	.bf = 1}
+#define HBW	{.fg = BLUE,	.bg = WHITE,	.bf = 1}
+#define HCW	{.fg = CYAN,	.bg = WHITE,	.bf = 1}
+#define HMW	{.fg = MAGENTA, .bg = WHITE,	.bf = 1}
+#define _HCK	{.fg = CYAN,	.bg = BLACK,	.un = 1,	.bf = 1}
+#define _HWK	{.fg = WHITE,	.bg = BLACK,	.un = 1,	.bf = 1}
+#define _HWB	{.fg = WHITE,	.bg = BLUE,	.un = 1,	.bf = 1}
+#define _HKW	{.fg = BLACK,	.bg = WHITE,	.un = 1,	.bf = 1}
+#define _HCW	{.fg = CYAN,	.bg = WHITE,	.un = 1,	.bf = 1}
+#define LDK	{.fg = BLACK,	.bg = BLACK}
+#define LRK	{.fg = RED,	.bg = BLACK}
+#define LGK	{.fg = GREEN,	.bg = BLACK}
+#define LYK	{.fg = YELLOW,	.bg = BLACK}
+#define LBK	{.fg = BLUE,	.bg = BLACK}
+#define LMK	{.fg = MAGENTA, .bg = BLACK}
+#define LCK	{.fg = CYAN,	.bg = BLACK}
+#define LWK	{.fg = WHITE,	.bg = BLACK}
+#define LKY	{.fg = BLACK,	.bg = YELLOW}
+#define LWB	{.fg = WHITE,	.bg = BLUE}
+#define LKM	{.fg = BLACK,	.bg = MAGENTA}
+#define LWM	{.fg = WHITE,	.bg = MAGENTA}
+#define LKC	{.fg = BLACK,	.bg = CYAN}
+#define LKW	{.fg = BLACK,	.bg = WHITE}
+#define LRW	{.fg = RED,	.bg = WHITE}
+#define LGW	{.fg = GREEN,	.bg = WHITE}
+#define LBW	{.fg = BLUE,	.bg = WHITE}
+#define LCW	{.fg = CYAN,	.bg = WHITE}
+#define LMW	{.fg = MAGENTA, .bg = WHITE}
+#define _LCK	{.fg = CYAN,	.bg = BLACK,	.un = 1}
+#define _LWK	{.fg = WHITE,	.bg = BLACK,	.un = 1}
+#define _LKM	{.fg = BLACK,	.bg = MAGENTA,	.un = 1}
+#define _LKW	{.fg = BLACK,	.bg = WHITE,	.un = 1}
+#define _LBW	{.fg = BLUE,	.bg = WHITE,	.un = 1}
+
+#define MAKE_TITLE_UNFOCUS	RSC(UI).ATTR()[UI_MAKE_TITLE_UNFOCUS]
+#define MAKE_TITLE_FOCUS	RSC(UI).ATTR()[UI_MAKE_TITLE_FOCUS]
+#define MAKE_BORDER_UNFOCUS	RSC(UI).ATTR()[UI_MAKE_BORDER_UNFOCUS]
+#define MAKE_BORDER_FOCUS	RSC(UI).ATTR()[UI_MAKE_BORDER_FOCUS]
+#define MAKE_SELECT_UNFOCUS	RSC(UI).ATTR()[UI_MAKE_SELECT_UNFOCUS]
+#define MAKE_SELECT_FOCUS	RSC(UI).ATTR()[UI_MAKE_SELECT_FOCUS]
+#define MAKE_PRINT_UNFOCUS	RSC(UI).ATTR()[UI_MAKE_PRINT_UNFOCUS]
+#define MAKE_PRINT_FOCUS	RSC(UI).ATTR()[UI_MAKE_PRINT_FOCUS]
+#define MAKE_PRINT_DROP 	RSC(UI).ATTR()[UI_MAKE_PRINT_DROP]
+
+typedef unsigned char	ASCII;
+
+typedef struct {
+	ASCII		*code;
+	ATTRIBUTE	*attr;
+	CoordSize	size;
+} Layer;
+
+typedef struct {
+	CoordSize	size;
+	Coordinate	origin,
+			select;
+	CoordShift	scroll;
+} Matrix;
+
+typedef struct {
+	SCANKEY 	quick;
+	ATTRIBUTE	*attr;
+	ASCII		*item;
+	size_t		length;
+} TCell;
+
+typedef struct {
+	ASCII		*comm;
+	size_t		length;
+} THover;
+
+typedef union {
+	void			*pvoid;
+	unsigned long long	*pullong;
+	signed long long	*psllong;
+	unsigned long		*pulong;
+	signed long		*pslong;
+	unsigned int		*puint;
+	signed int		*psint;
+
+	unsigned long long	ullong;
+	signed long long	sllong;
+	unsigned long		ulong;
+	signed long		slong;
+
+	struct {
+		unsigned int	uint[2];
+	};
+	struct {
+		signed int	sint[2];
+	};
+} DATA_TYPE;
+
+typedef struct _Grid {
+	TCell		cell;
+	THover		hover;
+	void		(*Update)(struct _Grid *grid, DATA_TYPE data[]);
+	DATA_TYPE	data[2];
+} TGrid;
+
+extern void Set_Data(TGrid*,	DATA_TYPE data, 		unsigned int) ;
+extern void Set_pVOID(TGrid*,	void *pVOID,			unsigned int) ;
+extern void Set_pULLONG(TGrid*, unsigned long long *pULLONG,	unsigned int) ;
+extern void Set_pSLLONG(TGrid*, signed long long *pSLLONG,	unsigned int) ;
+extern void Set_pULONG(TGrid*,	unsigned long *pULONG,		unsigned int) ;
+extern void Set_pSLONG(TGrid*,	signed long *pSLONG,		unsigned int) ;
+extern void Set_pUINT(TGrid*,	unsigned int *pUINT,		unsigned int) ;
+extern void Set_pSINT(TGrid*,	signed int *pSINT,		unsigned int) ;
+extern void Set_ULLONG(TGrid*,	unsigned long long _ULLONG,	unsigned int) ;
+extern void Set_SLLONG(TGrid*,	signed long long _SLLONG,	unsigned int) ;
+extern void Set_ULONG(TGrid*,	unsigned long _ULONG,		unsigned int) ;
+extern void Set_SLONG(TGrid*,	signed long _SLONG,		unsigned int) ;
+extern void Set_UINT(TGrid*,	unsigned int _UINT,		unsigned int) ;
+extern void Set_SINT(TGrid*,	signed int _SINT,		unsigned int) ;
+
+#define SET_DATA(_pGrid , _data , _order)				\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(DATA_TYPE)),		\
+			Set_Data,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(void *)) ,		\
+			Set_pVOID,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned long long *)),	\
+			Set_pULLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed long long *)),	\
+			Set_pSLLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned long *)) ,	\
+			Set_pULONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed long *)),		\
+			Set_pSLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned int *)) ,	\
+			Set_pUINT,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed int *)),		\
+			Set_pSINT,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned long long)) ,	\
+			Set_ULLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed long long)) ,	\
+			Set_SLLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned long)) , 	\
+			Set_ULONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed long)) ,		\
+			Set_SLONG,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(unsigned int)) ,		\
+			Set_UINT,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(signed int)) ,		\
+			Set_SINT,					\
+	__builtin_choose_expr(__builtin_types_compatible_p (		\
+		__typeof__(_data), __typeof__(COF_ST *)) ,		\
+			Set_pVOID,					\
+	(void)0)))))))))))))))(_pGrid, _data, _order)
+
+typedef struct _Stock {
+	struct _Stock	*next;
+
+	unsigned long long id;
+
+	struct Geometry {
+		Coordinate origin;
+	} geometry;
+} Stock;
+
+typedef struct {
+	Stock	*head,
+		*tail;
+} StockList;
+
+typedef enum {
+	WINFLAG_NO_FLAGS = 0,
+	WINFLAG_NO_STOCK = 1,
+	WINFLAG_NO_SCALE = 2,
+	WINFLAG_NO_BORDER= 4,
+	WINFLAG_NO_VSB	 = 8
+} WINDOW_FLAG;
+
+typedef struct _Win {
+	Layer		*layer;
+
+	unsigned long long id;
+
+	struct _Win	*prev,
+			*next;
+	struct {
+		void	(*Print)(struct _Win *win, void *list);
+	    struct {
+		int	(*Enter)(SCANKEY *scan, struct _Win *win);
+		void	(*Escape)(struct _Win *win);
+		void	(*Left)(struct _Win *win);
+		void	(*Right)(struct _Win *win);
+		void	(*Down)(struct _Win *win);
+		void	(*Up)(struct _Win *win);
+		void	(*Home)(struct _Win *win);
+		void	(*End)(struct _Win *win);
+		void	(*PgUp)(struct _Win *win);
+		void	(*PgDw)(struct _Win *win);
+		void	(*WinLeft)(struct _Win *win);
+		void	(*WinRight)(struct _Win *win);
+		void	(*WinDown)(struct _Win *win);
+		void	(*WinUp)(struct _Win *win);
+		void	(*Shrink)(struct _Win *win);
+		void	(*Expand)(struct _Win *win);
+	    } key;
+
+	    struct {
+	      ATTRIBUTE select,
+			border,
+			title;
+	    } color[2];
+
+		char	*title;
+	} hook;
+
+	Stock		*stock;
+	Matrix		matrix;
+	TGrid		*grid;
+	size_t		dim;
+
+	struct {
+		size_t	rowLen,
+			titleLen;
+	} lazyComp;
+
+	WINDOW_FLAG	flag;
+} Window;
+
+typedef struct {
+	Window	*head;
+} WinList;
+
+typedef void (*TCELLFUNC)(Window*, void*);
+typedef int  (*KEYFUNC)(SCANKEY*, Window*);
+typedef void (*WINFUNC)(Window*);
+typedef char REGSTR[];
+typedef char *REGPTR;
+
+extern ASCII hSpace[];
+extern ASCII hBar[];
+extern ASCII hLine[];
+
+extern Layer	*sLayer,
+		*dLayer,
+		*wLayer;
+
+extern WinList winList;
+
+extern int GetKey(SCANKEY *scan, struct timespec *tsec) ;
+
+extern SCREEN_SIZE GetScreenSize(void) ;
+
+extern TGrid *GridHover(TGrid *pGrid, const char *comment) ;
+
+extern void HookCellFunc(TCELLFUNC *with, TCELLFUNC what) ;
+
+extern void HookKeyFunc(KEYFUNC *with, KEYFUNC what) ;
+
+extern void HookWinFunc(WINFUNC *with, WINFUNC what) ;
+
+extern void HookAttrib(ATTRIBUTE *with, ATTRIBUTE what) ;
+
+extern void HookString(REGSTR *with, REGSTR what) ;
+
+extern void HookPointer(REGPTR *with, REGPTR what) ;
+
+#define StoreWindow(win, with, what)					\
+(									\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(TCELLFUNC)),HookCellFunc,\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(KEYFUNC)), HookKeyFunc,	\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(WINFUNC)), HookWinFunc,	\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(ATTRIBUTE)), HookAttrib ,\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(REGSTR) ), HookString,	\
+    __builtin_choose_expr(__builtin_types_compatible_p (		\
+	__typeof__(win->hook with), __typeof__(REGPTR) ), HookPointer,	\
+    (void)0))))))							\
+	(&(win->hook with), what)					\
+)
+
+#define GridCall_2xArg(gridCall, updateFunc)				\
+({									\
+	TGrid *pGrid = gridCall;					\
+	if (pGrid != NULL)						\
+	{								\
+		pGrid->Update = updateFunc;				\
+		pGrid->data[0].pvoid = NULL;				\
+		pGrid->data[1].pvoid = NULL;				\
+	}								\
+	pGrid;								\
+})
+
+#define GridCall_3xArg(gridCall, updateFunc,	arg0)			\
+({									\
+	TGrid *pGrid = gridCall;					\
+	if (pGrid != NULL)						\
+	{								\
+		pGrid->Update = updateFunc;				\
+		SET_DATA(pGrid, arg0, 0);				\
+		pGrid->data[1].pvoid = NULL;				\
+	}								\
+	pGrid;								\
+})
+
+#define GridCall_4xArg(gridCall, updateFunc,	arg0,	arg1)		\
+({									\
+	TGrid *pGrid = gridCall;					\
+	if (pGrid != NULL)						\
+	{								\
+		pGrid->Update = updateFunc;				\
+		SET_DATA(pGrid, arg0, 0);				\
+		SET_DATA(pGrid, arg1, 1);				\
+	}								\
+	pGrid;								\
+})
+
+#define DISPATCH_GridCall(_1,_2,_3,_4,_CURSOR, ... ) _CURSOR
+
+#define GridCall(...)							\
+	DISPATCH_GridCall( __VA_ARGS__ ,GridCall_4xArg ,		\
+					GridCall_3xArg ,		\
+					GridCall_2xArg ,		\
+					NULL)( __VA_ARGS__ )
+
+#define IndexAt(col, row)	((CUINT) col + (CUINT) row)
+
+#define LayerAt( layer, plane, col, row )				\
+	layer->plane[IndexAt(col, (row * layer->size.wth))]
+
+#define LayerFillAt(layer, col, row, len, source, attrib)		\
+({									\
+	memset(&LayerAt(layer, attr, col, row), attrib.value, (size_t) len); \
+	memcpy(&LayerAt(layer, code, col, row), source, (size_t) len);	\
+})
+
+#define LayerCopyAt(layer, col, row, len, attrib, source)		\
+({									\
+	memcpy(&LayerAt(layer, attr, col, row), attrib, (size_t) len);	\
+	memcpy(&LayerAt(layer, code, col, row), source, (size_t) len);	\
+})
+
+#define TGridAt(win, col, row)						\
+	win->grid[col + (row * win->matrix.size.wth)]
+
+#define TCellAt(win, col, row)						\
+	TGridAt(win, col, row).cell
+
+extern void DestroyLayer(Layer *layer) ;
+
+extern void CreateLayer(Layer *layer, CoordSize size) ;
+
+#define ResetLayer(layer, attrib)					\
+({									\
+	memset(layer->attr, attrib.value, layer->size.wth * layer->size.hth); \
+	memset(layer->code, 0x0, layer->size.wth * layer->size.hth);	\
+})
+
+#define ClearGarbage(_layer, _plane, _col, _row, _len, _value)		\
+({									\
+	memset(&LayerAt(_layer, _plane, _col, _row), _value, (size_t) _len); \
+})
+
+extern void FillLayerArea(Layer *layer,CUINT col, CUINT row,
+				CUINT width, CUINT height,
+				ASCII *source, ATTRIBUTE attrib) ;
+
+extern void AllocCopyAttr(TCell *cell, ATTRIBUTE attrib[]) ;
+
+extern void AllocFillAttr(TCell *cell, ATTRIBUTE attrib) ;
+
+extern void AllocCopyItem(TCell *cell, ASCII *item) ;
+
+extern void FreeAllTCells(Window *win) ;
+
+#define StoreTCell(win, shortkey, item, attrib) 			\
+({									\
+	TGrid *pGrid = NULL;						\
+  if (item != NULL)							\
+  {									\
+	win->dim++;							\
+									\
+	win->grid = realloc(win->grid, sizeof(TGrid) * win->dim);	\
+    if (win->grid != NULL)						\
+    {									\
+	pGrid = &win->grid[win->dim - 1];				\
+	pGrid->cell.quick.key = shortkey;				\
+	pGrid->cell.length = strlen((char *) item);			\
+	pGrid->hover.comm = NULL;					\
+	pGrid->hover.length = 0;					\
+	pGrid->Update = NULL;						\
+	pGrid->data[0].pvoid = NULL;					\
+	pGrid->data[1].pvoid = NULL;					\
+									\
+	__builtin_choose_expr(__builtin_types_compatible_p(		\
+		__typeof__(attrib),__typeof__(ATTRIBUTE[])),AllocCopyAttr,\
+	__builtin_choose_expr(__builtin_types_compatible_p(		\
+		__typeof__(attrib),__typeof__(ATTRIBUTE*)),AllocCopyAttr,\
+	__builtin_choose_expr(__builtin_types_compatible_p(		\
+		__typeof__(attrib),__typeof__(ATTRIBUTE)),AllocFillAttr,\
+	(void)0)))							\
+		(&pGrid->cell, attrib);					\
+									\
+	AllocCopyItem(&pGrid->cell, (ASCII *) item);			\
+    }									\
+  }									\
+	pGrid;								\
+})
+
+extern void DestroyWindow(Window *win) ;
+
+
+extern Window *CreateWindow_6xArg(Layer *layer, unsigned long long id,
+				CUINT width, CUINT height,
+				CUINT oCol, CUINT oRow) ;
+
+extern Window *CreateWindow_7xArg(Layer *layer, unsigned long long id,
+				CUINT width, CUINT height,
+				CUINT oCol, CUINT oRow, WINDOW_FLAG flag) ;
+
+#define DISPATCH_CreateWindow(_1,_2,_3,_4,_5,_6,_7, _CURSOR, ... ) _CURSOR
+
+#define CreateWindow(...)						\
+	DISPATCH_CreateWindow( __VA_ARGS__ ,				\
+				CreateWindow_7xArg ,			\
+				CreateWindow_6xArg ,			\
+				NULL,					\
+				NULL,					\
+				NULL,					\
+				NULL,					\
+				NULL)( __VA_ARGS__ )
+
+extern void RemoveWindow(Window *win, WinList *list) ;
+
+extern void AppendWindow(Window *win, WinList *list) ;
+
+extern void DestroyAllWindows(WinList *list) ;
+
+#define RemoveWinList(win, list)	RemoveNodeFromList(win, list)
+
+#define AppendWinList(win, list)	AppendNodeToList(win, list)
+
+extern void AnimateWindow(int rotate, WinList *list) ;
+
+extern Window *SearchWinListById(unsigned long long id, WinList *list) ;
+
+extern void PrintContent(Window *win, WinList *list, CUINT col, CUINT row) ;
+
+extern void ForEachCellPrint(Window *win, WinList *list) ;
+
+extern void EraseWindowWithBorder(Window *win) ;
+
+extern void PrintLCD(	Layer *layer, CUINT col, CUINT row,
+			int len, char *pStr, ATTRIBUTE lcdColor ) ;
+
+extern void MotionReset_Win(Window *win) ;
+
+extern void MotionLeft_Win(Window *win) ;
+
+extern void MotionRight_Win(Window *win) ;
+
+extern void MotionUp_Win(Window *win) ;
+
+extern void MotionDown_Win(Window *win) ;
+
+extern void MotionHome_Win(Window *win) ;
+
+extern void MotionEnd_Win(Window *win) ;
+
+extern void MotionTop_Win(Window *win) ;
+
+extern void MotionBottom_Win(Window *win) ;
+
+extern void MotionPgUp_Win(Window *win) ;
+
+extern void MotionPgDw_Win(Window *win) ;
+
+extern void MotionOriginLeft_Win(Window *win) ;
+
+extern void MotionOriginRight_Win(Window *win) ;
+
+extern void MotionOriginUp_Win(Window *win) ;
+
+extern void MotionOriginDown_Win(Window *win) ;
+
+extern void MotionShrink_Win(Window *win) ;
+
+extern void MotionExpand_Win(Window *win) ;
+
+extern void MotionUp_Wheel(Window *win) ;
+
+extern void MotionDown_Wheel(Window *win) ;
+
+extern void MotionPgUp_Wheel(Window *win) ;
+
+extern void MotionPgDw_Wheel(Window *win) ;
+
+extern void MotionHome_Wheel(Window *win) ;
+
+extern void MotionEnd_Wheel(Window *win) ;
+
+extern void ReScaleAllWindows(WinList *list) ;
+
+extern int Motion_Trigger(SCANKEY *scan, Window *win, WinList *list) ;
+
+extern void PrintWindowStack(WinList *winList) ;
+
+extern void WindowsUpdate(WinList *winList) ;
+
+#define EraseTCell_Menu(win)						\
+({									\
+	CoordShift shift = {						\
+		.horz = win->matrix.scroll.horz + win->matrix.select.col,\
+		.vert = win->matrix.scroll.vert + row			\
+	};								\
+	Coordinate cell = {						\
+		.col =	(win->matrix.origin.col				\
+			+ (win->matrix.select.col			\
+			* TCellAt(win, shift.horz, shift.vert).length)),\
+		.row =	(win->matrix.origin.row + row)			\
+	};								\
+	memset(&LayerAt(win->layer, attr, cell.col, cell.row),		\
+		RSC(UI).ATTR()[UI_WIN_MENU_ERASE_CELL].value,		\
+		TCellAt(win, shift.horz, shift.vert).length);		\
+	memset(&LayerAt(win->layer, code, cell.col, cell.row),		\
+		RSC(UI).ATTR()[UI_WIN_MENU_ERASE_CELL].value,		\
+		TCellAt(win, shift.horz, shift.vert).length);		\
+})
+
+extern void ForEachCellPrint_Drop(Window *win, void *plist) ;
+
+extern int Enter_StickyCell(SCANKEY *scan, Window *win) ;
+
+extern int MotionEnter_Cell(SCANKEY *scan, Window *win) ;
+
+extern void MotionEnd_Cell(Window *win) ;
+
+extern void MotionLeft_Menu(Window *win) ;
+
+extern void MotionRight_Menu(Window *win) ;
+
+extern void MotionUp_Menu(Window *win) ;
+
+extern void MotionDown_Menu(Window *win) ;
+
+extern void MotionHome_Menu(Window *win) ;
+
+extern void MotionEnd_Menu(Window *win) ;
+
+typedef union {
+	unsigned long long	qword;
+	struct {
+		unsigned int	lo, hi;
+	} dword;
+	struct {
+		unsigned short	lo[2],
+				hi[2];
+	} word;
+} DATA;
+
+typedef struct _Card {
+	struct _Card	*next;
+
+	Coordinate	origin;
+	struct {
+		void	(*Layout)(Layer *layer, struct _Card *card);
+		void	(*Draw)(Layer *layer, struct _Card *card);
+	} hook;
+	DATA		data;
+} Card;
+
+typedef struct {
+	Card	*head,
+		*tail;
+} CardList;
+
+typedef void (*CARDFUNC)(Layer*, Card*);
+
+extern Card *CreateCard(void) ;
+
+extern void AppendCard(Card *card, CardList *list) ;
+
+extern void DestroyAllCards(CardList *list) ;
+
+extern void HookCardFunc(CARDFUNC *with, CARDFUNC what) ;
+
+#define StoreCard(card, with, what)					\
+(									\
+    __builtin_choose_expr(__builtin_types_compatible_p( 		\
+	__typeof__(card->hook with), __typeof__(CARDFUNC)),HookCardFunc,\
+    (void)0)								\
+	(&(card->hook with), what)					\
+)
+
+extern void FreeAll(char *buffer) ;
+
+__typeof__ (errno) AllocAll(char **buffer) ;
+
+extern unsigned int WriteConsole(SCREEN_SIZE drawSize) ;
+
+extern void _TERMINAL_IN(void) ;
+extern void _TERMINAL_OUT(void) ;
+#define TERMINAL(IO)	_TERMINAL_##IO()
+
+extern void _LOCALE_IN(void) ;
+extern void _LOCALE_OUT(void) ;
+#define LOCALE(IO)	_LOCALE_##IO()
+
+extern void LocaleTo(int category) ;
+
+enum LOCALES {
+	LOC_EN,
+	LOC_FR,
+	LOC_CNT
+};
+
+extern enum LOCALES	AppLoc;
+extern  locale_t	SysLoc;
+
+#define SYS_LOCALE()		(SysLoc)
+#define GET_LOCALE()		(AppLoc)
+#define SET_LOCALE(_apploc)						\
+({									\
+	AppLoc = _apploc;						\
+	LocaleTo(LC_ALL);						\
+})
+
+enum THEMES {
+	THM_DFLT,
+	THM_USR1,
+	THM_USR2,
+	THM_CNT
+};
+
+extern enum THEMES	AppThm;
+
+#define GET_THEME()		(AppThm)
+#define SET_THEME(_app_thm)						\
+({									\
+	AppThm = _app_thm;						\
+})
+
+enum DUMP_METHOD {
+	DUMP_TO_JSON,
+	DUMP_TO_ANSI
+};
+
+extern void StopDump(void) ;
+extern __typeof__ (errno) StartDump(	char *dumpFormat, int tickReset,
+					enum DUMP_METHOD method ) ;
+extern void AbortDump(void) ;
+extern unsigned char DumpStatus(void) ;
+void ANSI_Header(void) ;
+void JSON_Header(void) ;
+void ANSI_Page(char *inStr, int outSize) ;
+void JSON_Page(char *inStr, int outSize) ;
+void ANSI_Break(void) ;
+void JSON_Break(void) ;
+
+extern __typeof__ (errno) SaveGeometries(char*) ;
+extern __typeof__ (errno) LoadGeometries(char*) ;
+
+#if defined(UBENCH) && UBENCH == 1
+  #define UI_Draw_uBenchmark(layer)					\
+  ({									\
+	char str[32];							\
+	int len = snprintf(str, 20+1, "%llu", UBENCH_METRIC(0));	\
+    if (len > 0)							\
+	LayerFillAt(layer, 0, 2, len, str, RSC(UI).ATTR()[UI_LAYOUT_UBENCH]); \
+  })
+#else
+  #define UI_Draw_uBenchmark(layer) {}
+#endif /* UBENCH */

riscv64/corefreq.h

@@ -0,0 +1,581 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#define OF( _ptr_ , ...)	_ptr_ __VA_ARGS__
+#define RO( _ptr_ , ...)	OF( _ptr_##_RO , __VA_ARGS__ )
+#define RW( _ptr_ , ...)	OF( _ptr_##_RW , __VA_ARGS__ )
+
+#define SHM_FILENAME_RO "corefreq-ro-shm"
+#define SHM_FILENAME_RW "corefreq-rw-shm"
+
+#define SIG_RING_MS	(500 * 1000000LU)
+#define CHILD_PS_MS	(500 * 1000000LU)
+#define CHILD_TH_MS	(500 * 1000000LU)
+
+enum CHIPSET {
+	IC_CHIPSET,
+	CHIPSETS
+};
+
+/* Circular buffer							*/
+#define RING_SIZE	16
+
+typedef struct
+{
+	Bit64				Toggle __attribute__ ((aligned (8)));
+
+	Bit64				OffLine __attribute__ ((aligned (8)));
+
+	COF_ST				Boost[BOOST(SIZE)];
+
+	struct
+	{
+		unsigned int		Revision;
+
+		struct {
+		unsigned short int	CfgLock :  1-0,
+					IORedir :  2-1,
+					SCTLRX	:  3-2,
+					Unused	: 16-3;
+		};
+		unsigned short int	CStateLimit;
+		unsigned short int	CStateBaseAddr; /* Any I/O BAR	*/
+	} Query;
+
+	struct {
+		struct {
+		unsigned int	PN	: 12-0,
+				BSP	: 32-12;
+		};
+		signed int		MPID,
+					CoreID,
+					ThreadID,
+					PackageID;
+		struct CLUSTER_ST	Cluster;
+		struct {
+		unsigned int		Set,
+					Size;
+		unsigned short		LineSz,
+					Way;
+		    struct {
+		    unsigned short	WriteBack: 1-0,
+					Inclusive: 2-1,
+					_pad16	: 16-2;
+		    } Feature;
+		} Cache[CACHE_MAX_LEVEL];
+	} Topology;
+
+	struct {
+		unsigned int		Limit[SENSOR_LIMITS_DIM];
+		struct {
+			unsigned int	ClockMod : 16-0,
+					Extended : 32-16;
+			} DutyCycle;
+		unsigned int		PowerPolicy;
+		struct HWP_STRUCT {
+			struct {
+			unsigned int	Highest,
+					Guaranteed,
+					Most_Efficient,
+					Lowest;
+			} Capabilities;
+			struct {
+			unsigned int	Minimum_Perf,
+					Maximum_Perf,
+					Desired_Perf,
+					Energy_Pref;
+			} Request;
+		} HWP;
+	} PowerThermal;
+
+	THERMAL_POINT			ThermalPoint;
+
+	struct {
+		struct {
+			double		Limit[SENSOR_LIMITS_DIM];
+		} Voltage;
+		struct {
+			double		Limit[SENSOR_LIMITS_DIM];
+		} Energy;
+		struct {
+			double		Limit[SENSOR_LIMITS_DIM];
+		} Power;
+	} Sensors;
+
+	struct FLIP_FLOP {
+
+		struct
+		{
+		unsigned long long
+					INST;
+			struct {
+		unsigned long long
+				UCC,
+				URC;
+			}		C0;
+		unsigned long long
+					C3,
+					C6,
+					C7,
+					TSC,
+					C1;
+			struct {
+		unsigned long long	ACCU;
+			} Power;
+		} Delta __attribute__ ((aligned (8)));
+
+		CLOCK			Clock;
+
+		struct {
+			double		IPS,
+					IPC,
+					CPI,
+					Turbo,
+					C0,
+					C3,
+					C6,
+					C7,
+					C1,
+					Energy,
+					Power;
+		} State;
+
+		struct {
+			double		Ratio,
+					Freq;
+		} Relative;
+
+		struct {
+			double		Freq;
+		    struct {
+			double		Perf;	/* STATUS or BOOST P-State */
+		    } Ratio;
+		} Absolute;
+
+		struct {
+		unsigned int		Sensor,
+					Temp;
+		enum THERM_PWR_EVENTS	Events[eDIM];
+		THERMAL_PARAM		Param;
+		} Thermal;
+
+		struct {
+			int		VID;
+			double		Vcore;
+		} Voltage;
+
+		struct {
+		unsigned int		SMI;
+			struct {
+			unsigned int	LOCAL,
+					UNKNOWN,
+					PCISERR,
+					IOCHECK;
+			} NMI;
+		} Counter;
+	} FlipFlop[2];
+
+	struct {
+		double		Freq[SENSOR_LIMITS_DIM];
+	} Relative;
+	struct {
+		double		Freq[SENSOR_LIMITS_DIM];
+	} Absolute;
+
+	struct {
+		Bit64			FLAGS	__attribute__ ((aligned (8)));
+		Bit64			HCR	__attribute__ ((aligned (8)));
+		Bit64			SCTLR	__attribute__ ((aligned (8)));
+		Bit64			SCTLR2	__attribute__ ((aligned (8)));
+		Bit64			EL	__attribute__ ((aligned (8)));
+		Bit64			FPSR	__attribute__ ((aligned (8)));
+		Bit64			FPCR	__attribute__ ((aligned (8)));
+		Bit64			SVCR	__attribute__ ((aligned (8)));
+		Bit64			CPACR	__attribute__ ((aligned (8)));
+	} SystemRegister;
+
+	struct SLICE_STRUCT {
+		unsigned long long	Exclusive __attribute__ ((aligned (8)));
+
+		struct
+		{
+		unsigned long long	TSC,
+					INST;
+		} Delta;
+
+		struct {
+		unsigned long long	TSC,
+					INST;
+		} Counter[3];
+
+		unsigned long long	Error;
+
+	    #ifdef __GLIBC__
+		struct {
+		     struct random_data data;
+			char		state[128];
+			int		value[2];
+		} Random;
+	    #else
+		struct {
+			char		state[128];
+			int		value[2];
+		} Random;
+	    #endif /* __GLIBC__ */
+
+		struct {
+		unsigned long long	inside,
+					trials;
+		} Monte_Carlo;
+	} Slice __attribute__ ((aligned (8)));
+} CPU_STRUCT;
+
+typedef struct
+{
+	Bit64			Toggle __attribute__ ((aligned (8)));
+
+	FEATURES		Features;
+
+	struct {
+		unsigned long long
+				_Unused1_	: 13-0,
+				VM		: 14-13,
+				IOMMU		: 15-14,
+				_Unused2_	: 20-15,
+				IOMMU_Ver_Major : 24-20,
+				IOMMU_Ver_Minor : 28-24,
+				_Unused3_	: 64-28;
+	} Technology;
+
+	struct {
+		unsigned long long
+				CLRBHB		:  2-0,
+				CSV2		:  6-2,
+				CSV3		:  8-6,
+				SSBS		: 10-8,
+				_UnusedMechBits : 64-10;
+	} Mechanisms;
+
+	enum THERMAL_FORMULAS	thermalFormula;
+	enum VOLTAGE_FORMULAS	voltageFormula;
+	enum POWER_FORMULAS	powerFormula;
+
+	struct {
+		unsigned int		Count,
+					OnLine;
+	} CPU;
+
+	SERVICE_PROC			Service;
+
+	union {
+		unsigned int		PM_version;
+		struct PMU_ST {
+			unsigned short	v, p;
+		} PM_ext;
+	};
+	struct {
+		unsigned int		Rel,
+					Abs;
+	} Top;
+
+	struct PKG_FLIP_FLOP {
+	    struct {
+		unsigned long long	PCLK;
+	      struct {
+		unsigned long long	PC02,
+					PC03,
+					PC04,
+					PC06,
+					PC07,
+					PC08,
+					PC09,
+					PC10;
+	      };
+		unsigned long long	MC6,
+					ACCU[PWR_DOMAIN(SIZE)];
+	    } Delta;
+
+	    struct {
+		unsigned long long	FC0;
+	    } Uncore;
+
+	    struct {
+		unsigned int		Sensor,
+					Temp;
+		enum THERM_PWR_EVENTS	Events[eDIM];
+	    } Thermal;
+
+	    struct {
+		struct {
+			int		CPU, SOC;
+		} VID;
+			double		CPU, SOC;
+	    } Voltage;
+	} FlipFlop[2] __attribute__ ((aligned (8)));
+
+	struct {
+		double			PC02,
+					PC03,
+					PC04,
+					PC06,
+					PC07,
+					PC08,
+					PC09,
+					PC10,
+					MC6;
+		struct {
+			double		Limit[SENSOR_LIMITS_DIM];
+		} Voltage;
+
+		struct {
+			double		Current,
+					Limit[SENSOR_LIMITS_DIM];
+		} Energy[PWR_DOMAIN(SIZE)];
+
+		struct {
+			double		Current,
+					Limit[SENSOR_LIMITS_DIM];
+		} Power[PWR_DOMAIN(SIZE)];
+	} State;
+
+	struct {
+		double			Turbo,
+					C0,
+					C3,
+					C6,
+					C7,
+					C1,
+					MC6;
+	} Avg;
+
+	struct {
+		struct {
+			double		Watts,
+					Joules,
+					Times;
+		} Unit;
+		struct {
+			double		TAU[PWR_LIMIT_SIZE];
+			unsigned short	PWL[PWR_LIMIT_SIZE];
+		  struct {
+			unsigned char	Enable	:  1-0,
+					Clamping:  2-1,
+					Unlock	:  3-2,
+					_Unused :  8-3;
+		    union {
+			unsigned char	TW;
+		      struct {
+			unsigned char	TW_Y	:  5-0,
+					TW_Z	:  7-5,
+					MaskBit :  8-7;
+		      };
+		    };
+		  } Feature[PWR_LIMIT_SIZE];
+		} Domain[PWR_DOMAIN(SIZE)];
+		unsigned short		TDP, Min, Max;
+		unsigned short		PPT, EDC, TDC;
+		struct {
+			unsigned short	TDC	:  1-0,
+					_Unused : 16-1;
+		} Feature;
+	} Power;
+
+	THERMAL_POINT			ThermalPoint;
+
+	signed int			ArchID;
+	enum HYPERVISOR 		HypervisorID;
+	char				Architecture[CODENAME_LEN],
+					Brand[BRAND_SIZE];
+} PROC_STRUCT;
+
+typedef struct
+{
+	FOOTPRINT		FootPrint;
+
+	BitCC			roomSched __attribute__ ((aligned (16)));
+
+	enum THERM_PWR_EVENTS	ProcessorEvents[eDIM];
+
+	struct {	/*	NMI bits: 0 is Unregistered; 1 is Registered */
+		Bit64		NMI	__attribute__ ((aligned (8)));
+		signed int	AutoClock, /* 10: Auto, 01: Init, 00: Specs */
+				Experimental,/* 0: Disable, 1: Enable	*/
+				HotPlug, /* < 0: Disable, Other: Enable */
+				PCI;	/*  < 0: Disable, other: Enable */
+		KERNEL_DRIVER	Driver; /*0:Disable, 1:Enable, 2:Full-control*/
+	} Registration;
+
+	struct {
+		Bit64		Operation	__attribute__ ((aligned (8)));
+
+		OS_DRIVER	OS;
+
+		unsigned int	tickReset,
+				tickStep;
+
+		pid_t		trackTask;
+		enum SORTBYFIELD sortByField;
+		int		reverseOrder,
+				taskCount;
+		TASK_MCB	taskList[TASK_LIMIT];
+
+		MEM_MCB 	memInfo;
+
+		struct {
+		unsigned short	version,
+				major,
+				minor;
+		} kernel;
+
+		unsigned short	procCount;
+
+		char		sysname[MAX_UTS_LEN],
+				release[MAX_UTS_LEN],
+				version[MAX_UTS_LEN],
+				machine[MAX_UTS_LEN];
+	} SysGate;
+
+	struct {
+		unsigned char	index[8];
+		char		array[MAX_UTS_LEN];
+	} CS;
+
+	struct {
+		unsigned int	Interval;
+		struct timespec pollingWait,
+				ringWaiting,
+				childWaiting,
+				sliceWaiting;
+	} Sleep;
+
+	time_t				StartedAt;
+
+	char				ShmName[TASK_COMM_LEN];
+	struct {
+		pid_t			Svr,
+					Cli,
+					GUI;
+	} App;
+
+	struct {
+		COF_ST			Boost[UNCORE_BOOST(SIZE)];
+	    struct
+	    {
+		unsigned long long	Speed;
+		unsigned int		Rate;
+	    } Bus;
+
+	    struct {
+		struct {
+			RAM_TIMING	Timing;
+			RAM_GEOMETRY	DIMM[MC_MAX_DIMM];
+		} Channel[MC_MAX_CHA];
+		unsigned short		SlotCount, ChannelCount;
+	    } MC[MC_MAX_CTRL];
+
+	unsigned long long		CtrlSpeed;
+	unsigned short			CtrlCount,
+					ChipID;
+
+	    struct {
+		unsigned short	/* 00:MHz , 01:MT/s , 10:MB/s , 11:VOID */
+					Bus_Rate:  2-0,
+					BusSpeed:  4-2,
+					DDR_Rate:  6-4,
+					DDRSpeed:  8-6,
+					DDR_Std : 12-8,
+					DDR_Ver : 16-12;
+	    } Unit;
+
+	    struct {
+		enum CHIPSET		ArchID;
+		char			CodeName[CODENAME_LEN];
+	    } Chipset;
+	} Uncore;
+
+	SMBIOS_ST		SMB;
+
+	PROC_STRUCT		Proc;
+	CPU_STRUCT		Cpu[];
+} SHM_STRUCT_RO;
+
+typedef struct {
+	struct {
+		Bit64		Sync __attribute__ ((aligned (8)));
+	} Proc;
+
+	struct {
+		RING_CTRL	buffer[RING_SIZE] __attribute__((aligned(16)));
+		unsigned int	head, tail;
+	} Ring[2]; /* [0] Parent ; [1] Child				*/
+
+	struct {
+		RING_CTRL	buffer[RING_SIZE] __attribute__((aligned(16)));
+		unsigned int	head, tail;
+	} Error;
+} SHM_STRUCT_RW;
+
+/* Error Reasons management.						*/
+typedef struct {
+	__typeof__ (errno)	no: 32;
+	__typeof__ (__LINE__)	ln: 26;
+	enum REASON_CLASS	rc: 6;
+} REASON_CODE;
+
+#define REASON_SET_2xARG(_reason, _rc, _no)				\
+{									\
+	_reason.no = _no;						\
+	_reason.ln = __LINE__;						\
+	_reason.rc = _rc;						\
+}
+
+#define REASON_SET_1xARG(_reason, _rc)					\
+{									\
+	_reason.no = errno;						\
+	_reason.ln = __LINE__;						\
+	_reason.rc = _rc;						\
+}
+
+#define REASON_SET_0xARG(_reason)					\
+{									\
+	_reason.no = errno;						\
+	_reason.ln = __LINE__;						\
+	_reason.rc = RC_SYS_CALL;					\
+}
+
+#define REASON_DISPATCH(_1,_2,_3,REASON_CURSOR, ... ) REASON_CURSOR
+
+#define REASON_SET( ... )						\
+	REASON_DISPATCH( __VA_ARGS__ ,	REASON_SET_2xARG,		\
+					REASON_SET_1xARG,		\
+					REASON_SET_0xARG)( __VA_ARGS__ )
+
+#define REASON_INIT(_reason)		\
+	REASON_CODE _reason = {.no = 0, .ln = 0, .rc = RC_SUCCESS}
+
+#define IS_REASON_SUCCESSFUL(_reason) (_reason.rc == RC_SUCCESS)
+
+#if defined(UBENCH) && UBENCH == 1
+    #define Print_uBenchmark(quiet)					\
+    ({									\
+	if (quiet)							\
+		printf("%llu\t%llu\n",UBENCH_METRIC(0),UBENCH_METRIC(1));\
+    })
+#else
+	#define Print_uBenchmark(quiet) {}
+#endif /* UBENCH */
+
+#define ELAPSED(ref)							\
+({									\
+	time_t now;							\
+	time(&now);							\
+	now - ref;							\
+})
+
+#define COF2FLOAT(_COF) 						\
+(									\
+	(double)_COF.Q + (double)_COF.R / UNIT_KHz(PRECISION)		\
+)

riscv64/corefreqm.c

@@ -0,0 +1,354 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+#define _GNU_SOURCE
+#include <sys/ioctl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <math.h>
+
+#include "bitasm.h"
+#include "coretypes.h"
+#include "corefreq.h"
+#include "corefreqm.h"
+
+#define DeltaTSC(pSlice)						\
+({									\
+	unsigned long long overhead = pSlice->Counter[1].TSC		\
+				    - pSlice->Counter[0].TSC;		\
+	pSlice->Delta.TSC = pSlice->Counter[2].TSC			\
+			  - pSlice->Counter[1].TSC;			\
+	if (overhead <= pSlice->Delta.TSC)				\
+		pSlice->Delta.TSC -= overhead;				\
+})
+
+#define DeltaINST(pSlice)						\
+({									\
+	unsigned long long overhead = pSlice->Counter[1].INST		\
+				    - pSlice->Counter[0].INST;		\
+	/*	Test and compute if counter has overflowed	*/	\
+	if (pSlice->Counter[2].INST >= pSlice->Counter[1].INST) 	\
+		pSlice->Delta.INST  =  pSlice->Counter[2].INST		\
+				    -  pSlice->Counter[1].INST; 	\
+	else {								\
+		pSlice->Delta.INST  = (INST_COUNTER_OVERFLOW + 0x1)	\
+				    - pSlice->Counter[1].INST;		\
+		pSlice->Delta.INST += pSlice->Counter[2].INST;		\
+	}								\
+	if (overhead <= pSlice->Delta.INST)				\
+		pSlice->Delta.INST -= overhead; 			\
+})
+
+void CallWith_RDTSC_RDPMC(	RO(SHM_STRUCT) *RO(Shm),
+				RW(SHM_STRUCT) *RW(Shm),
+				unsigned int cpu,
+				SLICE_FUNC SliceFunc,
+				unsigned long arg )
+{
+	struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice;
+
+	RDTSC_PMCx1(	pSlice->Counter[0].TSC,
+			/*TODO:pmevcntr3_el0*/mcycle,
+			pSlice->Counter[0].INST );
+
+	pSlice->Counter[0].INST &= INST_COUNTER_OVERFLOW;
+
+	RDTSC_PMCx1(	pSlice->Counter[1].TSC,
+			/*TODO:pmevcntr3_el0*/mcycle,
+			pSlice->Counter[1].INST );
+
+	pSlice->Counter[1].INST &= INST_COUNTER_OVERFLOW;
+
+	SliceFunc(RO(Shm), RW(Shm), cpu, arg);
+
+	RDTSC_PMCx1(	pSlice->Counter[2].TSC,
+			/*TODO:pmevcntr3_el0*/mcycle,
+			pSlice->Counter[2].INST );
+
+	pSlice->Counter[2].INST &= INST_COUNTER_OVERFLOW;
+
+	if (BITVAL(RW(Shm)->Proc.Sync, BURN)) {
+		DeltaTSC(pSlice);
+		DeltaINST(pSlice);
+	}
+}
+
+void CallWith_RDTSC_No_RDPMC(	RO(SHM_STRUCT) *RO(Shm),
+				RW(SHM_STRUCT) *RW(Shm),
+				unsigned int cpu,
+				SLICE_FUNC SliceFunc,
+				unsigned long arg )
+{
+	struct SLICE_STRUCT *pSlice = &RO(Shm)->Cpu[cpu].Slice;
+
+	RDTSC64(pSlice->Counter[0].TSC);
+
+	RDTSC64(pSlice->Counter[1].TSC);
+
+	SliceFunc(RO(Shm), RW(Shm), cpu, arg);
+
+	RDTSC64(pSlice->Counter[2].TSC);
+
+	if (BITVAL(RW(Shm)->Proc.Sync, BURN)) {
+		DeltaTSC(pSlice);
+		pSlice->Delta.INST = 0;
+	}
+}
+
+void Slice_NOP( RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+		unsigned int cpu, unsigned long arg )
+{
+	UNUSED(RO(Shm));
+	UNUSED(RW(Shm));
+	UNUSED(cpu);
+	UNUSED(arg);
+
+	__asm__ volatile
+	(
+		"nop"
+		:
+		:
+		:
+	);
+}
+
+void Slice_Atomic(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+		unsigned int cpu, unsigned long arg)
+{
+	UNUSED(RW(Shm));
+	register unsigned long loop = arg;
+    do {
+/*	__asm__ volatile
+	(
+		"ldr	x10,	%[_err]"		"\n\t"
+		"1:"					"\n\t"
+		"ldxr	x11,	[%[addr]]"		"\n\t"
+		"mrs	x11,	cntvct_el0"		"\n\t"
+		"stxr	w9,	x11, [%[addr]]" 	"\n\t"
+		"cbz	w9,	2f"			"\n\t"
+		"add	x10,	x10, #1"		"\n\t"
+		"b	1b"				"\n\t"
+		"2:"					"\n\t"
+		"str	x10,	%[_err]"
+		: [_err] "=m"	(RO(Shm)->Cpu[cpu].Slice.Error)
+		: [addr] "r"	(&RO(Shm)->Cpu[cpu].Slice.Exclusive)
+		: "cc", "memory", "%w9", "%x10", "%x11"
+	);*/
+    } while (loop-- != 0) ;
+}
+
+unsigned int CRC32vC(unsigned char *data, unsigned int len)
+{
+	unsigned int rem = 0, oloop = len, iloop;
+
+	while (oloop--) {
+		rem ^= *data++;
+		for (iloop = 0; iloop < 8; iloop++)
+			rem = (rem >> 1) ^ ((rem & 1) ? 0x436f7265 : 0);
+	}
+	return(rem);
+}
+
+void Slice_CRC32(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+		unsigned int cpu, unsigned long arg)
+{
+	unsigned char *data = (unsigned char *) CRC32_SRC;
+	unsigned int len = 16;
+	UNUSED(RW(Shm));
+	UNUSED(arg);
+
+	if (CRC32vC(data, len) != CRC32_EXP)
+		RO(Shm)->Cpu[cpu].Slice.Error++ ;
+}
+
+/*
+	Source: 1996 Software graduate thesis
+	Conic: a.X² + b.Y² + c.Z² = k
+	Variations:
+	    1 - l'ellipsoïde
+	    2 - l'hyperboloïde à une nappe
+	    3 - l'hyperboloïde à deux nappes
+	    4 - le cylindre elliptique
+	    5 - le cylindre hyperbolique
+	    6 - deux plans parallèles
+*/
+void Slice_Conic(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+		unsigned int cpu, unsigned long v)
+{
+	const double interval = (4.0 * 1024.0) - (double) cpu;
+	const struct {
+		double a, b, c, k;
+	} p[CONIC_VARIATIONS] = {
+		{.a=+1.0 , .b=+1.0, .c=-1.0 , .k=    +0.0},
+		{.a=-3.0 , .b=+3.0, .c=-3.0 , .k=-17000.0},
+		{.a=+0.01, .b=+0.7, .c=+0.2 , .k= +3000.0},
+		{.a=+2.0 , .b=+0.0, .c=+1.0 , .k= +5000.0},
+		{.a=-0.5 , .b=+0.0, .c=+0.75, .k=  +500.0},
+		{.a=+0.0 , .b=+0.0, .c=+1.0 , .k= +3000.0}
+	};
+	double X, Y, Z, Q, k;
+
+	const double step = (double) RO(Shm)->Proc.CPU.Count;
+
+	UNUSED(RW(Shm));
+
+	for (Y = -interval; Y <= interval; Y += step)
+	    for (X = -interval; X <= interval; X += step) {
+		Q=(p[v].k - p[v].a * pow(X,2.0) - p[v].b * pow(Y,2.0)) / p[v].c;
+		Z = sqrt(Q);
+
+		k = p[v].a*pow(X,2.0) + p[v].b*pow(Y,2.0) + p[v].c*pow(Z,2.0);
+
+		if (fabs(k - p[v].k) > CONIC_ERROR)
+			RO(Shm)->Cpu[cpu].Slice.Error++ ;
+	    }
+}
+
+void Slice_Turbo(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+		unsigned int cpu, unsigned long arg)
+{
+	UNUSED(arg);
+
+	Slice_Atomic(RO(Shm), RW(Shm), cpu, TURBO_LOOP);
+}
+
+void Slice_Monte_Carlo(RO(SHM_STRUCT) *RO(Shm), RW(SHM_STRUCT) *RW(Shm),
+			unsigned int cpu, unsigned long arg)
+{
+    if (RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials < PI_TRIALS)
+    {
+	double X, Y, Z;
+	UNUSED(arg);
+      #ifdef __GLIBC__
+	if (!random_r(	&RO(Shm)->Cpu[cpu].Slice.Random.data,
+			&RO(Shm)->Cpu[cpu].Slice.Random.value[0] )
+	 && !random_r(	&RO(Shm)->Cpu[cpu].Slice.Random.data,
+			&RO(Shm)->Cpu[cpu].Slice.Random.value[1] ))
+      #else
+	RO(Shm)->Cpu[cpu].Slice.Random.value[0] = (int) random();
+	RO(Shm)->Cpu[cpu].Slice.Random.value[1] = (int) random();
+      #endif /* __GLIBC__ */
+	{
+		X = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[0] / RAND_MAX;
+		Y = (double) RO(Shm)->Cpu[cpu].Slice.Random.value[1] / RAND_MAX;
+
+		Z = pow(X, 2.0) + pow(Y, 2.0);
+
+		if (Z <= 1.0) {
+			RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside++;
+		}
+	}
+	RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials++ ;
+    } else {
+	const double fi = (double) RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside,
+		ft = RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials ?
+		(double) RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials : 1.0;
+
+	const double PI = (fi / ft) * 4.0;
+
+	RO(Shm)->Cpu[cpu].Slice.Error += (fabs(PI - PI_CONST) > PI_ERROR) ?
+		+1LLU : RO(Shm)->Cpu[cpu].Slice.Error > 0LLU ? -1LLU : 0LLU;
+
+	RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.inside = 0LLU;
+	RO(Shm)->Cpu[cpu].Slice.Monte_Carlo.trials = 0LLU;
+    }
+}
+
+RING_SLICE order_list[] = {
+    {
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_ATOMIC, .sub = 0x0U,
+	.dl = {.lo = 1	, .hi = COREFREQ_TOGGLE_ON},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Atomic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd=COREFREQ_ORDER_CRC32, .sub = 0x0U,
+	.dl = {.lo = 1	, .hi = COREFREQ_TOGGLE_ON},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_CRC32, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_ELLIPSOID,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLOID_ONE_SHEET,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLOID_TWO_SHEETS,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_ELLIPTICAL_CYLINDER,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_HYPERBOLIC_CYLINDER,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_CONIC, .sub = CONIC_TWO_PARALLEL_PLANES,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Conic, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_TURBO, .sub = RAND_SMT,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Turbo, .pattern = RAND_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_TURBO, .sub = RR_SMT,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Turbo, .pattern = RR_SMT
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_TURBO, .sub = USR_CPU,
+	.dl = {.lo = 1	, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Turbo, .pattern = USR_CPU
+    },{
+	.ctrl = {
+	.cmd = COREFREQ_ORDER_MONTE_CARLO, .sub = 0x0U,
+	.dl = {.lo = 0x0, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = Slice_Monte_Carlo, .pattern = ALL_SMT
+    },{
+	.ctrl = {
+	.cmd = 0x0U, .sub = 0x0U,
+	.dl = {.lo = 0x0, .hi = 0x0},
+	.dh = {.lo = 0x0, .hi = 0x0}
+	},
+	.func = NULL
+    }
+};

riscv64/corefreqm.h

@@ -0,0 +1,79 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+
+typedef void (*SLICE_FUNC) (	RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+				unsigned int, unsigned long );
+
+void Slice_NOP( RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+		unsigned int, unsigned long );
+
+void Slice_Atomic(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+		unsigned int, unsigned long);
+
+void Slice_CRC32(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+		unsigned int, unsigned long);
+
+void Slice_Conic(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+		unsigned int, unsigned long);
+
+void Slice_Turbo(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+		unsigned int, unsigned long);
+
+void Slice_Monte_Carlo(RO(SHM_STRUCT)*, RW(SHM_STRUCT)*,
+			unsigned int, unsigned long);
+
+typedef struct {
+		RING_CTRL	ctrl;
+		SLICE_FUNC	func;
+	enum	PATTERN 	pattern;
+} RING_SLICE;
+
+extern RING_SLICE order_list[];
+
+typedef void (*CALL_FUNC)(	RO(SHM_STRUCT)*,
+				RW(SHM_STRUCT)*,
+				unsigned int,
+				SLICE_FUNC,
+				unsigned long );
+
+void CallWith_RDTSC_RDPMC(	RO(SHM_STRUCT)*,
+				RW(SHM_STRUCT)*,
+				unsigned int,
+				SLICE_FUNC,
+				unsigned long );
+
+void CallWith_RDTSC_No_RDPMC(	RO(SHM_STRUCT)*,
+				RW(SHM_STRUCT)*,
+				unsigned int,
+				SLICE_FUNC,
+				unsigned long );
+
+#define RESET_Slice(Slice)						\
+({									\
+	Slice.Counter[0].TSC = 0;					\
+	Slice.Counter[1].TSC = 0;					\
+	Slice.Counter[2].TSC = 0;					\
+	Slice.Counter[0].INST= 0;					\
+	Slice.Counter[1].INST= 0;					\
+	Slice.Counter[2].INST= 0;					\
+	Slice.Delta.TSC = 0;						\
+	Slice.Delta.INST= 0;						\
+	Slice.Error = 0;						\
+})
+
+#define SLICE_XCHG	0x436f757274696174LLU
+#define SLICE_ATOM	0x436f726546726571LLU
+
+#define TURBO_LOOP	0x7ffffffUL
+
+#define CRC32_SRC	"CYRIL_INGENIERIE"
+#define CRC32_EXP	0x44f9d7bc
+
+#define CONIC_ERROR	1e-07
+
+#define PI_TRIALS	100000000LLU
+#define PI_ERROR	1.0e-04
+#define PI_CONST	3.141592653589793

riscv64/risc_reg.h

@@ -0,0 +1,908 @@
+/*
+ * CoreFreq
+ * Copyright (C) 2015-2025 CYRIL COURTIAT
+ * Licenses: GPL2
+ */
+/*
+#define CPUPWRCTLR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0010, 0b111)
+#define ID_AA64ISAR2_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b010)
+#define ID_AA64ISAR3_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b011)
+#define ID_AA64ISAR4_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0110, 0b100)
+#define ID_AA64MMFR2_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b010)
+#define ID_AA64MMFR3_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0111, 0b011)
+#define ID_AA64SMFR0_EL1	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b101)
+#define ID_AA64ZFR0_EL1 	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b100)
+#define ID_AA64PFR2_EL1 	sys_reg(0b11, 0b000, 0b0000, 0b0100, 0b010)
+#define SCTLR2_EL1		sys_reg(0b11, 0b000, 0b0001, 0b0000, 0b011)
+#define MRS_SSBS2		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b110)
+#define MRS_PAN 		sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b011)
+#define MRS_UAO 		sys_reg(0b11, 0b000, 0b0100, 0b0010, 0b100)
+#define MRS_DIT 		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b101)
+#define MRS_TCO 		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b111)
+#define MRS_ALLINT		sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b000)
+#define MRS_PM			sys_reg(0b11, 0b000, 0b0100, 0b0011, 0b001)
+#define MRS_SVCR		sys_reg(0b11, 0b011, 0b0100, 0b0010, 0b010)
+#define MRS_FPMR		sys_reg(0b11, 0b011, 0b0100, 0b0100, 0b010)
+#define AMCGCR_EL0		sys_reg(0b11, 0b011, 0b1101, 0b0010, 0b010)
+#define CLUSTERCFR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b000)
+#define CLUSTERIDR_EL1		sys_reg(0b11, 0b000, 0b1111, 0b0011, 0b001)
+*/
+typedef union
+{
+	unsigned long long	value;	/* CPU0:0x412fd050 ; CPU4:0x414fd0b0 */
+	struct
+	{
+		unsigned long long
+		Revision	:  4-0,
+		PartNum 	: 16-4,
+		Architecture	: 20-16, /* 0b1111=by CPUID scheme	*/
+		Variant 	: 24-20,
+		Implementer	: 32-24,
+		RES0		: 64-32;
+	};
+} MIDR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Aff0		:  8-0,  /*	Thread ID		*/
+		Aff1		: 16-8,  /*	Core ID: CPUID[12-8] L1 */
+		Aff2		: 24-16, /*	Cluster ID - Level2	*/
+		MT		: 25-24, /*	Multithreading		*/
+		UNK		: 30-25,
+		U		: 31-30, /*	0=Uniprocessor		*/
+		RES1		: 32-31,
+		Aff3		: 40-32, /*	Cluster ID - Level3	*/
+		RES0		: 64-40;
+	};
+} MPIDR;
+/*
+CPU:MPIDR
+  0:0x81000000
+  1:0x81000100
+  2:0x81000200
+  3:0x81000300
+  4:0x81000400
+  5:0x81000500
+  6:0x81000600
+  7:0x81000700
+*/
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Revision	: 32-0,
+		RES0		: 64-32;
+	};
+} REVIDR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		EnableAll	:  1-0,
+		ResetEvent	:  2-1,
+		ResetCycle	:  3-2,
+		ClockDiv	:  4-3,  /* 1:PMCCNTR counts once / 64 cycles */
+		ExportEvent	:  5-4,
+		DisableCycle	:  6-5,  /* 1:PMCCNTR is disabled	*/
+		EnableLongCycle :  7-6,
+		EnableLongEvent :  8-7,
+		RES0		:  9-8,
+		FZO		: 10-9,  /* 1:Freeze-on-overflow	*/
+		RES1		: 11-10,
+		NumEvtCtrs	: 16-11,
+		IDcode		: 24-16,
+		Implementer	: 32-24,
+		Freeze_On_SPE	: 33-32,
+		RES2		: 64-33;
+	};
+} PMCR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		SEL		:  5-0,
+		RES0		: 64-5;
+	};
+} PMSELR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		CFILTR_EVTYPER	: 64-0;
+	};
+} PMXEVTYPER;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		RES0		: 20-0,
+		RLH		: 21-20,
+		RLU		: 22-21,
+		RLK		: 23-22,
+		T		: 24-23,
+		SH		: 25-24,
+		RES1		: 26-25,
+		M		: 27-26,
+		NSH		: 28-27,
+		NSU		: 29-28,
+		NSK		: 30-29,
+		U		: 31-30,
+		P		: 32-31,
+		RES2		: 56-32,
+		VS		: 58-56,
+		RES3		: 64-58;
+	};
+} PMCCFILTR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		EvtCount	: 16-0,
+		RES0		: 20-16,
+		RLH		: 21-20,
+		RLU		: 22-21,
+		RLK		: 23-22,
+		T		: 24-23,
+		SH		: 25-24,
+		MT		: 26-25,
+		M		: 27-26,
+		NSH		: 28-27,
+		NSU		: 29-28,
+		NSK		: 30-29,
+		U		: 31-30,
+		P		: 32-31,
+		TH		: 44-32,
+		RES1		: 54-44,
+		TLC		: 56-54,
+		VS		: 58-56,
+		SYNC		: 59-58,
+		RES2		: 60-59,
+		TE		: 61-60,
+		TC		: 64-61;
+	};
+} PMEVTYPER;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Pm		: 31-0,
+		C		: 32-31,
+		F0		: 33-32,
+		RES0		: 64-33;
+	};
+} PMCNTENSET;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Pm		: 31-0,
+		C		: 32-31,
+		F0		: 33-32,
+		RES0		: 64-33;
+	};
+} PMCNTENCLR;
+
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		EN		:  1-0,
+		SW		:  2-1,
+		CR		:  3-2,
+		ER		:  4-3,
+		UEN		:  5-4,
+		IR		:  6-5,
+		TID		:  7-6,
+		RES0		: 64-7;
+	};
+} PMUSERENR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		ClockFreq_Hz	: 32-0,
+		RES0		: 64-32;
+	};
+} CNTFRQ;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		PhysicalCount	: 64-0;
+	};
+} CNTPCT;
+
+typedef union
+{
+	unsigned long long	value;	/* SMT=0x0000000000000000	*/
+	struct
+	{
+		unsigned long long
+		CORE_PWRDN_EN	:  1-0,
+		RES0		:  4-1,
+		WFI_RET_CTRL	:  7-4,
+		WFE_RET_CTRL	: 10-7,
+		RES1		: 32-10,
+		RES2		: 64-32;
+	};
+} CPUPWRCTLR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		InD		:  1-0,
+		Level		:  4-1,
+		RES0		: 32-4,
+		RES1		: 64-32;
+	};
+} CSSELR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Ctype1		:  3-0,
+		Ctype2		:  6-3,
+		Ctype3		:  9-6,
+		RES0		: 21-9,
+		LoUIS		: 24-21,
+		LoC		: 27-24,
+		LoUU		: 30-27,
+		ICB		: 33-30,
+		RES1		: 64-33;
+	};
+} CLIDR;
+
+typedef union
+{	/*	CPU0:0x00000000003033ff ; CPU4:0x0000000000300000	*/
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		RES0		: 16-0,
+		ZEN		: 18-16,
+		RES1		: 20-18,
+		FPEN		: 22-20,
+		RES2		: 24-22,
+		SMEN		: 26-24,
+		RES3		: 28-26,
+		TTA		: 29-28,
+		E0POE		: 30-29,
+		RES4		: 64-30;
+	};
+} CPACR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		CG0NC		:  8-0,
+		CG1NC		: 16-8,
+		RES0		: 64-16;
+	};
+} AMCGCR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		DebugVer	:  4-0,
+		TraceVer	:  8-4,
+		PMUVer		: 12-8,
+		BRPs		: 16-12,
+		PMSS		: 20-16,
+		WRPs		: 24-20,
+		SEBEP		: 28-24,
+		CTX_CMPs	: 32-28,
+		PMSVer		: 36-32,
+		DoubleLock	: 40-36,
+		TraceFilt	: 44-40,
+		TraceBuffer	: 48-40,
+		MTPMU		: 52-48,
+		BRBE		: 56-52,
+		ExtTrcBuff	: 60-56,
+		HPMN0		: 64-60;
+	};
+} AA64DFR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		SYSPMUID	:  8-0,
+		BRPs		: 16-8,
+		WRPs		: 24-16,
+		CTX_CMPs	: 32-24,
+		SPMU		: 36-32,
+		PMICNTR 	: 40-36,
+		ABLE		: 44-40,
+		ITE		: 48-44,
+		EBEP		: 52-48,
+		DPFZS		: 56-52,
+		ABL_CMPs	: 64-56;
+	};
+} AA64DFR1;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		STEP		:  4-0,
+		BWE		:  8-4,
+		RES0		: 64-8;
+	};
+} AA64DFR2;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		RES0		:  4-0,
+		AES		:  8-4,
+		SHA1		: 12-8,
+		SHA2		: 16-12,
+		CRC32		: 20-16,
+		Atomic		: 24-20,
+		TME		: 28-24,
+		RDM		: 32-28,
+		SHA3		: 36-32,
+		SM3		: 40-36,
+		SM4		: 44-40,
+		DP		: 48-44,
+		FHM		: 52-48,
+		TS		: 56-52,
+		TLB		: 60-56,
+		RNDR		: 64-60;
+	};
+} AA64ISAR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		DPB		:  4-0,
+		APA		:  8-4,
+		API		: 12-8,
+		JSCVT		: 16-12,
+		FCMA		: 20-16,
+		LRCPC		: 24-20,
+		GPA		: 28-24,
+		GPI		: 32-28,
+		FRINTTS 	: 36-32,
+		SB		: 40-36,
+		SPECRES 	: 44-40,
+		BF16		: 48-44,
+		DGH		: 52-48,
+		I8MM		: 56-52,
+		XS		: 60-56,
+		LS64		: 64-60;
+	};
+} AA64ISAR1;
+
+typedef union
+{
+	unsigned long long	value;	/* CPU0:0x00000000 ; CPU4:0x00000000 */
+	struct
+	{
+		unsigned long long
+		WFxT		:  4-0,
+		RPRES		:  8-4,
+		GPA3		: 12-8,
+		APA3		: 16-12,
+		MOPS		: 20-16,
+		BC		: 24-20,
+		PAC_frac	: 28-24,
+		CLRBHB		: 32-28,
+		SYSREG_128	: 36-32,
+		SYSINSTR_128	: 40-36,
+		PRFMSLC 	: 44-40,
+		PCDPHINT	: 48-44,
+		RPRFM		: 52-48,
+		CSSC		: 56-52,
+		LUT		: 60-56,
+		ATS1A		: 64-60;
+	};
+} AA64ISAR2;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		CPA		:  4-0,
+		FAMINMAX	:  8-4,
+		TLBIW		: 12-8,
+		PACM		: 16-12,
+		LSFE		: 20-16,
+		OCCMO		: 24-20,
+		LSUI		: 28-24,
+		FPRCVT		: 32-28,
+		RES0		: 64-32;
+	};
+} AA64ISAR3;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		PARange 	:  4-0,
+		ASID_Bits	:  8-4,
+		BigEnd		: 12-8,
+		SNSMem		: 16-12,
+		BigEnd_EL0	: 20-16,
+		TGran16 	: 24-20,
+		TGran64 	: 28-24,
+		TGran4		: 32-28,
+		TGran16_2	: 36-32,
+		TGran64_2	: 40-36,
+		TGran4_2	: 44-40,
+		ExS		: 48-44,
+		RES0		: 56-48,
+		FGT		: 60-56,
+		ECV		: 64-60;
+	};
+} AA64MMFR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		HAFDBS		:  4-0,
+		VMID_Bits	:  8-4,
+		VH		: 12-8,
+		HPDS		: 16-12,
+		LO		: 20-16,
+		PAN		: 24-20,
+		SpecSEI		: 28-24,
+		XNX		: 32-28,
+		TWED		: 36-32,
+		ETS		: 40-36,
+		HCX		: 44-40,
+		AFP		: 48-44,
+		nTLBPA		: 52-48,
+		TIDCP1		: 56-52,
+		CMOW		: 60-56,
+		ECBHB		: 64-60;
+	};
+} AA64MMFR1;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		CnP		:  4-0,
+		UAO		:  8-4,
+		LSM		: 12-8,
+		IESB		: 16-12,
+		VARange 	: 20-16,
+		CCIDX		: 24-20,
+		NV		: 28-24,
+		ST		: 32-28,
+		AT		: 36-32,
+		IDS		: 40-36,
+		FWB		: 44-40,
+		RES0		: 48-44,
+		TTL		: 52-48,
+		BBM		: 56-52,
+		EVT		: 60-56,
+		E0PD		: 64-60;
+	};
+} AA64MMFR2;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		TCRX		:  4-0,
+		SCTLRX		:  8-4,
+		S1PIE		: 12-8,
+		S2PIE		: 16-12,
+		S1POE		: 20-16,
+		S2POE		: 24-20,
+		AIE		: 28-24,
+		MEC		: 32-28,
+		D128		: 36-32,
+		D128_2		: 40-36,
+		SNERR		: 44-40,
+		ANERR		: 48-44,
+		RES0		: 52-48,
+		SDERR		: 56-52,
+		ADERR		: 60-56,
+		Spec_FPACC	: 64-60;
+	};
+} AA64MMFR3;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		PoPS		:  4-0,
+		EIESB		:  8-4,
+		ASID2		: 12-8,
+		HACDBS		: 16-12,
+		FGWTE3		: 20-16,
+		NV_frac 	: 24-20,
+		E2H0		: 28-24,
+		RMEGDI		: 32-28,
+		RES0		: 36-32,
+		E3DSE		: 40-36,
+		RES1		: 44-40,
+		SRMASK		: 48-44,
+		RES2		: 64-48;
+	};
+} AA64MMFR4;
+
+typedef union
+{				/* CPU0:0x11112222 ; CPU4:0x1100000011111112 */
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		EL0		:  4-0,  /*0b0001=AArch64;0b0010=AArch{32,64}*/
+		EL1		:  8-4,
+		EL2		: 12-8,
+		EL3		: 16-12,
+		FP		: 20-16,
+		AdvSIMD 	: 24-20,
+		GIC		: 28-24,
+		RAS		: 32-28,
+		SVE		: 36-32,
+		SEL2		: 40-36,
+		MPAM		: 44-40,
+		AMU		: 48-44,
+		DIT		: 52-48,
+		RME		: 56-52,
+		CSV2		: 60-56,
+		CSV3		: 64-60;
+	};
+} AA64PFR0;
+/*
+CPU:AA64PFR0
+ 1:0x0000000011112222
+ 0:0x0000000011112222
+ 2:0x0000000011112222
+ 3:0x0000000011112222
+ 4:0x1100000011111112
+ 5:0x1100000011111112
+ 6:0x1100000011111112
+ 7:0x1100000011111112
+*/
+typedef union
+{
+	unsigned long long	value;	/*	Pkg:0x00000010		*/
+	struct
+	{
+		unsigned long long
+		BT		:  4-0,
+		SSBS		:  8-4,
+		MTE		: 12-8,
+		RAS_frac	: 16-12,
+		MPAM_frac	: 20-16,
+		SME		: 28-24,
+		RNDR_trap	: 32-28,
+		CSV2_frac	: 36-32,
+		NMI		: 40-36,
+		MTE_frac	: 44-40,
+		GCS		: 48-44,
+		THE		: 52-48,
+		MTEX		: 56-52,
+		DF2		: 60-56,
+		PFAR		: 64-60;
+	};
+} AA64PFR1;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		MTEPERM 	:  4-0,
+		MTESTOREONLY	:  8-4,
+		MTEFAR		: 12-8,
+		RES0		: 16-12,
+		UINJ		: 20-16,
+		RES1		: 32-20,
+		FPMR		: 36-32,
+		RES2		: 64-36;
+	};
+} AA64PFR2;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		RES0		: 28-0,
+		SF8DP2		: 29-28,
+		SF8DP4		: 30-29,
+		SF8FMA		: 31-30,
+		RES1		: 32-31,
+		F32F32		: 33-32,
+		BI32I32 	: 34-33,
+		B16F32		: 35-34,
+		F16F32		: 36-35,
+		I8I32		: 40-36,
+		F8F32		: 41-40,
+		F8F16		: 42-41,
+		F16F16		: 43-42,
+		B16B16		: 44-43,
+		I16I32		: 48-44,
+		F64F64		: 49-48,
+		RES2		: 52-49,
+		I16I64		: 56-52,
+		SMEver		: 60-56,
+		LUTv2		: 61-60,
+		RES3		: 63-61,
+		FA64		: 64-63;
+	};
+} AA64SMFR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		SVE_Ver 	:  4-0,
+		SVE_AES 	:  8-4,
+		RES0		: 16-8,
+		BitPerm 	: 20-16,
+		SVE_BF16	: 24-20,
+		B16B16		: 28-24,
+		RES1		: 32-28,
+		SVE_SHA3	: 36-32,
+		RES2		: 40-36,
+		SVE_SM4 	: 44-40,
+		SVE_I8MM	: 48-44,
+		RES3		: 52-48,
+		SVE_F32MM	: 56-52,
+		SVE_F64MM	: 60-56,
+		RES4		: 64-60;
+	};
+} AA64ZFR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		RES0		: 12-0,
+		SSBS		: 13-12,
+		RES1		: 32-13,
+		RES2		: 64-32;
+	};
+} SSBS2;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		SIMDReg 	:  4-0,
+		FPSP		:  8-4,
+		FPDP		: 12-8,
+		FPTrap		: 16-12,
+		FPDivide	: 20-16,
+		FPSqrt		: 24-20,
+		FPShVec 	: 28-24,
+		FPRound 	: 32-28,
+		RES0		: 64-32;
+	};
+} MVFR0;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		FPFtZ		:  4-0,
+		FPDNaN		:  8-4,
+		SIMDLS		: 12-8,
+		SIMDInt 	: 16-12,
+		SIMDSP		: 20-16,
+		SIMDHP		: 24-20,
+		FPHP		: 28-24,
+		SIMDFMAC 	: 32-28,
+		RES0		: 64-32;
+	};
+} MVFR1;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		SIMDMisc	:  4-0,
+		FPMisc		:  8-4,
+		RES0		: 32-8,
+		RES1		: 64-32;
+	};
+} MVFR2;
+
+typedef union
+{	/* R82; A55; A75; A76; A76AE; A77; A78; A78AE; A78C; X1; X1C; N3; V1 */
+	unsigned long long	value;	/*	Pkg:0x0000000007bfda77	*/
+	struct
+	{
+		unsigned long long
+		NUMCORE 	:  4-0,
+		NUMPE		:  9-4,
+		L3		: 10-9,
+		WRLAT		: 12-10,
+		RDLAT		: 13-12,
+		RDSLC		: 14-13,
+		ECC		: 15-14,
+		NUMMAS		: 17-15,
+		MAS		: 18-17,
+		RAZ1		: 19-18,
+		ACPW		: 20-19,
+		ACP		: 21-20,
+		RAZ2		: 22-21,
+		PPW		: 23-22,
+		PP		: 24-23,
+		RAZ3		: 25-24,
+		TRSH		: 29-25,
+		TRSV		: 33-29,
+		RAZ4		: 51-33,
+		L3SLC		: 54-51,
+		RAZ5		: 55-24,
+		SFIDX		: 59-55,
+		SFWAY		: 61-59,
+		NODES		: 64-61;
+	} IMP;
+	struct
+	{
+		unsigned long long
+		NUMCORE 	:  3-0,
+		RAZ1		:  4-3,
+		L3		:  5-4,
+		WRLAT		:  6-5,
+		RDLAT		:  7-6,
+		RDSLC		:  8-7,
+		ECC		:  9-8,
+		MAS		: 11-9,
+		ACP		: 12-11,
+		PP		: 13-12,
+		MAS_Ext 	: 14-13,
+		CPUSLC		: 22-14,
+		RAZ2		: 23-22,
+		WRDLY		: 24-23,
+		NUMPE		: 28-24,
+		RAZ3		: 30-28,
+		SafetyMode	: 32-30,
+		RSVD		: 64-32;
+	} DSU;
+} CLUSTERCFR;
+
+typedef union
+{
+	unsigned long long	value;	/*	Pkg:0x0000000000000041	*/
+	struct
+	{
+		unsigned long long
+		Revision	:  4-0,
+		Variant 	:  8-4,
+		RAZ		: 32-8,
+		RSVD		: 64-32;
+	};
+} CLUSTERIDR;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Highest 	:  8-0,
+		Guaranteed	: 16-8,
+		Most_Efficient	: 24-16,
+		Lowest		: 32-24,
+		ReservedBits	: 64-32; /* **Must be zero**		*/
+	};
+} HWP_CAPABILITIES;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		EN_Guarantee_Chg:  1-0,
+		EN_Excursion_Min:  2-1,
+		EN_Highest_Chg	:  3-2,
+		EN_PECI_OVERRIDE:  4-3,
+		ReservedBits	: 64-4;  /* **Must be zero**		*/
+	};
+} HWP_INTERRUPT;
+
+typedef union
+{
+	unsigned long long	value;
+	struct
+	{
+		unsigned long long
+		Minimum_Perf	:  8-0,
+		Maximum_Perf	: 16-8,
+		Desired_Perf	: 24-16,
+		Energy_Pref	: 32-24,
+		Activity_Window : 42-32,
+		Package_Control : 43-42,
+		ReservedBits	: 59-43,
+		Act_Window_Valid: 60-59, /* Activity_Window Valid; Default=0 */
+		EPP_Valid	: 61-60, /*1:[HWP_REQUEST];0:[HWP_REQUEST_PKG]*/
+		Desired_Valid	: 62-61, /* -> Desired_Perf		*/
+		Maximum_Valid	: 63-62, /* -> Maximum_Perf		*/
+		Minimum_Valid	: 64-63; /* -> Minimum_Perf		*/
+	};
+} HWP_REQUEST;