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[aarch64] Checking CSSELR and CCSIDR registers in ARMv9

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This commit is contained in:
CyrIng
2025-03-19 23:24:56 +01:00
parent 33b50d0a2b
commit d01cc84f0b
4 changed files with 40 additions and 26 deletions
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31
aarch64/arm_reg.h
View File

@@ -264,6 +264,33 @@ typedef union
};
} CPUPWRCTLR;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
LineSz : 3-0,
Assoc : 13-3,
Set : 28-13,
WrAlloc : 29-28,
RdAlloc : 30-29,
WrBack : 31-30,
WrThrough : 32-31,
RES0 : 63-32,
FEAT_CCIDX : 64-63;
};
struct
{
unsigned long long
LineSize : 3-0,
Associativity : 24-3,
RES1 : 32-24,
NumSets : 56-32,
RES2 : 64-56;
};
} CCSIDR;
typedef union
{
unsigned long long value;
@@ -272,8 +299,8 @@ typedef union
unsigned long long
InD : 1-0,
Level : 4-1,
RES0 : 32-4,
RES1 : 64-32;
TnD : 5-4,
RES0 : 64-5;
};
} CSSELR;

19
aarch64/corefreq-api.h
View File

@@ -33,24 +33,7 @@ typedef struct
struct CLUSTER_ST Cluster;
struct CACHE_INFO
{
union CCSIDR
{
unsigned long long value;
struct
{
unsigned long long
LineSz : 3-0,
Assoc : 13-3,
Set : 28-13,
WrAlloc : 29-28,
RdAlloc : 30-29,
WrBack : 31-30,
WrThrough : 32-31,
NumSets : 56-32,
RES0 : 63-56,
FEAT_CCIDX : 64-63;
};
} ccsid;
CCSIDR ccsid;
unsigned int Size;
} Cache[CACHE_MAX_LEVEL];
} CACHE_TOPOLOGY;

8
aarch64/corefreqd.c
View File

@@ -786,7 +786,9 @@ void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core),
for (level = 0; level < CACHE_MAX_LEVEL; level++)
if (RO(Core, AT(cpu))->T.Cache[level].ccsid.value != 0) {
RO(Shm)->Cpu[cpu].Topology.Cache[level].LineSz = \
RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSz + 4;
RO(Core, AT(cpu))->T.Cache[level].ccsid.FEAT_CCIDX ?
RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSize + 4
: RO(Core, AT(cpu))->T.Cache[level].ccsid.LineSz + 4;
RO(Shm)->Cpu[cpu].Topology.Cache[level].Set = \
RO(Core, AT(cpu))->T.Cache[level].ccsid.FEAT_CCIDX ?
@@ -794,7 +796,9 @@ void Topology(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc), RO(CORE) **RO(Core),
: RO(Core, AT(cpu))->T.Cache[level].ccsid.Set + 1;
RO(Shm)->Cpu[cpu].Topology.Cache[level].Way = \
RO(Core, AT(cpu))->T.Cache[level].ccsid.Assoc + 1;
RO(Core, AT(cpu))->T.Cache[level].ccsid.FEAT_CCIDX ?
RO(Core, AT(cpu))->T.Cache[level].ccsid.Associativity +1
: RO(Core, AT(cpu))->T.Cache[level].ccsid.Assoc + 1;
RO(Shm)->Cpu[cpu].Topology.Cache[level].Size = \
RO(Shm)->Cpu[cpu].Topology.Cache[level].Way

8
aarch64/corefreqk.c
View File

@@ -2062,10 +2062,10 @@ static CLOCK BaseClock_GenericMachine(unsigned int ratio)
static void Cache_Level(CORE_RO *Core, unsigned int level, unsigned int select)
{
const CSSELR cssel[CACHE_MAX_LEVEL] = {
[0] = { .InD = 1, .Level = 0 }, /* L1I */
[1] = { .InD = 0, .Level = 0 }, /* L1D */
[2] = { .InD = 0, .Level = 1 }, /* L2 */
[3] = { .InD = 0, .Level = 2 } /* L3 */
[0] = { .InD = 1, .Level = 0, .TnD = 0, .RES0 = 0 }, /* L1I */
[1] = { .InD = 0, .Level = 0, .TnD = 0, .RES0 = 0 }, /* L1D */
[2] = { .InD = 0, .Level = 1, .TnD = 0, .RES0 = 0 }, /* L2 */
[3] = { .InD = 0, .Level = 2, .TnD = 0, .RES0 = 0 } /* L3 */
};
volatile AA64MMFR2 mmfr2;