ich777/CoreFreq
1
0
Fork 0
mirror of https://github.com/cyring/CoreFreq.git synced 2025-07-23 12:13:07 +02:00
Code Issues Packages Projects Releases Wiki Activity

[Intel][ADL ... MTL] Keep all enabled memory controllers

Browse Source
This commit is contained in:
CyrIng
2024-07-31 12:11:59 +02:00
parent 36adf0e855
commit fdb74e7c1f
1 changed files with 14 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
x86_64/corefreqk.c
View File

@@ -6590,19 +6590,15 @@ static PCI_CALLBACK ADL_IMC(struct pci_dev *dev)
if ( (PCI_CALLBACK) 0 == rc)
{
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value != 0xffffffff) {
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
if (mc & 1) {
PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0;
} else {
for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].ADL.Sched.ReservedBits1=0;
}
}
}
break;
}
}
}
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount > 0)
{
@@ -6651,19 +6647,15 @@ static PCI_CALLBACK MTL_IMC(struct pci_dev *dev)
if ( (PCI_CALLBACK) 0 == rc)
{
if (PUBLIC(RO(Proc))->Uncore.MC[mc].MTL.MADCH.value != 0xffffffff) {
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].MTL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
if (mc & 1) {
PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0;
} else {
for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].MTL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].MTL.Sched.ReservedBits1=0;
}
}
}
break;
}
}
}
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount > 0)
{