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https://github.com/cyring/CoreFreq.git
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[Family 18h] Hygon C86 7375
[AMD] Fixed some typos
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@@ -469,7 +469,7 @@ typedef union
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unsigned long long /* MSR 0xC001_00[68:64] P-State [4:0] */
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CpuFid : 6-0, /* Core Frequency ID. RW: Value <= 2Fh */
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CpuDid : 9-6, /* Core Divisor ID. RW: 0h-4h divide by 1-16 */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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Reserved1 : 22-16,
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NbDid : 23-22, /* Northbridge Divisor ID. RW: 0-1 => 0-2 */
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Reserved2 : 25-23,
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@@ -484,7 +484,7 @@ typedef union
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unsigned long long /* MSR 0xC001_00[6B:64] P-State [7:0] */
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CpuDid : 4-0, /* Core Divisor ID. RW */
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CpuFid : 9-4, /* Core Frequency ID. RW */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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Reserved1 : 32-16,
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IddValue : 40-32, /* Current value field. RW */
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IddDiv : 42-40, /* Current divisor field. RW */
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@@ -496,7 +496,7 @@ typedef union
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unsigned long long /* MSR 0xC001_00[6B:64] P-State [7:0] */
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CpuDidLSD : 4-0, /* Core Divisor ID least significant digit.RW*/
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CpuDidMSD : 9-4, /* Core Divisor ID most significant digit. RW*/
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CpuVid : 16-9, /* Core Voltage ID. RW */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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Reserved1 : 32-16,
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IddValue : 40-32, /* Current value field. RW */
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IddDiv : 42-40, /* Current divisor field. RW */
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@@ -508,7 +508,7 @@ typedef union
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unsigned long long /* MSR 0xC001_00[6B:64] P-state [7:0] */
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CpuFid : 6-0, /* Core Frequency ID. RW */
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CpuDid : 9-6, /* Core Divisor ID. RW:0h-4h divide by 1-16 */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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CpuVid : 16-9, /* Core Voltage ID. RW */
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CpuVid_bit : 17-16,
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Reserved1 : 22-17,
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NbPstate : 23-22, /* Northbrige MSR 0xC001_0071[NbPstateDis] */
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@@ -522,8 +522,8 @@ typedef union
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{
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unsigned long long /* MSR 0xC001_0064 [P-state [7:0]] */
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CpuFid : 8-0, /* Core Frequency ID. RW: FFh-10h <Value>*25 */
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CpuDfsId : 14-8, /* Core Divisor ID. RW */
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CpuVid : 22-14, /* Core Voltage ID. RW */
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CpuDfsId : 14-8, /* Core Divisor ID. RW */
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CpuVid : 22-14, /* Core Voltage ID. RW */
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IddValue : 30-22, /* Current Dissipation in amps. RW */
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IddDiv : 32-30, /* Current Dissipation Divisor. RW */
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Reserved : 63-32,
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@@ -552,7 +552,7 @@ typedef union
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CpuFid : 8-0, /* RO: Current Core Frequency ID */
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CpuDfsId : 14-8, /* RO: Current Core DID */
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CpuVid : 22-14, /* RO: Current Core VID */
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CurHwPstate : 25-22, /* RO: Cuurent hardware P-state */
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CurHwPstate : 25-22, /* RO: Current hardware P-state */
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Reserved : 64-63;
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};
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} HW_PSTATE_STATUS;
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@@ -2034,7 +2034,10 @@ static void InitTimer_AMD_Zen4_RPL(unsigned int cpu) ;
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"Hygon C86 XXXX NN-core Processor"
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7285(32),7280(64),7265(24),
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5285(16),
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3285( 8),3280( 8),3230( 4), */
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3285( 8),3280( 8),3230( 4),
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[Family 18h] 9F_02h
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Stepping 2
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"Hygon C86 7375" */
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#define _Hygon_Family_18h \
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{.ExtFamily=0x9, .Family=0xF, .ExtModel=0x0, .Model=0x0}
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