CyrIng
|
7d00073f0e
|
[Build][aarch64] Temperature compilation based on CONFIG_THERMAL
|
2025-07-08 09:22:50 +02:00 |
|
CyrIng
|
a9bd15efe3
|
[aarch64] Getting temperature from the Generic Thermal Management
|
2025-07-07 16:39:47 +02:00 |
|
CyrIng
|
d1a61cb80d
|
[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state
|
2025-06-23 09:14:59 +02:00 |
|
CyrIng
|
743135c206
|
[aarch64] Provide the state of WFI/WFE Low Power Methods
|
2025-06-20 22:48:45 +02:00 |
|
CyrIng
|
40a47f225a
|
[aarch64] Set the UI comment for PMULL instruction
|
2025-06-16 18:36:26 +02:00 |
|
CyrIng
|
dd9886812e
|
[aarch64] Registers requiring a safe access guard (TID3)
|
2025-06-14 13:27:49 +02:00 |
|
CyrIng
|
efb383dd5a
|
[aarch64] Drop Experimental guard to safely read ID_AA64MMFR3_EL1
|
2025-06-14 08:43:01 +02:00 |
|
CyrIng
|
f16141f14c
|
[aarch64] Display detected Interconnect Technology in UI
|
2025-06-13 19:07:41 +02:00 |
|
CyrIng
|
92e070b098
|
[aarch64] Query Cache Coherent Network|Interconnect via DT
|
2025-06-11 14:56:46 +02:00 |
|
CyrIng
|
cf4269f0fe
|
[aarch64] Adding multiple Processors and Architectures
* Cortex-A320, Cortex-A520, Cortex-A720AE, Cortex-A725,
Cortex-R82AE, Cortex-X925, Neoverse N3, Neoverse V3, Neoverse V3AE
* ARMv8.1-A, ARMv8.8-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A
|
2025-06-10 22:02:43 +02:00 |
|
CyrIng
|
0f682fef43
|
[aarch64] Assign DSU-RTL version according to detected ARM arch.
|
2025-06-09 21:48:10 +02:00 |
|
CyrIng
|
63b9b9c8f4
|
[aarch64] Improve detection of Mesh interconnect via DT/ACPI
|
2025-06-09 16:15:41 +02:00 |
|
CyrIng
|
cbc2c206f0
|
[aarch64] Query CMN either from DeviceTree either from ACPI
|
2025-06-08 16:03:51 +02:00 |
|
CyrIng
|
2d078106ad
|
[aarch64] JSON export DSU, CMN, CCI, CCN
|
2025-06-07 21:00:10 +02:00 |
|
CyrIng
|
4cdca0e8f1
|
[aarch64] Display the presence of the DynamIQ Shared Unit (DSU)
|
2025-06-07 16:29:25 +02:00 |
|
CyrIng
|
a0dd03153f
|
[aarch64] Added SMT and big.LITTLE labels in the UI footer
|
2025-06-07 15:16:58 +02:00 |
|
CyrIng
|
3a7c7033f2
|
[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16
|
2025-06-05 20:46:55 +02:00 |
|
CyrIng
|
90d4825ad0
|
[Kernel][6.15] Fix missing cpufreq_get_policy and asm/amd/nb.h
|
2025-05-31 10:05:27 +02:00 |
|
CyrIng
|
dfac22ae8a
|
[Doc] Obfuscate support email format in README and CLI usage
|
2025-05-29 09:12:38 +02:00 |
|
CyrIng
|
6b7ea15142
|
[aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables
|
2025-05-28 15:17:58 +02:00 |
|
CyrIng
|
6b176cd026
|
[Kernel] Use VM_DONTEXPAND in mmap() for stability and isolation
|
2025-05-28 07:01:03 +02:00 |
|
CyrIng
|
a3b978a2d3
|
[Code Review] Make module parameters load-time only (#547)
|
2025-05-22 19:19:09 +02:00 |
|
CyrIng
|
2569ef0518
|
[aarch64][riscv64][ppc64] Improving the CPU topology to detect BSP
|
2025-05-19 20:50:18 +02:00 |
|
CyrIng
|
e684e642d0
|
[UI] Increased length of L3 cache digits in header
|
2025-05-12 12:12:29 +02:00 |
|
CyrIng
|
93c7096e2b
|
[Code Review] Refactored variable names for inclusivity
|
2025-05-08 11:17:40 +02:00 |
|
CyrIng
|
d94626d276
|
[IMC] Can display Twelve Channel memory controller
* Renamed `Disabled` to `Undefined` channels
|
2025-05-03 17:48:32 +02:00 |
|
CyrIng
|
c508b7d3f1
|
[CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number
|
2025-04-18 14:48:51 +02:00 |
|
CyrIng
|
2cce3ed28d
|
[Build] Prevent module loading if detected CPU count > CORE_COUNT
|
2025-04-12 09:37:20 +02:00 |
|
CyrIng
|
812f297a22
|
[Build] Kernel 6.15 is switching to use hrtimer_setup()
|
2025-04-09 09:54:20 +02:00 |
|
CyrIng
|
5c620b7f42
|
[Build] of_root defined since Kernel 3.19
|
2025-04-02 14:54:47 +02:00 |
|
CyrIng
|
17886cba2b
|
[Build] Replaced inline C functions with static or macro
* Kernel 6.14 `node_to_amd_nb()` workaround
|
2025-03-31 16:49:47 +02:00 |
|
CyrIng
|
a44d56c315
|
Merge branch 'hotfix_optimizations'
|
2025-03-31 12:16:27 +02:00 |
|
CyrIng
|
9a9a9651e8
|
[Build] Added CONFIG_ACPI_CPPC_LIB to conditionnaly build EPP
|
2025-03-26 14:10:27 +01:00 |
|
CyrIng
|
73d1856d4a
|
uBench: Code clean-up
|
2025-03-22 09:18:09 +01:00 |
|
CyrIng
|
d01cc84f0b
|
[aarch64] Checking CSSELR and CCSIDR registers in ARMv9
|
2025-03-19 23:24:56 +01:00 |
|
CyrIng
|
33b50d0a2b
|
[aarch64] If FEAT_CCIDX implemented read NumSets from upper reg
|
2025-03-19 17:26:50 +01:00 |
|
CyrIng
|
d54e1b8c56
|
[aarch64] Safely access the PMU registers
* Detect the Android AVF hypervisor
* Comment PMC in uBench macros
|
2025-03-19 13:21:26 +01:00 |
|
CyrIng
|
5dba49ee90
|
[aarch64][riscv64][ppc64] Improving DT integration to detect VM
|
2025-03-16 12:55:00 +01:00 |
|
CyrIng
|
260d8af2ff
|
[AArch64] Improving virtualization detection from Device Tree
|
2025-03-15 15:09:44 +01:00 |
|
CyrIng
|
f314201943
|
[Build] Changed some inline function prototypes
|
2025-02-23 08:05:03 +01:00 |
|
CyrIng
|
17a08f536a
|
Copyright (C) 2015-2025 CYRIL COURTIAT
|
2025-01-19 13:15:05 +01:00 |
|
CyrIng
|
f688e95c7e
|
[AArch64] Checking specification of Memory Model Feature Registers
|
2024-12-15 11:10:01 +01:00 |
|
CyrIng
|
51827cdc10
|
[AArch64] Aggregate and display ISA features of ID_AA64ISAR3_EL1
|
2024-12-12 19:00:57 +01:00 |
|
CyrIng
|
d0ac57de0f
|
[AArch64] Instruction Set Attribute Register 3 ID_AA64ISAR3_EL1
|
2024-12-11 14:40:20 +01:00 |
|
CyrIng
|
8eae541e8c
|
[UI] Fix System Registers window for a 3 digits CPU id number
|
2024-12-06 22:08:34 +01:00 |
|
CyrIng
|
a33aa70778
|
[AArch64] Processor Feature Register 2 AA64PFR2_EL1
|
2024-12-06 21:47:42 +01:00 |
|
CyrIng
|
d73f4dc6c8
|
[AArch64] Display FP and SIMD bits from MVFR
* Added remaining `CLRBHB` and `PCDPHINT` of `ISAR2`
|
2024-12-04 19:47:49 +01:00 |
|
CyrIng
|
0ee6ea9d19
|
[AArch64] Display the Streaming Vector Control Register SVCR
* Query and export the Media and VFP Feature Registers `MVFR`
|
2024-12-04 13:26:40 +01:00 |
|
CyrIng
|
56d46c24a3
|
[AArch64] Display, export Floating-point Control Register FPCR
|
2024-12-04 01:47:17 +01:00 |
|
CyrIng
|
e6072d7a39
|
[AArch64] Architectural Feature Access Control Register CPACR
|
2024-11-30 12:27:22 +01:00 |
|