ich777/CoreFreq
1
0
Fork 0
mirror of https://github.com/cyring/CoreFreq.git synced 2025-07-23 04:12:59 +02:00
Code Issues Packages Projects Releases Wiki Activity

[Code Review] Intel Core Ultra: Registers name and address updated

Browse Source
This commit is contained in:
CyrIng
2025-05-18 12:30:34 +02:00
parent c3704a245a
commit e7deead548
4 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
x86_64/corefreq-api.h
View File

@@ -606,7 +606,7 @@ typedef struct
/* E014h */ MTL_IMC_CR_TC_WRRD WRRD; /* 32 bits */
/* E018h */ MTL_IMC_CR_TC_WRWR WRWR; /* 32 bits */
/* E050h */ MTL_IMC_TC_PWDEN PWDEN; /* 64-bits */
/* E070h */ MTL_IMC_CR_TC_ODT ODT; /* 64 bits */
/* E070h */ MTL_IMC_TC_CAS CAS; /* 64 bits */
/* E088h */ MTL_IMC_SC_GS_CFG Sched; /* 64 bits */
/* E4A0h */ MTL_IMC_REFRESH_TC Refresh; /*64 bits */
/* E4C0h */ MTL_IMC_SREXITTP SRExit; /* 64 bits */

10
x86_64/corefreqd.c
View File

@@ -6123,10 +6123,10 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
unsigned short tWR_quantity;
TIMING(mc, cha).tCCD = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ODT.tCCD;
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.CAS.tCCD;
TIMING(mc, cha).tCL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ODT.tCL;
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.CAS.tCL;
TIMING(mc, cha).tRCD_RD = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ACT.tRCD;
@@ -6167,11 +6167,11 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
break;
}
if (RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.Timing.tWRPRE >=
(RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ODT.tCWL + tWR_quantity))
(RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.CAS.tCWL + tWR_quantity))
{
TIMING(mc, cha).tWR = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.Timing.tWRPRE
- RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ODT.tCWL
- RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.CAS.tCWL
- tWR_quantity;
}
@@ -6185,7 +6185,7 @@ void MTL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ACT.tFAW;
TIMING(mc, cha).tCWL = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.ODT.tCWL;
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.CAS.tCWL;
TIMING(mc, cha).tRDRD_SG = \
RO(Proc)->Uncore.MC[mc].Channel[cha].MTL.RDRD.tRDRD_SG;

2
x86_64/corefreqk.c
View File

@@ -5737,7 +5737,7 @@ static void Query_MTL_IMC(void __iomem *mchmap, unsigned short mc)
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].MTL.PWDEN.value = \
readq(mchmap + 0xe050 + 0x800 * cha);
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].MTL.ODT.value = \
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].MTL.CAS.value = \
readq(mchmap + 0xe070 + 0x800 * cha);
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].MTL.Refresh.value = \

6
x86_64/intel_reg.h
View File

@@ -4153,7 +4153,7 @@ typedef union
} ADL_IMC_CR_TC_ACT;
typedef union
{ /* Device: 0 - Function: 0 - Offset Channel0: E138h & Channel1: TODO */
{ /* Device: 0 - Function: 0 - Offset Channel0: E138h & Channel1: E938h */
unsigned long long value;
struct {
unsigned long long
@@ -4625,7 +4625,7 @@ typedef union
tCWL : 32-24, /* LPDDR4: 4-64; DDR4: 5-64 @ 1N */
ReservedBits3 : 64-32;
};
} MTL_IMC_CR_TC_ODT; /* ODT timing parameters */
} MTL_IMC_TC_CAS; /* CAS timing parameters */
typedef union
{ /* Device: 0 - Function: 0 - Offset Channel0: 423Ch & Channel1: 463Ch */
@@ -4663,7 +4663,7 @@ typedef union
} ADL_IMC_REFRESH_TC; /* Refresh timing parameters */
typedef union
{ /* Device: 0 - Function: 0 - Offset Channel0: E4A0h & Channel1: TODO */
{ /* Device: 0 - Function: 0 - Offset Channel0: E4A0h & Channel1: ECA0h */
unsigned long long value;
struct {
unsigned long long