CyrIng
a9bd15efe3
[aarch64] Getting temperature from the Generic Thermal Management
2025-07-07 16:39:47 +02:00
CyrIng
35f9a9c384
[AMD][Zen5][Strix Halo] Adding the RYZEN AI MAX 385
2025-06-30 23:24:12 +02:00
CyrIng
14ff2c58b7
[AMD] Add fallback TjMax for legacy CPU families
2025-06-29 12:35:02 +02:00
CyrIng
deb3da7f00
[AMD] Add missing DCU and XPROC_LEAK bitmasks on legacy processors
2025-06-23 19:36:46 +02:00
CyrIng
396c8dc7ce
[AMD][Excavator] Fix setting the scope of temperature to Package
2025-06-23 14:57:58 +02:00
CyrIng
d1a61cb80d
[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state
2025-06-23 09:14:59 +02:00
CyrIng
78b27bb575
[Build] Support building CoreFreq binaries individually or together
2025-06-22 13:03:15 +02:00
CyrIng
2ca0adf748
[CR] In _F4() cast complement mask to the type of bit argument
2025-06-21 19:27:41 +02:00
CyrIng
633c8519a6
[UI] Rephrased string for the CPUID.80000001.ECX[27] feature
2025-06-21 12:31:59 +02:00
CyrIng
f618ffb4f8
[UI] Optimize POWERED() macro with branchless 3-state array lookup
2025-06-21 10:55:45 +02:00
CyrIng
743135c206
[aarch64] Provide the state of WFI/WFE Low Power Methods
2025-06-20 22:48:45 +02:00
CyrIng
40a47f225a
[aarch64] Set the UI comment for PMULL instruction
2025-06-16 18:36:26 +02:00
CyrIng
dd9886812e
[aarch64] Registers requiring a safe access guard (TID3)
2025-06-14 13:27:49 +02:00
CyrIng
efb383dd5a
[aarch64] Drop Experimental guard to safely read ID_AA64MMFR3_EL1
2025-06-14 08:43:01 +02:00
CyrIng
f16141f14c
[aarch64] Display detected Interconnect Technology in UI
2025-06-13 19:07:41 +02:00
CyrIng
92e070b098
[aarch64] Query Cache Coherent Network|Interconnect via DT
2025-06-11 14:56:46 +02:00
CyrIng
cf4269f0fe
[aarch64] Adding multiple Processors and Architectures
...
* Cortex-A320, Cortex-A520, Cortex-A720AE, Cortex-A725,
Cortex-R82AE, Cortex-X925, Neoverse N3, Neoverse V3, Neoverse V3AE
* ARMv8.1-A, ARMv8.8-A, ARMv9.1-A, ARMv9.2-A, ARMv9.3-A
2025-06-10 22:02:43 +02:00
CyrIng
0f682fef43
[aarch64] Assign DSU-RTL version according to detected ARM arch.
2025-06-09 21:48:10 +02:00
CyrIng
63b9b9c8f4
[aarch64] Improve detection of Mesh interconnect via DT/ACPI
2025-06-09 16:15:41 +02:00
CyrIng
cbc2c206f0
[aarch64] Query CMN either from DeviceTree either from ACPI
2025-06-08 16:03:51 +02:00
CyrIng
2d078106ad
[aarch64] JSON export DSU, CMN, CCI, CCN
2025-06-07 21:00:10 +02:00
CyrIng
4cdca0e8f1
[aarch64] Display the presence of the DynamIQ Shared Unit (DSU)
2025-06-07 16:29:25 +02:00
CyrIng
a0dd03153f
[aarch64] Added SMT and big.LITTLE labels in the UI footer
2025-06-07 15:16:58 +02:00
CyrIng
3a7c7033f2
[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16
2025-06-05 20:46:55 +02:00
CyrIng
b6223385b9
[AMD] Decodes voltages of Phoenix families using Rembrandt SVI
2025-06-04 12:59:45 +02:00
CyrIng
c2e28ed3ee
[AMD][Raphael] Attempt to read the SoC voltage
2025-05-31 11:46:19 +02:00
CyrIng
90d4825ad0
[Kernel][6.15] Fix missing cpufreq_get_policy and asm/amd/nb.h
2025-05-31 10:05:27 +02:00
CyrIng
2c03ceab46
[AMD][Raphael] Don't probe the HSMP on Desktop/Mobile/Embedded
2025-05-30 08:31:18 +02:00
CyrIng
dfac22ae8a
[Doc] Obfuscate support email format in README and CLI usage
2025-05-29 09:12:38 +02:00
CyrIng
0974aceba3
[Doc] Added command line usage instructions to the README
2025-05-29 08:53:41 +02:00
CyrIng
6b7ea15142
[aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables
2025-05-28 15:17:58 +02:00
CyrIng
6b176cd026
[Kernel] Use VM_DONTEXPAND in mmap() for stability and isolation
2025-05-28 07:01:03 +02:00
CyrIng
989036f384
[Intel] Added the Bartlett Lake/S entry
...
* `Clearwater Forest` architecture name fix
2025-05-26 13:44:53 +02:00
CyrIng
5ec7b7c743
[AMD][Genoa] Attempt to read SOC voltage
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* Apply monitoring interval in RAM consumption calculation
2025-05-24 11:55:12 +02:00
CyrIng
094c2f3c27
[Kernel] If version is >= 6.0 then call SMU via CONFIG_AMD_NB
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Ryzen 9950X issue #548
2025-05-22 20:22:39 +02:00
CyrIng
a3b978a2d3
[Code Review] Make module parameters load-time only ( #547 )
2025-05-22 19:19:09 +02:00
CyrIng
6a99cfb4b4
[x86_64] Add lock prefix to bit ops for cross-package atomicity
2025-05-20 21:54:11 +02:00
CyrIng
2569ef0518
[aarch64][riscv64][ppc64] Improving the CPU topology to detect BSP
2025-05-19 20:50:18 +02:00
CyrIng
e7deead548
[Code Review] Intel Core Ultra: Registers name and address updated
2025-05-18 12:30:34 +02:00
CyrIng
c3704a245a
[Intel][ADL/N] Adding "Twin Lake" and "Amston Lake" codenames
2025-05-16 23:04:51 +02:00
CyrIng
398dc12544
[AMD][Zen] Count DIMM ranks from the enabled chip select
2025-05-14 14:33:59 +02:00
CyrIng
fcc0e0f70e
[AMD][Zen][UMC] Computes DIMM ranks based on DDR type
2025-05-12 17:13:28 +02:00
CyrIng
347045ed17
Revert "[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98"
...
This reverts commit e5a5d0c1d6
2025-05-12 15:37:08 +02:00
CyrIng
e684e642d0
[UI] Increased length of L3 cache digits in header
2025-05-12 12:12:29 +02:00
CyrIng
c2b396a215
[AMD][Zen] Now conducts Datafabric calls through Kernel PCI
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[HSMP] Provides its own lock rather than SMN' lock
2025-05-12 11:55:34 +02:00
CyrIng
22f9c460a9
[AMD][Zen] HSMP arguments index fix in CONFIG_AMD_NB build mode
2025-05-11 13:03:04 +02:00
CyrIng
acbe192ad5
[AMD][Zen] Replaced package thermal with a pointer function
2025-05-10 18:11:05 +02:00
CyrIng
43fd828bdc
[AMD][Genoa] Probe up to four memory controllers
2025-05-10 15:11:21 +02:00
CyrIng
0729f349e4
[AMD] Improved EPYC Genoa support
...
* CCD and CCX topology fixed to compute the right thermal SMU address
* Increase `BIT_IO_RETRIES_COUNT` to parallelize `HSMP_RD_DIMM_PWR` calls
* Added specifics for an "Eng Sample" of Genoa architecture
2025-05-09 19:44:16 +02:00
CyrIng
93c7096e2b
[Code Review] Refactored variable names for inclusivity
2025-05-08 11:17:40 +02:00
