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[no ci] Format Changes

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This commit is contained in:
Michael J. Manley
2022-06-23 11:26:13 -07:00
parent fa9c5ef6c0
commit bed5fced7b
725 changed files with 219949 additions and 199821 deletions
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148
.clang-format Normal file
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@@ -0,0 +1,148 @@
---
Language: Cpp
# BasedOnStyle: LLVM
AccessModifierOffset: -4
AlignAfterOpenBracket: Align
AlignConsecutiveMacros: false
AlignConsecutiveAssignments: false
AlignConsecutiveBitFields: false
AlignConsecutiveDeclarations: false
AlignEscapedNewlines: Right
AlignOperands: Align
AlignTrailingComments: true
AllowAllArgumentsOnNextLine: true
AllowAllConstructorInitializersOnNextLine: true
AllowAllParametersOfDeclarationOnNextLine: true
AllowShortEnumsOnASingleLine: true
AllowShortBlocksOnASingleLine: Never
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: All
AllowShortLambdasOnASingleLine: All
AllowShortIfStatementsOnASingleLine: Never
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: MultiLine
BinPackArguments: true
BinPackParameters: true
BraceWrapping:
AfterCaseLabel: false
AfterClass: false
AfterControlStatement: Never
AfterEnum: false
AfterFunction: false
AfterNamespace: false
AfterObjCDeclaration: false
AfterStruct: false
AfterUnion: false
AfterExternBlock: false
BeforeCatch: false
BeforeElse: false
BeforeLambdaBody: false
BeforeWhile: false
IndentBraces: false
SplitEmptyFunction: true
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: None
BreakBeforeBraces: Attach
BreakBeforeInheritanceComma: false
BreakInheritanceList: BeforeColon
BreakBeforeTernaryOperators: true
BreakConstructorInitializersBeforeComma: false
BreakConstructorInitializers: BeforeColon
BreakAfterJavaFieldAnnotations: false
BreakStringLiterals: true
ColumnLimit: 130
CommentPragmas: '^ IWYU pragma:'
CompactNamespaces: false
ConstructorInitializerAllOnOneLineOrOnePerLine: false
ConstructorInitializerIndentWidth: 8
ContinuationIndentWidth: 8
Cpp11BracedListStyle: true
DeriveLineEnding: true
DerivePointerAlignment: false
DisableFormat: false
ExperimentalAutoDetectBinPacking: false
FixNamespaceComments: true
ForEachMacros:
- foreach
- Q_FOREACH
- BOOST_FOREACH
IncludeBlocks: Preserve
IncludeCategories:
- Regex: '^"(llvm|llvm-c|clang|clang-c)/'
Priority: 2
SortPriority: 0
- Regex: '^(<|"(gtest|gmock|isl|json)/)'
Priority: 3
SortPriority: 0
- Regex: '.*'
Priority: 1
SortPriority: 0
IncludeIsMainRegex: '(Test)?$'
IncludeIsMainSourceRegex: ''
IndentCaseLabels: false
IndentCaseBlocks: false
IndentGotoLabels: true
IndentPPDirectives: None
IndentExternBlock: AfterExternBlock
IndentWidth: 8
IndentWrappedFunctionNames: false
InsertTrailingCommas: None
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
NamespaceIndentation: None
ObjCBinPackProtocolList: Auto
ObjCBlockIndentWidth: 8
ObjCBreakBeforeNestedBlockParam: true
ObjCSpaceAfterProperty: false
ObjCSpaceBeforeProtocolList: true
PenaltyBreakAssignment: 2
PenaltyBreakBeforeFirstCallParameter: 19
PenaltyBreakComment: 300
PenaltyBreakFirstLessLess: 120
PenaltyBreakString: 1000
PenaltyBreakTemplateDeclaration: 10
PenaltyExcessCharacter: 1000000
PenaltyReturnTypeOnItsOwnLine: 60
PointerAlignment: Right
ReflowComments: true
SortIncludes: false
SortUsingDeclarations: false
SpaceAfterCStyleCast: false
SpaceAfterLogicalNot: false
SpaceAfterTemplateKeyword: true
SpaceBeforeAssignmentOperators: true
SpaceBeforeCpp11BracedList: false
SpaceBeforeCtorInitializerColon: true
SpaceBeforeInheritanceColon: true
SpaceBeforeParens: ControlStatements
SpaceBeforeRangeBasedForLoopColon: true
SpaceInEmptyBlock: false
SpaceInEmptyParentheses: false
SpacesBeforeTrailingComments: 1
SpacesInAngles: false
SpacesInConditionalStatement: false
SpacesInContainerLiterals: true
SpacesInCStyleCastParentheses: false
SpacesInParentheses: false
SpacesInSquareBrackets: false
SpaceBeforeSquareBrackets: false
Standard: Latest
StatementMacros:
- Q_UNUSED
- QT_REQUIRE_VERSION
TabWidth: 8
UseCRLF: false
UseTab: Never
WhitespaceSensitiveMacros:
- STRINGIZE
- PP_STRINGIZE
- BOOST_PP_STRINGIZE
---

1097
experimental/printer_epsonlx810/lpt_epsonlx810.c
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File diff suppressed because it is too large Load Diff

23
experimental/printer_epsonlx810/plugin.c
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@@ -8,38 +8,35 @@ extern char pcem_path[512];
LPT_DEVICE l_epsonlx810 = {"Epson LX-810 Printer", "lpt_epsonlx810", &lpt_epsonprinter_device};
#define safe_strncpy(a,b,n) do { strncpy((a),(b),(n)-1); (a)[(n)-1] = 0; } while (0)
#define safe_strncpy(a, b, n) \
do { \
strncpy((a), (b), (n)-1); \
(a)[(n)-1] = 0; \
} while (0)
char printer_path[512];
void set_printer_path(char *s)
{
void set_printer_path(char *s) {
safe_strncpy(printer_path, s, 512);
append_slash(printer_path, 512);
}
void load_config()
{
void load_config() {
char *cfg_printer_path = config_get_string(CFG_GLOBAL, "Paths", "printer_path", 0);
if (cfg_printer_path)
set_printer_path(cfg_printer_path);
}
void save_config()
{
config_set_string(CFG_GLOBAL, "Paths", "printer_path", printer_path);
}
void save_config() { config_set_string(CFG_GLOBAL, "Paths", "printer_path", printer_path); }
void init_config()
{
void init_config() {
char s[512];
append_filename(s, pcem_path, "printer/", 512);
set_printer_path(s);
}
PLUGIN_INIT(printer_epsonlx810)
{
PLUGIN_INIT(printer_epsonlx810) {
add_config_callback(load_config, save_config, init_config);
pcem_add_lpt(&l_epsonlx810);
}

18
experimental/printer_epsonlx810/wx-imagesave.cc
View File

@@ -4,20 +4,16 @@
#include <wx/wfstream.h>
#include <wx/log.h>
int wx_image_save_fullpath(const char* fullpath, const char* format, unsigned char* rgba, int width, int height, int alpha)
{
int wx_image_save_fullpath(const char *fullpath, const char *format, unsigned char *rgba, int width, int height, int alpha) {
int x, y;
wxLogNull logNull;
wxImage image(width, height);
if (alpha)
{
if (alpha) {
// these will be automatically freed
unsigned char *rgb = (unsigned char *)malloc(width * height * 3);
unsigned char *a = (unsigned char *)malloc(width * height);
for (x = 0; x < width; ++x)
{
for (y = 0; y < height; ++y)
{
for (x = 0; x < width; ++x) {
for (y = 0; y < height; ++y) {
rgb[(y * width + x) * 3 + 0] = rgba[(y * width + x) * 4 + 0];
rgb[(y * width + x) * 3 + 1] = rgba[(y * width + x) * 4 + 1];
rgb[(y * width + x) * 3 + 2] = rgba[(y * width + x) * 4 + 2];
@@ -26,8 +22,7 @@ int wx_image_save_fullpath(const char* fullpath, const char* format, unsigned ch
}
image.SetData(rgb);
image.SetAlpha(a);
}
else
} else
image.SetData(rgba, true);
wxImageHandler *h;
@@ -42,8 +37,7 @@ int wx_image_save_fullpath(const char* fullpath, const char* format, unsigned ch
h = new wxPNGHandler();
int res = 0;
if (h)
{
if (h) {
wxString p(fullpath);
wxFileOutputStream stream(p);

88
includes/private/bswap.h
View File

@@ -11,16 +11,13 @@
#define bswap_16(x) \
({ \
uint16_t __x = (x); \
((uint16_t)( \
(((uint16_t)(__x) & (uint16_t)0x00ffU) << 8) | \
(((uint16_t)(__x) & (uint16_t)0xff00U) >> 8) )); \
((uint16_t)((((uint16_t)(__x) & (uint16_t)0x00ffU) << 8) | (((uint16_t)(__x) & (uint16_t)0xff00U) >> 8))); \
})
#define bswap_32(x) \
({ \
uint32_t __x = (x); \
((uint32_t)( \
(((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
((uint32_t)((((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
(((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
(((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
(((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24))); \
@@ -29,8 +26,7 @@
#define bswap_64(x) \
({ \
uint64_t __x = (x); \
((uint64_t)( \
(uint64_t)(((uint64_t)(__x) & (uint64_t)0x00000000000000ffULL) << 56) | \
((uint64_t)((uint64_t)(((uint64_t)(__x) & (uint64_t)0x00000000000000ffULL) << 56) | \
(uint64_t)(((uint64_t)(__x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
(uint64_t)(((uint64_t)(__x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
(uint64_t)(((uint64_t)(__x) & (uint64_t)0x00000000ff000000ULL) << 8) | \
@@ -42,35 +38,17 @@
#endif /* !HAVE_BYTESWAP_H */
static inline uint16_t bswap16(uint16_t x)
{
return bswap_16(x);
}
static inline uint16_t bswap16(uint16_t x) { return bswap_16(x); }
static inline uint32_t bswap32(uint32_t x)
{
return bswap_32(x);
}
static inline uint32_t bswap32(uint32_t x) { return bswap_32(x); }
static inline uint64_t bswap64(uint64_t x)
{
return bswap_64(x);
}
static inline uint64_t bswap64(uint64_t x) { return bswap_64(x); }
static inline void bswap16s(uint16_t *s)
{
*s = bswap16(*s);
}
static inline void bswap16s(uint16_t *s) { *s = bswap16(*s); }
static inline void bswap32s(uint32_t *s)
{
*s = bswap32(*s);
}
static inline void bswap32s(uint32_t *s) { *s = bswap32(*s); }
static inline void bswap64s(uint64_t *s)
{
*s = bswap64(*s);
}
static inline void bswap64s(uint64_t *s) { *s = bswap64(*s); }
#if defined(WORDS_BIGENDIAN)
#define be_bswap(v, size) (v)
@@ -85,35 +63,17 @@ static inline void bswap64s(uint64_t *s)
#endif
#define CPU_CONVERT(endian, size, type) \
static inline type endian ## size ## _to_cpu(type v)\
{\
return endian ## _bswap(v, size);\
}\
static inline type endian##size##_to_cpu(type v) { return endian##_bswap(v, size); } \
\
static inline type cpu_to_ ## endian ## size(type v)\
{\
return endian ## _bswap(v, size);\
}\
static inline type cpu_to_##endian##size(type v) { return endian##_bswap(v, size); } \
\
static inline void endian ## size ## _to_cpus(type *p)\
{\
endian ## _bswaps(p, size)\
}\
static inline void endian##size##_to_cpus(type *p) { endian##_bswaps(p, size) } \
\
static inline void cpu_to_ ## endian ## size ## s(type *p)\
{\
endian ## _bswaps(p, size)\
}\
static inline void cpu_to_##endian##size##s(type *p) { endian##_bswaps(p, size) } \
\
static inline type endian ## size ## _to_cpup(const type *p)\
{\
return endian ## size ## _to_cpu(*p);\
}\
static inline type endian##size##_to_cpup(const type *p) { return endian##size##_to_cpu(*p); } \
\
static inline void cpu_to_ ## endian ## size ## w(type *p, type v)\
{\
*p = cpu_to_ ## endian ## size(v);\
}
static inline void cpu_to_##endian##size##w(type *p, type v) { *p = cpu_to_##endian##size(v); }
CPU_CONVERT(be, 16, uint16_t)
CPU_CONVERT(be, 32, uint32_t)
@@ -137,16 +97,14 @@ CPU_CONVERT(le, 64, uint64_t)
#else
static inline void cpu_to_le16wu(uint16_t *p, uint16_t v)
{
static inline void cpu_to_le16wu(uint16_t *p, uint16_t v) {
uint8_t *p1 = (uint8_t *)p;
p1[0] = v;
p1[1] = v >> 8;
}
static inline void cpu_to_le32wu(uint32_t *p, uint32_t v)
{
static inline void cpu_to_le32wu(uint32_t *p, uint32_t v) {
uint8_t *p1 = (uint8_t *)p;
p1[0] = v;
@@ -155,28 +113,24 @@ static inline void cpu_to_le32wu(uint32_t *p, uint32_t v)
p1[3] = v >> 24;
}
static inline uint16_t le16_to_cpupu(const uint16_t *p)
{
static inline uint16_t le16_to_cpupu(const uint16_t *p) {
const uint8_t *p1 = (const uint8_t *)p;
return p1[0] | (p1[1] << 8);
}
static inline uint32_t le32_to_cpupu(const uint32_t *p)
{
static inline uint32_t le32_to_cpupu(const uint32_t *p) {
const uint8_t *p1 = (const uint8_t *)p;
return p1[0] | (p1[1] << 8) | (p1[2] << 16) | (p1[3] << 24);
}
static inline void cpu_to_be16wu(uint16_t *p, uint16_t v)
{
static inline void cpu_to_be16wu(uint16_t *p, uint16_t v) {
uint8_t *p1 = (uint8_t *)p;
p1[0] = v >> 8;
p1[1] = v;
}
static inline void cpu_to_be32wu(uint32_t *p, uint32_t v)
{
static inline void cpu_to_be32wu(uint32_t *p, uint32_t v) {
uint8_t *p1 = (uint8_t *)p;
p1[0] = v >> 24;

3
includes/private/bus/mca.h
View File

@@ -1,7 +1,8 @@
#ifndef _MCA_H_
#define _MCA_H_
void mca_init(int nr_cards);
void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), void (*reset)(void *priv), void *priv);
void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), void (*reset)(void *priv),
void *priv);
void mca_set_index(int index);
uint8_t mca_read(uint16_t port);
void mca_write(uint16_t port, uint8_t val);

6
includes/private/bus/pci.h
View File

@@ -2,8 +2,10 @@
#define _PCI_H_
void pci_init(int type);
void pci_slot(int card);
void pci_add_specific(int card, uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
int pci_add(uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
void pci_add_specific(int card, uint8_t (*read)(int func, int addr, void *priv),
void (*write)(int func, int addr, uint8_t val, void *priv), void *priv);
int pci_add(uint8_t (*read)(int func, int addr, void *priv), void (*write)(int func, int addr, uint8_t val, void *priv),
void *priv);
void pci_set_irq_routing(int card, int irq);
void pci_set_card_routing(int card, int pci_int);
void pci_set_irq(int card, int pci_int);

111
includes/private/codegen/codegen.h
View File

@@ -29,8 +29,7 @@
same page).
*/
typedef struct codeblock_t
{
typedef struct codeblock_t {
uint32_t pc;
uint32_t _cs;
uint32_t phys, phys_2;
@@ -86,13 +85,9 @@ extern uint8_t *block_write_data;
#define BLOCK_INVALID 0
static inline int get_block_nr(codeblock_t *block)
{
return ((uintptr_t)block - (uintptr_t)codeblock) / sizeof(codeblock_t);
}
static inline int get_block_nr(codeblock_t *block) { return ((uintptr_t)block - (uintptr_t)codeblock) / sizeof(codeblock_t); }
static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
{
static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs) {
codeblock_t *block;
uint64_t a = _cs | ((uint64_t)phys << 32);
@@ -100,11 +95,9 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
return NULL;
block = &codeblock[pages[phys >> 12].head];
while (block)
{
while (block) {
uint64_t block_cmp = block->_cs | ((uint64_t)block->phys << 32);
if (a == block_cmp)
{
if (a == block_cmp) {
if (!((block->status ^ cpu_cur_status) & CPU_STATUS_FLAGS) &&
((block->status & cpu_cur_status & CPU_STATUS_MASK) == (cpu_cur_status & CPU_STATUS_MASK)))
break;
@@ -118,23 +111,18 @@ static inline codeblock_t *codeblock_tree_find(uint32_t phys, uint32_t _cs)
return block;
}
static inline void codeblock_tree_add(codeblock_t *new_block)
{
static inline void codeblock_tree_add(codeblock_t *new_block) {
codeblock_t *block = &codeblock[pages[new_block->phys >> 12].head];
uint64_t a = new_block->_cs | ((uint64_t)new_block->phys << 32);
if (!pages[new_block->phys >> 12].head)
{
if (!pages[new_block->phys >> 12].head) {
pages[new_block->phys >> 12].head = get_block_nr(new_block);
new_block->parent = new_block->left = new_block->right = BLOCK_INVALID;
}
else
{
} else {
codeblock_t *old_block = NULL;
uint64_t old_block_cmp = 0;
while (block)
{
while (block) {
old_block = block;
old_block_cmp = old_block->_cs | ((uint64_t)old_block->phys << 32);
@@ -154,8 +142,7 @@ static inline void codeblock_tree_add(codeblock_t *new_block)
}
}
static inline void codeblock_tree_delete(codeblock_t *block)
{
static inline void codeblock_tree_delete(codeblock_t *block) {
uint16_t parent_nr = block->parent;
codeblock_t *parent;
@@ -164,13 +151,11 @@ static inline void codeblock_tree_delete(codeblock_t *block)
else
parent = NULL;
if (!block->left && !block->right)
{
if (!block->left && !block->right) {
/*Easy case - remove from parent*/
if (!parent)
pages[block->phys >> 12].head = BLOCK_INVALID;
else
{
else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
@@ -179,59 +164,43 @@ static inline void codeblock_tree_delete(codeblock_t *block)
parent->right = BLOCK_INVALID;
}
return;
}
else if (!block->left)
{
} else if (!block->left) {
/*Only right node*/
if (!parent_nr)
{
if (!parent_nr) {
pages[block->phys >> 12].head = block->right;
codeblock[pages[block->phys >> 12].head].parent = BLOCK_INVALID;
}
else
{
} else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
{
if (parent->left == block_nr) {
parent->left = block->right;
codeblock[parent->left].parent = parent_nr;
}
if (parent->right == block_nr)
{
if (parent->right == block_nr) {
parent->right = block->right;
codeblock[parent->right].parent = parent_nr;
}
}
return;
}
else if (!block->right)
{
} else if (!block->right) {
/*Only left node*/
if (!parent_nr)
{
if (!parent_nr) {
pages[block->phys >> 12].head = block->left;
codeblock[pages[block->phys >> 12].head].parent = BLOCK_INVALID;
}
else
{
} else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
{
if (parent->left == block_nr) {
parent->left = block->left;
codeblock[parent->left].parent = parent_nr;
}
if (parent->right == block_nr)
{
if (parent->right == block_nr) {
parent->right = block->left;
codeblock[parent->right].parent = parent_nr;
}
}
return;
}
else
{
} else {
/*Difficult case - node has two children. Walk right child to find lowest node*/
codeblock_t *lowest = &codeblock[block->right], *highest;
codeblock_t *old_parent;
@@ -246,8 +215,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
/*Replace deleted node with lowest node*/
if (!parent_nr)
pages[block->phys >> 12].head = lowest_nr;
else
{
else {
uint16_t block_nr = get_block_nr(block);
if (parent->left == block_nr)
@@ -264,10 +232,8 @@ static inline void codeblock_tree_delete(codeblock_t *block)
old_parent->left = BLOCK_INVALID;
highest = &codeblock[lowest->right];
if (!lowest->right)
{
if (lowest_nr != block->right)
{
if (!lowest->right) {
if (lowest_nr != block->right) {
lowest->right = block->right;
codeblock[block->right].parent = lowest_nr;
}
@@ -277,8 +243,7 @@ static inline void codeblock_tree_delete(codeblock_t *block)
while (highest->right)
highest = &codeblock[highest->right];
if (block->right && block->right != lowest_nr)
{
if (block->right && block->right != lowest_nr) {
highest->right = block->right;
codeblock[block->right].parent = get_block_nr(highest);
}
@@ -290,26 +255,20 @@ static inline void codeblock_tree_delete(codeblock_t *block)
void codegen_mark_code_present_multibyte(codeblock_t *block, uint32_t start_pc, int len);
static inline void codegen_mark_code_present(codeblock_t *block, uint32_t start_pc, int len)
{
if (len == 1)
{
if (block->flags & CODEBLOCK_BYTE_MASK)
{
static inline void codegen_mark_code_present(codeblock_t *block, uint32_t start_pc, int len) {
if (len == 1) {
if (block->flags & CODEBLOCK_BYTE_MASK) {
if (!((start_pc ^ block->pc) & ~0x3f)) /*Starts in second page*/
block->page_mask |= ((uint64_t)1 << (start_pc & PAGE_MASK_MASK));
else
block->page_mask2 |= ((uint64_t)1 << (start_pc & PAGE_MASK_MASK));
}
else
{
} else {
if (!((start_pc ^ block->pc) & ~0xfff)) /*Starts in second page*/
block->page_mask |= ((uint64_t)1 << ((start_pc >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK));
else
block->page_mask2 |= ((uint64_t)1 << ((start_pc >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK));
}
}
else
} else
codegen_mark_code_present_multibyte(block, start_pc, len);
}
@@ -328,7 +287,8 @@ void codegen_set_op32();
void codegen_flush();
void codegen_check_flush(struct page_t *page, uint64_t mask, uint32_t phys_addr);
struct ir_data_t;
x86seg *codegen_generate_ea(struct ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc, uint32_t op_32, int stack_offset);
x86seg *codegen_generate_ea(struct ir_data_t *ir, x86seg *op_ea_seg, uint32_t fetchdat, int op_ssegs, uint32_t *op_pc,
uint32_t op_32, int stack_offset);
void codegen_check_seg_read(codeblock_t *block, struct ir_data_t *ir, x86seg *seg);
void codegen_check_seg_write(codeblock_t *block, struct ir_data_t *ir, x86seg *seg);
@@ -359,8 +319,7 @@ extern void (*codegen_timing_block_start)();
extern void (*codegen_timing_block_end)();
extern int (*codegen_timing_jump_cycles)();
typedef struct codegen_timing_t
{
typedef struct codegen_timing_t {
void (*start)();
void (*prefix)(uint8_t prefix, uint32_t fetchdat);
void (*opcode)(uint8_t opcode, uint32_t fetchdat, int op_32, uint32_t op_pc);

4
includes/private/codegen/codegen_accumulate.h
View File

@@ -1,8 +1,7 @@
#ifndef _CODEGEN_ACCUMULATE_H_
#define _CODEGEN_ACCUMULATE_H_
enum
{
enum {
ACCREG_ins = 0,
ACCREG_cycles = 1,
@@ -15,5 +14,4 @@ void codegen_accumulate(int acc_reg, int delta);
void codegen_accumulate_flush(struct ir_data_t *ir);
void codegen_accumulate_reset();
#endif /* _CODEGEN_ACCUMULATE_H_ */

3
includes/private/codegen/codegen_backend.h
View File

@@ -31,8 +31,7 @@ extern const uOpFn uop_handlers[];
/*Register will not be preserved across function calls*/
#define HOST_REG_FLAG_VOLATILE (1 << 0)
typedef struct host_reg_def_t
{
typedef struct host_reg_def_t {
int reg;
int flags;
} host_reg_def_t;

1
includes/private/codegen/codegen_backend_arm.h
View File

@@ -26,5 +26,4 @@ void host_arm_nop(codeblock_t *block);
void codegen_alloc(codeblock_t *block, int size);
#endif /* _CODEGEN_BACKEND_ARM_H_ */

2
includes/private/codegen/codegen_backend_arm64.h
View File

@@ -14,7 +14,6 @@
#define BLOCK_MAX 0x3c0
void host_arm64_BLR(codeblock_t *block, int addr_reg);
void host_arm64_CBNZ(codeblock_t *block, int reg, uintptr_t dest);
void host_arm64_MOVK_IMM(codeblock_t *block, int reg, uint32_t imm_data);
@@ -33,5 +32,4 @@ void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
uint32_t host_arm64_find_imm(uint32_t data);
#endif /* _CODEGEN_BACKEND_ARM64_H_ */

1
includes/private/codegen/codegen_backend_arm64_defs.h
View File

@@ -137,5 +137,4 @@ extern void *codegen_fp_round_quad;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
#endif /* _CODEGEN_BACKEND_ARM64_DEFS_H_ */

3
includes/private/codegen/codegen_backend_arm64_ops.h
View File

@@ -254,17 +254,14 @@ void host_arm64_call(codeblock_t *block, void *dst_addr);
void host_arm64_jump(codeblock_t *block, uintptr_t dst_addr);
void host_arm64_mov_imm(codeblock_t *block, int reg, uint32_t imm_data);
#define in_range7_x(offset) (((offset) >= -0x200) && ((offset) < (0x200)) && !((offset)&7))
#define in_range12_b(offset) (((offset) >= 0) && ((offset) < 0x1000))
#define in_range12_h(offset) (((offset) >= 0) && ((offset) < 0x2000) && !((offset)&1))
#define in_range12_w(offset) (((offset) >= 0) && ((offset) < 0x4000) && !((offset)&3))
#define in_range12_q(offset) (((offset) >= 0) && ((offset) < 0x8000) && !((offset)&7))
void codegen_direct_read_8(codeblock_t *block, int host_reg, void *p);
void codegen_alloc(codeblock_t *block, int size);
#endif /* _CODEGEN_BACKEND_ARM64_OPS_H_ */

5
includes/private/codegen/codegen_backend_arm_defs.h
View File

@@ -66,8 +66,8 @@
#define REG_MASK_LR (1 << REG_LR)
#define REG_MASK_PC (1 << REG_PC)
#define REG_MASK_LOCAL (REG_MASK_R4 | REG_MASK_R5 | REG_MASK_R6 | REG_MASK_R7 | \
REG_MASK_R8 | REG_MASK_R9 | REG_MASK_R10 | REG_MASK_R11)
#define REG_MASK_LOCAL \
(REG_MASK_R4 | REG_MASK_R5 | REG_MASK_R6 | REG_MASK_R7 | REG_MASK_R8 | REG_MASK_R9 | REG_MASK_R10 | REG_MASK_R11)
#define CODEGEN_HOST_REGS 7
#define CODEGEN_HOST_FP_REGS 8
@@ -91,5 +91,4 @@ extern void *codegen_fp_round;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
#endif /* _CODEGEN_BACKEND_ARM_DEFS_H_ */

4
includes/private/codegen/codegen_backend_arm_ops.h
View File

@@ -105,7 +105,8 @@ void host_arm_ORR_IMM_cond(codeblock_t *block, uint32_t cond, int dst_reg, int s
void host_arm_ORR_REG_LSL_cond(codeblock_t *block, uint32_t cond, int dst_reg, int src_reg_n, int src_reg_m, int shift);
#define host_arm_ORR_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_AL, dst_reg, src_reg, imm)
#define host_arm_ORR_REG_LSL(block, dst_reg, src_reg_a, src_reg_b, shift) host_arm_ORR_REG_LSL_cond(block, COND_AL, dst_reg, src_reg_a, src_reg_b, shift)
#define host_arm_ORR_REG_LSL(block, dst_reg, src_reg_a, src_reg_b, shift) \
host_arm_ORR_REG_LSL_cond(block, COND_AL, dst_reg, src_reg_a, src_reg_b, shift)
#define host_arm_ORRCC_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_CC, dst_reg, src_reg, imm)
#define host_arm_ORREQ_IMM(block, dst_reg, src_reg, imm) host_arm_ORR_IMM_cond(block, COND_EQ, dst_reg, src_reg, imm)
@@ -254,5 +255,4 @@ void host_arm_VZIP_D8(codeblock_t *block, int d_reg, int m_reg);
void host_arm_VZIP_D16(codeblock_t *block, int d_reg, int m_reg);
void host_arm_VZIP_D32(codeblock_t *block, int d_reg, int m_reg);
#endif /* _CODEGEN_BACKEND_ARM_OPS_H_ */

1
includes/private/codegen/codegen_backend_x86-64.h
View File

@@ -16,5 +16,4 @@
#define CODEGEN_BACKEND_HAS_MOV_IMM
#endif /* _CODEGEN_BACKEND_X86_64_H_ */

1
includes/private/codegen/codegen_backend_x86-64_defs.h
View File

@@ -70,5 +70,4 @@ extern void *codegen_mem_store_double;
extern void *codegen_gpf_rout;
extern void *codegen_exit_rout;
#endif /* _CODEGEN_BACKEND_X86_64_DEFS_H_ */

1
includes/private/codegen/codegen_backend_x86-64_ops.h
View File

@@ -198,5 +198,4 @@ void host_x86_XOR8_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR16_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_XOR32_REG_REG(codeblock_t *block, int dst_reg, int src_reg);
#endif /* _CODEGEN_BACKEND_X86_64_OPS_H_ */

52
includes/private/codegen/codegen_backend_x86-64_ops_helpers.h
View File

@@ -3,29 +3,23 @@
#define JMP_LEN_BYTES 5
static inline void codegen_addbyte(codeblock_t *block, uint8_t val)
{
if (block_pos >= BLOCK_MAX)
{
static inline void codegen_addbyte(codeblock_t *block, uint8_t val) {
if (block_pos >= BLOCK_MAX) {
fatal("codegen_addbyte over! %i\n", block_pos);
// CPU_BLOCK_END();
}
block_write_data[block_pos++] = val;
}
static inline void codegen_addbyte2(codeblock_t *block, uint8_t vala, uint8_t valb)
{
if (block_pos > (BLOCK_MAX-2))
{
static inline void codegen_addbyte2(codeblock_t *block, uint8_t vala, uint8_t valb) {
if (block_pos > (BLOCK_MAX - 2)) {
fatal("codegen_addbyte2 over! %i\n", block_pos);
CPU_BLOCK_END();
}
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
}
static inline void codegen_addbyte3(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc)
{
if (block_pos > (BLOCK_MAX-3))
{
static inline void codegen_addbyte3(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc) {
if (block_pos > (BLOCK_MAX - 3)) {
fatal("codegen_addbyte3 over! %i\n", block_pos);
CPU_BLOCK_END();
}
@@ -33,10 +27,8 @@ static inline void codegen_addbyte3(codeblock_t *block, uint8_t vala, uint8_t va
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
}
static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald)
{
if (block_pos > (BLOCK_MAX-4))
{
static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald) {
if (block_pos > (BLOCK_MAX - 4)) {
fatal("codegen_addbyte4 over! %i\n", block_pos);
CPU_BLOCK_END();
}
@@ -46,10 +38,8 @@ static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t va
block_write_data[block_pos++] = vald;
}
static inline void codegen_addword(codeblock_t *block, uint16_t val)
{
if (block_pos > (BLOCK_MAX-2))
{
static inline void codegen_addword(codeblock_t *block, uint16_t val) {
if (block_pos > (BLOCK_MAX - 2)) {
fatal("codegen_addword over! %i\n", block_pos);
CPU_BLOCK_END();
}
@@ -57,10 +47,8 @@ static inline void codegen_addword(codeblock_t *block, uint16_t val)
block_pos += 2;
}
static inline void codegen_addlong(codeblock_t *block, uint32_t val)
{
if (block_pos > (BLOCK_MAX-4))
{
static inline void codegen_addlong(codeblock_t *block, uint32_t val) {
if (block_pos > (BLOCK_MAX - 4)) {
fatal("codegen_addlong over! %i\n", block_pos);
CPU_BLOCK_END();
}
@@ -68,10 +56,8 @@ static inline void codegen_addlong(codeblock_t *block, uint32_t val)
block_pos += 4;
}
static inline void codegen_addquad(codeblock_t *block, uint64_t val)
{
if (block_pos > (BLOCK_MAX-8))
{
static inline void codegen_addquad(codeblock_t *block, uint64_t val) {
if (block_pos > (BLOCK_MAX - 8)) {
fatal("codegen_addquad over! %i\n", block_pos);
CPU_BLOCK_END();
}
@@ -79,10 +65,8 @@ static inline void codegen_addquad(codeblock_t *block, uint64_t val)
block_pos += 8;
}
static inline void codegen_alloc_bytes(codeblock_t *block, int size)
{
if (block_pos > ((BLOCK_MAX - size) - JMP_LEN_BYTES))
{
static inline void codegen_alloc_bytes(codeblock_t *block, int size) {
if (block_pos > ((BLOCK_MAX - size) - JMP_LEN_BYTES)) {
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
@@ -97,12 +81,10 @@ static inline void codegen_alloc_bytes(codeblock_t *block, int size)
}
}
static inline int is_imm8(uint32_t imm_data)
{
static inline int is_imm8(uint32_t imm_data) {
if (imm_data <= 0x7f || imm_data >= 0xffffff80)
return 1;
return 0;
}
#endif /* _CODEGEN_BACKEND_X86_64_OPS_HELPERS_H_ */

7
includes/private/codegen/codegen_backend_x86-64_ops_sse.h
View File

@@ -36,11 +36,13 @@ void host_x86_MOVD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg
void host_x86_MOVD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_ABS_XREG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift,
int src_reg);
void host_x86_MOVQ_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVQ_BASE_OFFSET_XREG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOVQ_XREG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b,
int shift);
void host_x86_MOVQ_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVQ_XREG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
@@ -116,5 +118,4 @@ void host_x86_SUBSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_UNPCKLPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
#endif /* _CODEGEN_BACKEND_X86_64_OPS_SSE_H_ */

1
includes/private/codegen/codegen_backend_x86.h
View File

@@ -16,5 +16,4 @@
#define CODEGEN_BACKEND_HAS_MOV_IMM
#endif /* _CODEGEN_BACKEND_X86_H_ */

1
includes/private/codegen/codegen_backend_x86_ops.h
View File

@@ -197,5 +197,4 @@ void host_x86_XOR8_REG_IMM(codeblock_t *block, int dst_reg, uint8_t imm_data);
void host_x86_XOR16_REG_IMM(codeblock_t *block, int dst_reg, uint16_t imm_data);
void host_x86_XOR32_REG_IMM(codeblock_t *block, int dst_reg, uint32_t imm_data);
#endif /* _CODEGEN_BACKEND_X86_OPS_H_ */

1
includes/private/codegen/codegen_backend_x86_ops_fpu.h
View File

@@ -7,5 +7,4 @@ void host_x87_FLDCW(codeblock_t *block, void *p);
void host_x87_FLDd_BASE(codeblock_t *block, int base_reg);
void host_x87_FSTPd_BASE(codeblock_t *block, int base_reg);
#endif /* _CODEGEN_BACKEND_X86_OPS_FPU_H_ */

31
includes/private/codegen/codegen_backend_x86_ops_helpers.h
View File

@@ -3,29 +3,25 @@
#define JMP_LEN_BYTES 5
static inline void codegen_addbyte(codeblock_t *block, uint8_t val)
{
static inline void codegen_addbyte(codeblock_t *block, uint8_t val) {
if (block_pos >= BLOCK_MAX)
fatal("codegen_addbyte over! %i\n", block_pos);
block_write_data[block_pos++] = val;
}
static inline void codegen_addbyte2(codeblock_t *block, uint8_t vala, uint8_t valb)
{
static inline void codegen_addbyte2(codeblock_t *block, uint8_t vala, uint8_t valb) {
if (block_pos > (BLOCK_MAX - 2))
fatal("codegen_addbyte2 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
}
static inline void codegen_addbyte3(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc)
{
static inline void codegen_addbyte3(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc) {
if (block_pos > (BLOCK_MAX - 3))
fatal("codegen_addbyte3 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
block_write_data[block_pos++] = valb;
block_write_data[block_pos++] = valc;
}
static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald)
{
static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t valb, uint8_t valc, uint8_t vald) {
if (block_pos > (BLOCK_MAX - 4))
fatal("codegen_addbyte4 over! %i\n", block_pos);
block_write_data[block_pos++] = vala;
@@ -34,32 +30,28 @@ static inline void codegen_addbyte4(codeblock_t *block, uint8_t vala, uint8_t va
block_write_data[block_pos++] = vald;
}
static inline void codegen_addword(codeblock_t *block, uint16_t val)
{
static inline void codegen_addword(codeblock_t *block, uint16_t val) {
if (block_pos > (BLOCK_MAX - 2))
fatal("codegen_addword over! %i\n", block_pos);
*(uint16_t *)&block_write_data[block_pos] = val;
block_pos += 2;
}
static inline void codegen_addlong(codeblock_t *block, uint32_t val)
{
static inline void codegen_addlong(codeblock_t *block, uint32_t val) {
if (block_pos > (BLOCK_MAX - 4))
fatal("codegen_addlong over! %i\n", block_pos);
*(uint32_t *)&block_write_data[block_pos] = val;
block_pos += 4;
}
static inline void codegen_addquad(codeblock_t *block, uint64_t val)
{
static inline void codegen_addquad(codeblock_t *block, uint64_t val) {
if (block_pos > (BLOCK_MAX - 8))
fatal("codegen_addquad over! %i\n", block_pos);
*(uint64_t *)&block_write_data[block_pos] = val;
block_pos += 8;
}
static void codegen_allocate_new_block(codeblock_t *block)
{
static void codegen_allocate_new_block(codeblock_t *block) {
/*Current block is full. Allocate a new block*/
struct mem_block_t *new_block = codegen_allocator_allocate(block->head_mem_block, get_block_nr(block));
uint8_t *new_ptr = codeblock_allocator_get_ptr(new_block);
@@ -73,18 +65,15 @@ static void codegen_allocate_new_block(codeblock_t *block)
block_write_data = new_ptr;
}
static inline void codegen_alloc_bytes(codeblock_t *block, int size)
{
static inline void codegen_alloc_bytes(codeblock_t *block, int size) {
if (block_pos > ((BLOCK_MAX - size) - JMP_LEN_BYTES))
codegen_allocate_new_block(block);
}
static inline int is_imm8(uint32_t imm_data)
{
static inline int is_imm8(uint32_t imm_data) {
if (imm_data <= 0x7f || imm_data >= 0xffffff80)
return 1;
return 0;
}
#endif /* _CODEGEN_BACKEND_X86_OPS_HELPERS_H_ */

7
includes/private/codegen/codegen_backend_x86_ops_sse.h
View File

@@ -36,13 +36,15 @@ void host_x86_MOVD_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg
void host_x86_MOVD_XREG_REG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_MOVQ_ABS_XREG(codeblock_t *block, void *p, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift, int src_reg);
void host_x86_MOVQ_ABS_REG_REG_SHIFT_XREG(codeblock_t *block, uint32_t addr, int src_reg_a, int src_reg_b, int shift,
int src_reg);
void host_x86_MOVQ_BASE_INDEX_XREG(codeblock_t *block, int base_reg, int idx_reg, int src_reg);
void host_x86_MOVQ_BASE_OFFSET_XREG(codeblock_t *block, int base_reg, int offset, int src_reg);
void host_x86_MOVQ_STACK_OFFSET_XREG(codeblock_t *block, int offset, int src_reg);
void host_x86_MOVQ_XREG_ABS(codeblock_t *block, int dst_reg, void *p);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b, int shift);
void host_x86_MOVQ_XREG_ABS_REG_REG_SHIFT(codeblock_t *block, int dst_reg, uint32_t addr, int src_reg_a, int src_reg_b,
int shift);
void host_x86_MOVQ_XREG_BASE_INDEX(codeblock_t *block, int dst_reg, int base_reg, int idx_reg);
void host_x86_MOVQ_XREG_BASE_OFFSET(codeblock_t *block, int dst_reg, int base_reg, int offset);
void host_x86_MOVQ_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
@@ -113,5 +115,4 @@ void host_x86_SUBSD_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
void host_x86_UNPCKLPS_XREG_XREG(codeblock_t *block, int dst_reg, int src_reg);
#endif /* _CODEGEN_BACKEND_X86_OPS_SSE_H_ */

1
includes/private/codegen/codegen_ir.h
View File

@@ -8,5 +8,4 @@ ir_data_t *codegen_ir_init();
void codegen_ir_set_unroll(int count, int start, int first_instruction);
void codegen_ir_compile(ir_data_t *ir, codeblock_t *block);
#endif /* _CODEGEN_IR_H_ */

180
includes/private/codegen/codegen_ir_defs.h
View File

@@ -32,7 +32,6 @@
at compile time.*/
#define UOP_TYPE_JUMP_DEST (1 << 25)
#define UOP_LOAD_FUNC_ARG_0 (UOP_TYPE_PARAMS_REGS | 0x00)
#define UOP_LOAD_FUNC_ARG_1 (UOP_TYPE_PARAMS_REGS | 0x01)
#define UOP_LOAD_FUNC_ARG_2 (UOP_TYPE_PARAMS_REGS | 0x02)
@@ -160,40 +159,55 @@
#define UOP_ROR_IMM (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | 0x59)
/*UOP_CMP_IMM_JZ_DEST - if (src_reg_a == imm_data) then jump to ptr*/
#define UOP_CMP_IMM_JZ_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x60 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_IMM_JZ_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x60 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_IMM_JNZ_DEST - if (src_reg_a != imm_data) then jump to ptr*/
#define UOP_CMP_IMM_JNZ_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x61 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_IMM_JNZ_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x61 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JB_DEST - if (src_reg_a < src_reg_b) then jump to ptr*/
#define UOP_CMP_JB_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x62 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JB_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x62 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNB_DEST - if (src_reg_a >= src_reg_b) then jump to ptr*/
#define UOP_CMP_JNB_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x63 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNB_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x63 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JO_DEST - if (src_reg_a < src_reg_b) then jump to ptr*/
#define UOP_CMP_JO_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x64 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JO_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x64 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNO_DEST - if (src_reg_a >= src_reg_b) then jump to ptr*/
#define UOP_CMP_JNO_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x65 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNO_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x65 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JZ_DEST - if (src_reg_a == src_reg_b) then jump to ptr*/
#define UOP_CMP_JZ_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x66 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JZ_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x66 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNZ_DEST - if (src_reg_a != src_reg_b) then jump to ptr*/
#define UOP_CMP_JNZ_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x67 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNZ_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x67 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JL_DEST - if (signed)(src_reg_a < src_reg_b) then jump to ptr*/
#define UOP_CMP_JL_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x68 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JL_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x68 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNL_DEST - if (signed)(src_reg_a >= src_reg_b) then jump to ptr*/
#define UOP_CMP_JNL_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x69 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNL_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x69 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JBE_DEST - if (src_reg_a <= src_reg_b) then jump to ptr*/
#define UOP_CMP_JBE_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6a | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JBE_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6a | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNBE_DEST - if (src_reg_a > src_reg_b) then jump to ptr*/
#define UOP_CMP_JNBE_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6b | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNBE_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6b | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JLE_DEST - if (signed)(src_reg_a <= src_reg_b) then jump to ptr*/
#define UOP_CMP_JLE_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6c | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JLE_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6c | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_CMP_JNLE_DEST - if (signed)(src_reg_a > src_reg_b) then jump to ptr*/
#define UOP_CMP_JNLE_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6d | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_CMP_JNLE_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x6d | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_TEST_JNS_DEST - if (src_reg_a positive) then jump to ptr*/
#define UOP_TEST_JNS_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x70 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_TEST_JNS_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x70 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_TEST_JS_DEST - if (src_reg_a positive) then jump to ptr*/
#define UOP_TEST_JS_DEST (UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x71 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
#define UOP_TEST_JS_DEST \
(UOP_TYPE_PARAMS_REGS | UOP_TYPE_PARAMS_IMM | UOP_TYPE_PARAMS_POINTER | 0x71 | UOP_TYPE_ORDER_BARRIER | UOP_TYPE_JUMP)
/*UOP_FP_ENTER - must be called before any FPU register accessed*/
#define UOP_FP_ENTER (UOP_TYPE_PARAMS_IMM | 0x80 | UOP_TYPE_BARRIER)
@@ -332,8 +346,7 @@
#define UOP_MASK 0xffff
typedef struct uop_t
{
typedef struct uop_t {
uint32_t type;
ir_reg_t dest_reg_a;
ir_reg_t src_reg_a;
@@ -351,15 +364,13 @@ typedef struct uop_t
#define UOP_NR_MAX 4096
typedef struct ir_data_t
{
typedef struct ir_data_t {
uop_t uops[UOP_NR_MAX];
int wr_pos;
struct codeblock_t *block;
} ir_data_t;
static inline uop_t *uop_alloc(ir_data_t *ir, uint32_t uop_type)
{
static inline uop_t *uop_alloc(ir_data_t *ir, uint32_t uop_type) {
uop_t *uop;
if (ir->wr_pos >= UOP_NR_MAX)
@@ -383,15 +394,13 @@ static inline uop_t *uop_alloc(ir_data_t *ir, uint32_t uop_type)
return uop;
}
static inline void uop_set_jump_dest(ir_data_t *ir, int jump_uop)
{
static inline void uop_set_jump_dest(ir_data_t *ir, int jump_uop) {
uop_t *uop = &ir->uops[jump_uop];
uop->jump_dest_uop = ir->wr_pos;
}
static inline int uop_gen(uint32_t uop_type, ir_data_t *ir)
{
static inline int uop_gen(uint32_t uop_type, ir_data_t *ir) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -399,8 +408,7 @@ static inline int uop_gen(uint32_t uop_type, ir_data_t *ir)
return ir->wr_pos - 1;
}
static inline int uop_gen_reg_src1(uint32_t uop_type, ir_data_t *ir, int src_reg_a)
{
static inline int uop_gen_reg_src1(uint32_t uop_type, ir_data_t *ir, int src_reg_a) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -409,16 +417,14 @@ static inline int uop_gen_reg_src1(uint32_t uop_type, ir_data_t *ir, int src_reg
return ir->wr_pos - 1;
}
static inline void uop_gen_reg_src1_arg(uint32_t uop_type, ir_data_t *ir, int arg, int src_reg_a)
{
static inline void uop_gen_reg_src1_arg(uint32_t uop_type, ir_data_t *ir, int arg, int src_reg_a) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->src_reg_a = codegen_reg_read(src_reg_a);
}
static inline int uop_gen_reg_src1_imm(uint32_t uop_type, ir_data_t *ir, int src_reg, uint32_t imm)
{
static inline int uop_gen_reg_src1_imm(uint32_t uop_type, ir_data_t *ir, int src_reg, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -428,8 +434,7 @@ static inline int uop_gen_reg_src1_imm(uint32_t uop_type, ir_data_t *ir, int src
return ir->wr_pos - 1;
}
static inline void uop_gen_reg_dst_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, uint32_t imm)
{
static inline void uop_gen_reg_dst_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -437,8 +442,7 @@ static inline void uop_gen_reg_dst_imm(uint32_t uop_type, ir_data_t *ir, int des
uop->imm_data = imm;
}
static inline void uop_gen_reg_dst_pointer(uint32_t uop_type, ir_data_t *ir, int dest_reg, void *p)
{
static inline void uop_gen_reg_dst_pointer(uint32_t uop_type, ir_data_t *ir, int dest_reg, void *p) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -446,8 +450,7 @@ static inline void uop_gen_reg_dst_pointer(uint32_t uop_type, ir_data_t *ir, int
uop->p = p;
}
static inline void uop_gen_reg_dst_src1(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg)
{
static inline void uop_gen_reg_dst_src1(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -455,8 +458,7 @@ static inline void uop_gen_reg_dst_src1(uint32_t uop_type, ir_data_t *ir, int de
uop->dest_reg_a = codegen_reg_write(dest_reg, ir->wr_pos - 1);
}
static inline void uop_gen_reg_dst_src1_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, uint32_t imm)
{
static inline void uop_gen_reg_dst_src1_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -465,8 +467,7 @@ static inline void uop_gen_reg_dst_src1_imm(uint32_t uop_type, ir_data_t *ir, in
uop->imm_data = imm;
}
static inline void uop_gen_reg_dst_src2(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b)
{
static inline void uop_gen_reg_dst_src2(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -475,8 +476,8 @@ static inline void uop_gen_reg_dst_src2(uint32_t uop_type, ir_data_t *ir, int de
uop->dest_reg_a = codegen_reg_write(dest_reg, ir->wr_pos - 1);
}
static inline void uop_gen_reg_dst_src2_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b, uint32_t imm)
{
static inline void uop_gen_reg_dst_src2_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b,
uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -486,8 +487,8 @@ static inline void uop_gen_reg_dst_src2_imm(uint32_t uop_type, ir_data_t *ir, in
uop->imm_data = imm;
}
static inline void uop_gen_reg_dst_src3(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b, int src_reg_c)
{
static inline void uop_gen_reg_dst_src3(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg_a, int src_reg_b,
int src_reg_c) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -497,8 +498,7 @@ static inline void uop_gen_reg_dst_src3(uint32_t uop_type, ir_data_t *ir, int de
uop->dest_reg_a = codegen_reg_write(dest_reg, ir->wr_pos - 1);
}
static inline void uop_gen_reg_dst_src_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg, uint32_t imm)
{
static inline void uop_gen_reg_dst_src_imm(uint32_t uop_type, ir_data_t *ir, int dest_reg, int src_reg, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -507,8 +507,7 @@ static inline void uop_gen_reg_dst_src_imm(uint32_t uop_type, ir_data_t *ir, int
uop->imm_data = imm;
}
static inline int uop_gen_reg_src2(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b)
{
static inline int uop_gen_reg_src2(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -518,8 +517,7 @@ static inline int uop_gen_reg_src2(uint32_t uop_type, ir_data_t *ir, int src_reg
return ir->wr_pos - 1;
}
static inline void uop_gen_reg_src2_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, uint32_t imm)
{
static inline void uop_gen_reg_src2_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -528,8 +526,7 @@ static inline void uop_gen_reg_src2_imm(uint32_t uop_type, ir_data_t *ir, int sr
uop->imm_data = imm;
}
static inline void uop_gen_reg_src3(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, int src_reg_c)
{
static inline void uop_gen_reg_src3(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, int src_reg_c) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -538,8 +535,8 @@ static inline void uop_gen_reg_src3(uint32_t uop_type, ir_data_t *ir, int src_re
uop->src_reg_c = codegen_reg_read(src_reg_c);
}
static inline void uop_gen_reg_src3_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, int src_reg_c, uint32_t imm)
{
static inline void uop_gen_reg_src3_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, int src_reg_c,
uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -549,24 +546,21 @@ static inline void uop_gen_reg_src3_imm(uint32_t uop_type, ir_data_t *ir, int sr
uop->imm_data = imm;
}
static inline void uop_gen_imm(uint32_t uop_type, ir_data_t *ir, uint32_t imm)
{
static inline void uop_gen_imm(uint32_t uop_type, ir_data_t *ir, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->imm_data = imm;
}
static inline void uop_gen_pointer(uint32_t uop_type, ir_data_t *ir, void *p)
{
static inline void uop_gen_pointer(uint32_t uop_type, ir_data_t *ir, void *p) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
uop->p = p;
}
static inline void uop_gen_pointer_imm(uint32_t uop_type, ir_data_t *ir, void *p, uint32_t imm)
{
static inline void uop_gen_pointer_imm(uint32_t uop_type, ir_data_t *ir, void *p, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -574,8 +568,7 @@ static inline void uop_gen_pointer_imm(uint32_t uop_type, ir_data_t *ir, void *p
uop->imm_data = imm;
}
static inline void uop_gen_reg_src_pointer(uint32_t uop_type, ir_data_t *ir, int src_reg_a, void *p)
{
static inline void uop_gen_reg_src_pointer(uint32_t uop_type, ir_data_t *ir, int src_reg_a, void *p) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -583,8 +576,7 @@ static inline void uop_gen_reg_src_pointer(uint32_t uop_type, ir_data_t *ir, int
uop->p = p;
}
static inline void uop_gen_reg_src_pointer_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, void *p, uint32_t imm)
{
static inline void uop_gen_reg_src_pointer_imm(uint32_t uop_type, ir_data_t *ir, int src_reg_a, void *p, uint32_t imm) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -593,8 +585,7 @@ static inline void uop_gen_reg_src_pointer_imm(uint32_t uop_type, ir_data_t *ir,
uop->imm_data = imm;
}
static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, void *p)
{
static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, int src_reg_a, int src_reg_b, void *p) {
uop_t *uop = uop_alloc(ir, uop_type);
uop->type = uop_type;
@@ -609,7 +600,8 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
#define uop_ADD(ir, dst_reg, src_reg_a, src_reg_b) uop_gen_reg_dst_src2(UOP_ADD, ir, dst_reg, src_reg_a, src_reg_b)
#define uop_ADD_IMM(ir, dst_reg, src_reg, imm) uop_gen_reg_dst_src_imm(UOP_ADD_IMM, ir, dst_reg, src_reg, imm)
#define uop_ADD_LSHIFT(ir, dst_reg, src_reg_a, src_reg_b, shift) uop_gen_reg_dst_src2_imm(UOP_ADD_LSHIFT, ir, dst_reg, src_reg_a, src_reg_b, shift)
#define uop_ADD_LSHIFT(ir, dst_reg, src_reg_a, src_reg_b, shift) \
uop_gen_reg_dst_src2_imm(UOP_ADD_LSHIFT, ir, dst_reg, src_reg_a, src_reg_b, shift)
#define uop_AND(ir, dst_reg, src_reg_a, src_reg_b) uop_gen_reg_dst_src2(UOP_AND, ir, dst_reg, src_reg_a, src_reg_b)
#define uop_AND_IMM(ir, dst_reg, src_reg, imm) uop_gen_reg_dst_src_imm(UOP_AND_IMM, ir, dst_reg, src_reg, imm)
#define uop_ANDN(ir, dst_reg, src_reg_a, src_reg_b) uop_gen_reg_dst_src2(UOP_ANDN, ir, dst_reg, src_reg_a, src_reg_b)
@@ -667,8 +659,20 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
#define uop_FSQRT(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_FSQRT, ir, dst_reg, src_reg)
#define uop_FTST(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_FTST, ir, dst_reg, src_reg)
#define uop_FP_ENTER(ir) do { if (!codegen_fpu_entered) uop_gen_imm(UOP_FP_ENTER, ir, cpu_state.oldpc); codegen_fpu_entered = 1; codegen_mmx_entered = 0; } while (0)
#define uop_MMX_ENTER(ir) do { if (!codegen_mmx_entered) uop_gen_imm(UOP_MMX_ENTER, ir, cpu_state.oldpc); codegen_mmx_entered = 1; codegen_fpu_entered = 0; } while (0)
#define uop_FP_ENTER(ir) \
do { \
if (!codegen_fpu_entered) \
uop_gen_imm(UOP_FP_ENTER, ir, cpu_state.oldpc); \
codegen_fpu_entered = 1; \
codegen_mmx_entered = 0; \
} while (0)
#define uop_MMX_ENTER(ir) \
do { \
if (!codegen_mmx_entered) \
uop_gen_imm(UOP_MMX_ENTER, ir, cpu_state.oldpc); \
codegen_mmx_entered = 1; \
codegen_fpu_entered = 0; \
} while (0)
#define uop_JMP(ir, p) uop_gen_pointer(UOP_JMP, ir, p)
#define uop_JMP_DEST(ir) uop_gen(UOP_JMP_DEST, ir)
@@ -676,18 +680,26 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
#define uop_LOAD_SEG(ir, p, src_reg) uop_gen_reg_src_pointer(UOP_LOAD_SEG, ir, src_reg, p)
#define uop_MEM_LOAD_ABS(ir, dst_reg, seg_reg, imm) uop_gen_reg_dst_src_imm(UOP_MEM_LOAD_ABS, ir, dst_reg, seg_reg, imm)
#define uop_MEM_LOAD_REG(ir, dst_reg, seg_reg, addr_reg) uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_REG, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_LOAD_REG_OFFSET(ir, dst_reg, seg_reg, addr_reg, offset) uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_REG, ir, dst_reg, seg_reg, addr_reg, offset)
#define uop_MEM_LOAD_SINGLE(ir, dst_reg, seg_reg, addr_reg) uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_SINGLE, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_LOAD_DOUBLE(ir, dst_reg, seg_reg, addr_reg) uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_DOUBLE, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_LOAD_REG(ir, dst_reg, seg_reg, addr_reg) \
uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_REG, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_LOAD_REG_OFFSET(ir, dst_reg, seg_reg, addr_reg, offset) \
uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_REG, ir, dst_reg, seg_reg, addr_reg, offset)
#define uop_MEM_LOAD_SINGLE(ir, dst_reg, seg_reg, addr_reg) \
uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_SINGLE, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_LOAD_DOUBLE(ir, dst_reg, seg_reg, addr_reg) \
uop_gen_reg_dst_src2_imm(UOP_MEM_LOAD_DOUBLE, ir, dst_reg, seg_reg, addr_reg, 0)
#define uop_MEM_STORE_ABS(ir, seg_reg, imm, src_reg) uop_gen_reg_src2_imm(UOP_MEM_STORE_ABS, ir, seg_reg, src_reg, imm)
#define uop_MEM_STORE_REG(ir, seg_reg, addr_reg, src_reg) uop_gen_reg_src3_imm(UOP_MEM_STORE_REG, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MEM_STORE_REG_OFFSET(ir, seg_reg, addr_reg, offset, src_reg) uop_gen_reg_src3_imm(UOP_MEM_STORE_REG, ir, seg_reg, addr_reg, src_reg, offset)
#define uop_MEM_STORE_REG(ir, seg_reg, addr_reg, src_reg) \
uop_gen_reg_src3_imm(UOP_MEM_STORE_REG, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MEM_STORE_REG_OFFSET(ir, seg_reg, addr_reg, offset, src_reg) \
uop_gen_reg_src3_imm(UOP_MEM_STORE_REG, ir, seg_reg, addr_reg, src_reg, offset)
#define uop_MEM_STORE_IMM_8(ir, seg_reg, addr_reg, imm) uop_gen_reg_src2_imm(UOP_MEM_STORE_IMM_8, ir, seg_reg, addr_reg, imm)
#define uop_MEM_STORE_IMM_16(ir, seg_reg, addr_reg, imm) uop_gen_reg_src2_imm(UOP_MEM_STORE_IMM_16, ir, seg_reg, addr_reg, imm)
#define uop_MEM_STORE_IMM_32(ir, seg_reg, addr_reg, imm) uop_gen_reg_src2_imm(UOP_MEM_STORE_IMM_32, ir, seg_reg, addr_reg, imm)
#define uop_MEM_STORE_SINGLE(ir, seg_reg, addr_reg, src_reg) uop_gen_reg_src3_imm(UOP_MEM_STORE_SINGLE, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MEM_STORE_DOUBLE(ir, seg_reg, addr_reg, src_reg) uop_gen_reg_src3_imm(UOP_MEM_STORE_DOUBLE, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MEM_STORE_SINGLE(ir, seg_reg, addr_reg, src_reg) \
uop_gen_reg_src3_imm(UOP_MEM_STORE_SINGLE, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MEM_STORE_DOUBLE(ir, seg_reg, addr_reg, src_reg) \
uop_gen_reg_src3_imm(UOP_MEM_STORE_DOUBLE, ir, seg_reg, addr_reg, src_reg, 0)
#define uop_MOV(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_MOV, ir, dst_reg, src_reg)
#define uop_MOV_IMM(ir, reg, imm) uop_gen_reg_dst_imm(UOP_MOV_IMM, ir, reg, imm)
@@ -698,8 +710,10 @@ static inline void uop_gen_reg_src2_pointer(uint32_t uop_type, ir_data_t *ir, in
#define uop_MOVSX(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_MOVSX, ir, dst_reg, src_reg)
#define uop_MOVZX(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_MOVZX, ir, dst_reg, src_reg)
#define uop_MOV_DOUBLE_INT(ir, dst_reg, src_reg) uop_gen_reg_dst_src1(UOP_MOV_DOUBLE_INT, ir, dst_reg, src_reg)
#define uop_MOV_INT_DOUBLE(ir, dst_reg, src_reg/*, nrc, orc*/) uop_gen_reg_dst_src1(UOP_MOV_INT_DOUBLE, ir, dst_reg, src_reg/*, nrc, orc*/)
#define uop_MOV_INT_DOUBLE_64(ir, dst_reg, src_reg_d, src_reg_q, tag) uop_gen_reg_dst_src3(UOP_MOV_INT_DOUBLE_64, ir, dst_reg, src_reg_d, src_reg_q, tag)
#define uop_MOV_INT_DOUBLE(ir, dst_reg, src_reg /*, nrc, orc*/) \
uop_gen_reg_dst_src1(UOP_MOV_INT_DOUBLE, ir, dst_reg, src_reg /*, nrc, orc*/)
#define uop_MOV_INT_DOUBLE_64(ir, dst_reg, src_reg_d, src_reg_q, tag) \
uop_gen_reg_dst_src3(UOP_MOV_INT_DOUBLE_64, ir, dst_reg, src_reg_d, src_reg_q, tag)
#define uop_NOP_BARRIER(ir) uop_gen(UOP_NOP_BARRIER, ir)

3
includes/private/codegen/codegen_ops.h
View File

@@ -5,7 +5,8 @@
struct ir_data_t;
typedef uint32_t (*RecompOpFn)(codeblock_t *block, struct ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
typedef uint32_t (*RecompOpFn)(codeblock_t *block, struct ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
uint32_t op_pc);
extern RecompOpFn recomp_opcodes[512];
extern RecompOpFn recomp_opcodes_0f[512];

1
includes/private/codegen/codegen_ops_3dnow.h
View File

@@ -17,5 +17,4 @@ uint32_t ropPFSUB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uint32_t ropPFSUBR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPI2FD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_3DNOW_H_ */

2
includes/private/codegen/codegen_ops_arith.h
View File

@@ -57,7 +57,6 @@ uint32_t rop81_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uint32_t rop83_w(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t rop83_l(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropDEC_r16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropDEC_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
@@ -66,5 +65,4 @@ uint32_t ropINC_r32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropINCDEC(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_ARITH_H_ */

1
includes/private/codegen/codegen_ops_branch.h
View File

@@ -71,5 +71,4 @@ uint32_t ropLOOP(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uint32_t ropLOOPE(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropLOOPNE(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_BRANCH_H_ */

1
includes/private/codegen/codegen_ops_fpu_arith.h
View File

@@ -65,5 +65,4 @@ uint32_t ropFCHS(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fet
uint32_t ropFSQRT(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFTST(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_FPU_ARITH_H_ */

1
includes/private/codegen/codegen_ops_fpu_constant.h
View File

@@ -4,5 +4,4 @@
uint32_t ropFLD1(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFLDZ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_FPU_CONSTANT_H_ */

1
includes/private/codegen/codegen_ops_fpu_loadstore.h
View File

@@ -19,5 +19,4 @@ uint32_t ropFISTl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uint32_t ropFISTPl(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropFISTPq(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_FPU_LOADSTORE_H_ */

1
includes/private/codegen/codegen_ops_fpu_misc.h
View File

@@ -14,5 +14,4 @@ uint32_t ropFSTSW_AX(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropFXCH(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_FPU_MISC_H_ */

65
includes/private/codegen/codegen_ops_helpers.h
View File

@@ -4,100 +4,78 @@
#include "386_common.h"
#include "codegen_backend.h"
static inline int LOAD_SP_WITH_OFFSET(ir_data_t *ir, int offset)
{
if (stack32)
{
if (offset)
{
static inline int LOAD_SP_WITH_OFFSET(ir_data_t *ir, int offset) {
if (stack32) {
if (offset) {
uop_ADD_IMM(ir, IREG_eaaddr, IREG_ESP, offset);
return IREG_eaaddr;
}
else
} else
return IREG_ESP;
}
else
{
if (offset)
{
} else {
if (offset) {
uop_ADD_IMM(ir, IREG_eaaddr_W, IREG_SP, offset);
uop_MOVZX(ir, IREG_eaaddr, IREG_eaaddr_W);
return IREG_eaaddr;
}
else
{
} else {
uop_MOVZX(ir, IREG_eaaddr, IREG_SP);
return IREG_eaaddr;
}
}
}
static inline int LOAD_SP(ir_data_t *ir)
{
return LOAD_SP_WITH_OFFSET(ir, 0);
}
static inline int LOAD_SP(ir_data_t *ir) { return LOAD_SP_WITH_OFFSET(ir, 0); }
static inline void ADD_SP(ir_data_t *ir, int offset)
{
static inline void ADD_SP(ir_data_t *ir, int offset) {
if (stack32)
uop_ADD_IMM(ir, IREG_ESP, IREG_ESP, offset);
else
uop_ADD_IMM(ir, IREG_SP, IREG_SP, offset);
}
static inline void SUB_SP(ir_data_t *ir, int offset)
{
static inline void SUB_SP(ir_data_t *ir, int offset) {
if (stack32)
uop_SUB_IMM(ir, IREG_ESP, IREG_ESP, offset);
else
uop_SUB_IMM(ir, IREG_SP, IREG_SP, offset);
}
static inline void fpu_POP(codeblock_t *block, ir_data_t *ir)
{
static inline void fpu_POP(codeblock_t *block, ir_data_t *ir) {
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP + 1);
else
uop_ADD_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 1);
}
static inline void fpu_POP2(codeblock_t *block, ir_data_t *ir)
{
static inline void fpu_POP2(codeblock_t *block, ir_data_t *ir) {
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP + 2);
else
uop_ADD_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 2);
}
static inline void fpu_PUSH(codeblock_t *block, ir_data_t *ir)
{
static inline void fpu_PUSH(codeblock_t *block, ir_data_t *ir) {
if (block->flags & CODEBLOCK_STATIC_TOP)
uop_MOV_IMM(ir, IREG_FPU_TOP, cpu_state.TOP - 1);
else
uop_SUB_IMM(ir, IREG_FPU_TOP, IREG_FPU_TOP, 1);
}
static inline void CHECK_SEG_LIMITS(codeblock_t *block, ir_data_t *ir, x86seg *seg, int addr_reg, int end_offset)
{
static inline void CHECK_SEG_LIMITS(codeblock_t *block, ir_data_t *ir, x86seg *seg, int addr_reg, int end_offset) {
if ((seg == &cpu_state.seg_ds && codegen_flat_ds && !(cpu_cur_status & CPU_STATUS_NOTFLATDS)) ||
(seg == &cpu_state.seg_ss && codegen_flat_ss && !(cpu_cur_status & CPU_STATUS_NOTFLATSS)))
return;
uop_CMP_JB(ir, addr_reg, ireg_seg_limit_low(seg), codegen_gpf_rout);
if (end_offset)
{
if (end_offset) {
uop_ADD_IMM(ir, IREG_temp3, addr_reg, end_offset);
uop_CMP_JNBE(ir, IREG_temp3, ireg_seg_limit_high(seg), codegen_gpf_rout);
}
else
} else
uop_CMP_JNBE(ir, addr_reg, ireg_seg_limit_high(seg), codegen_gpf_rout);
}
static inline void LOAD_IMMEDIATE_FROM_RAM_8(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
static inline void LOAD_IMMEDIATE_FROM_RAM_8(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr) {
uop_MOVZX_REG_PTR_8(ir, dest_reg, get_ram_ptr(addr));
}
void LOAD_IMMEDIATE_FROM_RAM_16_unaligned(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr);
static inline void LOAD_IMMEDIATE_FROM_RAM_16(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
static inline void LOAD_IMMEDIATE_FROM_RAM_16(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr) {
if ((addr & 0xfff) == 0xfff)
LOAD_IMMEDIATE_FROM_RAM_16_unaligned(block, ir, dest_reg, addr);
else
@@ -105,8 +83,7 @@ static inline void LOAD_IMMEDIATE_FROM_RAM_16(codeblock_t *block, ir_data_t *ir,
}
void LOAD_IMMEDIATE_FROM_RAM_32_unaligned(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr);
static inline void LOAD_IMMEDIATE_FROM_RAM_32(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr)
{
static inline void LOAD_IMMEDIATE_FROM_RAM_32(codeblock_t *block, ir_data_t *ir, int dest_reg, uint32_t addr) {
if ((addr & 0xfff) >= 0xffd)
LOAD_IMMEDIATE_FROM_RAM_32_unaligned(block, ir, dest_reg, addr);
else
@@ -114,8 +91,7 @@ static inline void LOAD_IMMEDIATE_FROM_RAM_32(codeblock_t *block, ir_data_t *ir,
}
int codegen_can_unroll_full(codeblock_t *block, ir_data_t *ir, uint32_t next_pc, uint32_t dest_addr);
static inline int codegen_can_unroll(codeblock_t *block, ir_data_t *ir, uint32_t next_pc, uint32_t dest_addr)
{
static inline int codegen_can_unroll(codeblock_t *block, ir_data_t *ir, uint32_t next_pc, uint32_t dest_addr) {
if (block->flags & CODEBLOCK_BYTE_MASK)
return 0;
@@ -128,5 +104,4 @@ static inline int codegen_can_unroll(codeblock_t *block, ir_data_t *ir, uint32_t
return codegen_can_unroll_full(block, ir, next_pc, dest_addr);
}
#endif /* _CODEGEN_OPS_HELPERS_H_ */

1
includes/private/codegen/codegen_ops_jump.h
View File

@@ -23,5 +23,4 @@ uint32_t ropRETF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropRETF_imm_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropRETF_imm_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_JUMP_H_ */

1
includes/private/codegen/codegen_ops_logic.h
View File

@@ -38,5 +38,4 @@ uint32_t ropXOR_w_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
uint32_t ropXOR_l_rm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropXOR_l_rmw(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_LOGIC_H_ */

1
includes/private/codegen/codegen_ops_misc.h
View File

@@ -39,5 +39,4 @@ uint32_t ropSTD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetc
uint32_t ropCLI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSTI(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MISC_H_ */

1
includes/private/codegen/codegen_ops_mmx_arith.h
View File

@@ -20,5 +20,4 @@ uint32_t ropPMADDWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropPMULHW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPMULLW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_ARITH_H_ */

1
includes/private/codegen/codegen_ops_mmx_cmp.h
View File

@@ -7,5 +7,4 @@ uint32_t ropPCMPGTB(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropPCMPGTW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPCMPGTD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_CMP_H_ */

1
includes/private/codegen/codegen_ops_mmx_loadstore.h
View File

@@ -6,5 +6,4 @@ uint32_t ropMOVD_d_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropMOVQ_r_q(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropMOVQ_q_r(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_LOADSTORE_H_ */

1
includes/private/codegen/codegen_ops_mmx_logic.h
View File

@@ -5,5 +5,4 @@ uint32_t ropPANDN(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uint32_t ropPOR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPXOR(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_LOGIC_H_ */

1
includes/private/codegen/codegen_ops_mmx_pack.h
View File

@@ -10,5 +10,4 @@ uint32_t ropPUNPCKHBW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_
uint32_t ropPUNPCKHWD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUNPCKHDQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_PACK_H_ */

1
includes/private/codegen/codegen_ops_mmx_shift.h
View File

@@ -8,5 +8,4 @@ uint32_t ropPSLLW(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
uint32_t ropPSLLD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPSLLQ(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MMX_SHIFT_H_ */

1
includes/private/codegen/codegen_ops_mov.h
View File

@@ -44,5 +44,4 @@ uint32_t ropXCHG_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropXLAT(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_MOV_H_ */

1
includes/private/codegen/codegen_ops_shift.h
View File

@@ -17,5 +17,4 @@ uint32_t ropSHLD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint3
uint32_t ropSHRD_16_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropSHRD_32_imm(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_SHIFT_H_ */

1
includes/private/codegen/codegen_ops_stack.h
View File

@@ -50,5 +50,4 @@ uint32_t ropPOPA_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t
uint32_t ropPUSHF(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
uint32_t ropPUSHFD(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc);
#endif /* _CODEGEN_OPS_STACK_H_ */

41
includes/private/codegen/codegen_reg.h
View File

@@ -15,8 +15,7 @@
#define IREG_SIZE_D (4 << IREG_SIZE_SHIFT)
#define IREG_SIZE_Q (5 << IREG_SIZE_SHIFT)
enum
{
enum {
IREG_EAX = 0,
IREG_ECX = 1,
IREG_EDX = 2,
@@ -220,8 +219,7 @@ enum
#define IREG_TOP_diff_stack_offset 32
static inline int ireg_seg_base(x86seg *seg)
{
static inline int ireg_seg_base(x86seg *seg) {
if (seg == &cpu_state.seg_cs)
return IREG_CS_base;
if (seg == &cpu_state.seg_ds)
@@ -238,8 +236,7 @@ static inline int ireg_seg_base(x86seg *seg)
return 0;
}
static inline int ireg_seg_limit_low(x86seg *seg)
{
static inline int ireg_seg_limit_low(x86seg *seg) {
if (seg == &cpu_state.seg_cs)
return IREG_CS_limit_low;
if (seg == &cpu_state.seg_ds)
@@ -255,8 +252,7 @@ static inline int ireg_seg_limit_low(x86seg *seg)
fatal("ireg_seg_limit_low : unknown segment\n");
return 0;
}
static inline int ireg_seg_limit_high(x86seg *seg)
{
static inline int ireg_seg_limit_high(x86seg *seg) {
if (seg == &cpu_state.seg_cs)
return IREG_CS_limit_high;
if (seg == &cpu_state.seg_ds)
@@ -281,8 +277,7 @@ extern uint8_t reg_last_version[IREG_COUNT];
/*This register and the parent uOP have been optimised out.*/
#define REG_FLAGS_DEAD (1 << 1)
typedef struct
{
typedef struct {
/*Refcount of pending reads on this register version*/
uint8_t refcount;
/*Flags*/
@@ -299,14 +294,12 @@ extern reg_version_t reg_version[IREG_COUNT][256];
can be optimised out*/
extern uint16_t reg_dead_list;
static inline void add_to_dead_list(reg_version_t *regv, int reg, int version)
{
static inline void add_to_dead_list(reg_version_t *regv, int reg, int version) {
regv->next = reg_dead_list;
reg_dead_list = version | (reg << 8);
}
typedef struct
{
typedef struct {
uint16_t reg;
uint16_t version;
} ir_reg_t;
@@ -320,8 +313,7 @@ extern int max_version_refcount;
#define REG_VERSION_MAX 250
#define REG_REFCOUNT_MAX 250
static inline ir_reg_t codegen_reg_read(int reg)
{
static inline ir_reg_t codegen_reg_read(int reg) {
ir_reg_t ireg;
reg_version_t *version;
@@ -343,14 +335,14 @@ static inline ir_reg_t codegen_reg_read(int reg)
CPU_BLOCK_END();
if (version->refcount > max_version_refcount)
max_version_refcount = version->refcount;
// pclog("codegen_reg_read: %i %i %i\n", reg & IREG_REG_MASK, ireg.version, reg_version_refcount[IREG_GET_REG(ireg.reg)][ireg.version]);
// pclog("codegen_reg_read: %i %i %i\n", reg & IREG_REG_MASK, ireg.version,
// reg_version_refcount[IREG_GET_REG(ireg.reg)][ireg.version]);
return ireg;
}
int reg_is_native_size(ir_reg_t ir_reg);
static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
{
static inline ir_reg_t codegen_reg_write(int reg, int uop_nr) {
ir_reg_t ireg;
int last_version = reg_last_version[IREG_GET_REG(reg)];
reg_version_t *version;
@@ -363,9 +355,9 @@ static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
ireg.version = last_version + 1;
if (IREG_GET_REG(reg) > IREG_EBX && last_version && !reg_version[IREG_GET_REG(reg)][last_version].refcount &&
!(reg_version[IREG_GET_REG(reg)][last_version].flags & REG_FLAGS_REQUIRED))
{
if (reg_is_native_size(ireg)) /*Non-native size registers have an implicit dependency on the previous version, so don't add to dead list*/
!(reg_version[IREG_GET_REG(reg)][last_version].flags & REG_FLAGS_REQUIRED)) {
if (reg_is_native_size(ireg)) /*Non-native size registers have an implicit dependency on the previous version, so
don't add to dead list*/
add_to_dead_list(&reg_version[IREG_GET_REG(reg)][last_version], IREG_GET_REG(reg), last_version);
}
@@ -388,10 +380,7 @@ static inline ir_reg_t codegen_reg_write(int reg, int uop_nr)
return ireg;
}
static inline int ir_reg_is_invalid(ir_reg_t ir_reg)
{
return (IREG_GET_REG(ir_reg.reg) == IREG_INVALID);
}
static inline int ir_reg_is_invalid(ir_reg_t ir_reg) { return (IREG_GET_REG(ir_reg.reg) == IREG_INVALID); }
struct ir_data_t;

87
includes/private/codegen/codegen_timing_common.h
View File

@@ -77,12 +77,10 @@
#define HAS_IMM8 (1ull << 34)
#define HAS_IMM1632 (1ull << 35)
#define REGMASK_IMPL_ESP (1 << 8)
#define REGMASK_SHIFTPACK (1 << 9)
#define REGMASK_MULTIPLY (1 << 9)
extern uint64_t opcode_deps[256];
extern uint64_t opcode_deps_mod3[256];
extern uint64_t opcode_deps_0f[256];
@@ -120,50 +118,52 @@ extern uint64_t opcode_deps_81_mod3[8];
extern uint64_t opcode_deps_8x[8];
extern uint64_t opcode_deps_8x_mod3[8];
static inline uint32_t get_addr_regmask(uint64_t data, uint32_t fetchdat, int op_32)
{
static inline uint32_t get_addr_regmask(uint64_t data, uint32_t fetchdat, int op_32) {
uint32_t addr_regmask = 0;
if (data & MODRM)
{
if (data & MODRM) {
uint8_t modrm = fetchdat & 0xff;
if ((modrm & 0xc0) != 0xc0)
{
if (op_32 & 0x200)
{
if ((modrm & 0x7) == 4)
{
if ((modrm & 0xc0) != 0xc0) {
if (op_32 & 0x200) {
if ((modrm & 0x7) == 4) {
uint8_t sib = (fetchdat >> 8) & 0xff;
if ((modrm & 0xc0) != 0xc0 && (sib & 7) != 5)
{
if ((modrm & 0xc0) != 0xc0 && (sib & 7) != 5) {
addr_regmask = 1 << (sib & 7);
if ((sib & 0x38) != 0x20)
addr_regmask |= 1 << ((sib >> 3) & 7);
}
}
else if ((modrm & 0xc7) != 5)
{
} else if ((modrm & 0xc7) != 5) {
addr_regmask = 1 << (modrm & 7);
}
}
else
{
if ((modrm & 0xc7) != 0x06)
{
switch (modrm & 7)
{
case 0: addr_regmask = REG_BX | REG_SI; break;
case 1: addr_regmask = REG_BX | REG_DI; break;
case 2: addr_regmask = REG_BP | REG_SI; break;
case 3: addr_regmask = REG_BP | REG_DI; break;
case 4: addr_regmask = REG_SI; break;
case 5: addr_regmask = REG_DI; break;
case 6: addr_regmask = REG_BP; break;
case 7: addr_regmask = REG_BX; break;
} else {
if ((modrm & 0xc7) != 0x06) {
switch (modrm & 7) {
case 0:
addr_regmask = REG_BX | REG_SI;
break;
case 1:
addr_regmask = REG_BX | REG_DI;
break;
case 2:
addr_regmask = REG_BP | REG_SI;
break;
case 3:
addr_regmask = REG_BP | REG_DI;
break;
case 4:
addr_regmask = REG_SI;
break;
case 5:
addr_regmask = REG_DI;
break;
case 6:
addr_regmask = REG_BP;
break;
case 7:
addr_regmask = REG_BX;
break;
}
}
}
@@ -176,18 +176,15 @@ static inline uint32_t get_addr_regmask(uint64_t data, uint32_t fetchdat, int op
return addr_regmask;
}
static inline uint32_t get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit8, int op_32)
{
static inline uint32_t get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit8, int op_32) {
uint32_t mask = 0;
if (data & SRCDEP_REG)
{
if (data & SRCDEP_REG) {
int reg = (fetchdat >> 3) & 7;
if (bit8)
reg &= 3;
mask |= (1 << reg);
}
if (data & SRCDEP_RM)
{
if (data & SRCDEP_RM) {
int reg = fetchdat & 7;
if (bit8)
reg &= 3;
@@ -204,18 +201,15 @@ static inline uint32_t get_srcdep_mask(uint64_t data, uint32_t fetchdat, int bit
return mask;
}
static inline uint32_t get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit8)
{
static inline uint32_t get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit8) {
uint32_t mask = 0;
if (data & DSTDEP_REG)
{
if (data & DSTDEP_REG) {
int reg = (fetchdat >> 3) & 7;
if (bit8)
reg &= 3;
mask |= (1 << reg);
}
if (data & DSTDEP_RM)
{
if (data & DSTDEP_RM) {
int reg = fetchdat & 7;
if (bit8)
reg &= 3;
@@ -232,5 +226,4 @@ static inline uint32_t get_dstdep_mask(uint64_t data, uint32_t fetchdat, int bit
return mask;
}
#endif /* _CODEGEN_TIMING_COMMON_H_ */

6
includes/private/codegen/codegen_x86-64.h
View File

@@ -14,15 +14,11 @@
#define BLOCK_MAX 1620
enum
{
OP_RET = 0xc3
};
enum { OP_RET = 0xc3 };
#define NR_HOST_REGS 4
extern int host_reg_mapping[NR_HOST_REGS];
#define NR_HOST_XMM_REGS 7
extern int host_reg_xmm_mapping[NR_HOST_XMM_REGS];
#endif /* _CODEGEN_X86_64_H_ */

152
includes/private/cpu/386_common.h
View File

@@ -1,24 +1,52 @@
#ifndef _386_COMMON_H_
#define _386_COMMON_H_
#define readmemb(s, a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1)?readmembl((s)+(a)): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uint32_t)((s) + (a))) )
#define readmemw(s, a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmeml(s, a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemq(s, a) ((readlookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7))?readmemql((s)+(a)):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemb(s, a) \
((readlookup2[(uint32_t)((s) + (a)) >> 12] == -1) \
? readmembl((s) + (a)) \
: *(uint8_t *)(readlookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))))
#define readmemw(s, a) \
((readlookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 1)) \
? readmemwl((s) + (a)) \
: *(uint16_t *)(readlookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))))
#define readmeml(s, a) \
((readlookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 3)) \
? readmemll((s) + (a)) \
: *(uint32_t *)(readlookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))))
#define readmemq(s, a) \
((readlookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 7)) \
? readmemql((s) + (a)) \
: *(uint64_t *)(readlookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))))
#define writememb(s, a, v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1) writemembl((s)+(a),v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememw(s, a, v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 1)) writememwl((s)+(a),v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememl(s, a, v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 3)) writememll((s)+(a),v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememq(s, a, v) if (writelookup2[(uint32_t)((s)+(a))>>12]==-1 || (((s)+(a)) & 7)) writememql((s)+(a),v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememb(s, a, v) \
if (writelookup2[(uint32_t)((s) + (a)) >> 12] == -1) \
writemembl((s) + (a), v); \
else \
*(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememw(s, a, v) \
if (writelookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 1)) \
writememwl((s) + (a), v); \
else \
*(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememl(s, a, v) \
if (writelookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 3)) \
writememll((s) + (a), v); \
else \
*(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
#define writememq(s, a, v) \
if (writelookup2[(uint32_t)((s) + (a)) >> 12] == -1 || (((s) + (a)) & 7)) \
writememql((s) + (a), v); \
else \
*(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uint32_t)((s) + (a))) = v
int checkio(int port);
#define check_io_perm(port) if (!IOPLp || (cpu_state.eflags&VM_FLAG)) \
{ \
#define check_io_perm(port) \
if (!IOPLp || (cpu_state.eflags & VM_FLAG)) { \
int tempi = checkio(port); \
if (cpu_state.abrt) return 1; \
if (tempi) \
{ \
if (cpu_state.abrt) \
return 1; \
if (tempi) { \
if (cpu_state.eflags & VM_FLAG) \
x86gpf_expected(NULL, 0); \
else \
@@ -28,48 +56,43 @@ int checkio(int port);
}
#define SEG_CHECK_READ(seg) \
do \
{ \
if ((seg)->base == 0xffffffff) \
{ \
do { \
if ((seg)->base == 0xffffffff) { \
x86gpf("Segment can't read", 0); \
return 1; \
} \
} while (0)
#define SEG_CHECK_WRITE(seg) \
do \
{ \
if ((seg)->base == 0xffffffff) \
{ \
do { \
if ((seg)->base == 0xffffffff) { \
x86gpf("Segment can't write", 0); \
return 1; \
} \
} while (0)
#define CHECK_READ(seg, low, high) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && (((seg)->access & 10) == 8))) \
{ \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || \
((msw & 1) && !(cpu_state.eflags & VM_FLAG) && (((seg)->access & 10) == 8))) { \
x86gpf("Limit check", 0); \
return 1; \
}
#define CHECK_WRITE(seg, low, high) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || !((seg)->access & 2) || ((msw & 1) && !(cpu_state.eflags & VM_FLAG) && ((seg)->access & 8))) \
{ \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high) || !((seg)->access & 2) || \
((msw & 1) && !(cpu_state.eflags & VM_FLAG) && ((seg)->access & 8))) { \
x86gpf("Limit check", 0); \
return 1; \
}
#define CHECK_WRITE_REP(seg, low, high) \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high)) \
{ \
if ((low < (seg)->limit_low) || (high > (seg)->limit_high)) { \
x86gpf("Limit check", 0); \
break; \
}
#define NOTRM if (!(msw & 1) || (cpu_state.eflags & VM_FLAG))\
{ \
#define NOTRM \
if (!(msw & 1) || (cpu_state.eflags & VM_FLAG)) { \
x86_int(6); \
return 1; \
}
@@ -178,9 +201,7 @@ static inline uint32_t geteal() {
return readmeml(easeg, cpu_state.eaaddr);
}
static inline uint64_t geteaq() {
return readmemq(easeg, cpu_state.eaaddr);
}
static inline uint64_t geteaq() { return readmemq(easeg, cpu_state.eaaddr); }
static inline uint8_t geteab_mem() {
if (eal_r)
@@ -198,21 +219,62 @@ static inline uint32_t geteal_mem() {
return readmeml(easeg, cpu_state.eaaddr);
}
static inline void seteaq(uint64_t v) {
writememql(easeg + cpu_state.eaaddr, v);
}
static inline void seteaq(uint64_t v) { writememql(easeg + cpu_state.eaaddr, v); }
#define seteab(v) if (cpu_mod!=3) { if (eal_w) *(uint8_t *)eal_w=v; else writemembl(easeg+cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
#define seteaw(v) if (cpu_mod!=3) { if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
#define seteal(v) if (cpu_mod!=3) { if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
#define seteab(v) \
if (cpu_mod != 3) { \
if (eal_w) \
*(uint8_t *)eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v); \
} else if (cpu_rm & 4) \
cpu_state.regs[cpu_rm & 3].b.h = v; \
else \
cpu_state.regs[cpu_rm].b.l = v
#define seteaw(v) \
if (cpu_mod != 3) { \
if (eal_w) \
*(uint16_t *)eal_w = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].w = v
#define seteal(v) \
if (cpu_mod != 3) { \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].l = v
#define seteab_mem(v) if (eal_w) *(uint8_t *)eal_w=v; else writemembl(easeg+cpu_state.eaaddr,v);
#define seteaw_mem(v) if (eal_w) *(uint16_t *)eal_w=v; else writememwl(easeg+cpu_state.eaaddr,v);
#define seteal_mem(v) if (eal_w) *eal_w=v; else writememll(easeg+cpu_state.eaaddr,v);
#define seteab_mem(v) \
if (eal_w) \
*(uint8_t *)eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v);
#define seteaw_mem(v) \
if (eal_w) \
*(uint16_t *)eal_w = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v);
#define seteal_mem(v) \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v);
#define getbytef() ((uint8_t)(fetchdat)); cpu_state.pc++
#define getwordf() ((uint16_t)(fetchdat)); cpu_state.pc+=2
#define getbyte2f() ((uint8_t)(fetchdat>>8)); cpu_state.pc++
#define getword2f() ((uint16_t)(fetchdat>>8)); cpu_state.pc+=2
#define getbytef() \
((uint8_t)(fetchdat)); \
cpu_state.pc++
#define getwordf() \
((uint16_t)(fetchdat)); \
cpu_state.pc += 2
#define getbyte2f() \
((uint8_t)(fetchdat >> 8)); \
cpu_state.pc++
#define getword2f() \
((uint16_t)(fetchdat >> 8)); \
cpu_state.pc += 2
#endif /* _386_COMMON_H_ */

15539
includes/private/cpu/386_ops.h
View File

File diff suppressed because it is too large Load Diff

11
includes/private/cpu/8087.h
View File

@@ -16,18 +16,13 @@
#define CHECK_WRITE(seg, addr_lo, addr_hi)
#define PREFETCH_RUN(timing, bytes, rmdat, a, b, c, d, e)
static uint32_t readmeml(uint32_t seg, uint32_t addr) {
return readmemw(seg, addr) | (readmemw(seg, addr + 2) << 16);
}
static uint32_t readmeml(uint32_t seg, uint32_t addr) { return readmemw(seg, addr) | (readmemw(seg, addr + 2) << 16); }
static uint64_t readmemq(uint32_t seg, uint32_t addr) {
return (uint64_t)readmemw(seg, addr) | ((uint64_t)readmemw(seg, addr + 2) << 16) |
((uint64_t)readmemw(seg, addr + 4) << 32) |
((uint64_t)readmemw(seg, addr + 6) << 48);
((uint64_t)readmemw(seg, addr + 4) << 32) | ((uint64_t)readmemw(seg, addr + 6) << 48);
}
static void writememb_8087(uint32_t seg, uint32_t addr, uint8_t val) {
writememb(seg + addr, val);
}
static void writememb_8087(uint32_t seg, uint32_t addr, uint8_t val) { writememb(seg + addr, val); }
static void writememl(uint32_t seg, uint32_t addr, uint32_t val) {
writememw(seg, addr, val & 0xffff);
writememw(seg, addr + 2, (val >> 16) & 0xffff);

13
includes/private/cpu/cpu.h
View File

@@ -69,14 +69,7 @@ extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
extern int timing_misaligned;
enum {
FPU_NONE,
FPU_8087,
FPU_287,
FPU_287XL,
FPU_387,
FPU_BUILTIN
};
enum { FPU_NONE, FPU_8087, FPU_287, FPU_287XL, FPU_387, FPU_BUILTIN };
extern CPU *cpu_s;
@@ -132,9 +125,7 @@ extern int cpu_cyrix_alignment;
#define CPU_FEATURE_SYSCALL (1 << 7)
extern uint32_t cpu_features;
static inline int cpu_has_feature(int feature) {
return cpu_features & feature;
}
static inline int cpu_has_feature(int feature) { return cpu_features & feature; }
#define CR4_TSD (1 << 2)
#define CR4_DE (1 << 3)

26
includes/private/cpu/x86.h
View File

@@ -226,16 +226,24 @@ extern float mips, flops;
#define getr16(r) cpu_state.regs[r].w
#define getr32(r) cpu_state.regs[r].l
#define setr8(r, v) if (r&4) cpu_state.regs[r&3].b.h=v; \
else cpu_state.regs[r&3].b.l=v;
#define setr8(r, v) \
if (r & 4) \
cpu_state.regs[r & 3].b.h = v; \
else \
cpu_state.regs[r & 3].b.l = v;
#define setr16(r, v) cpu_state.regs[r].w = v
#define setr32(r, v) cpu_state.regs[r].l = v
#define fetchea() { rmdat=readmemb(cs+pc); pc++; \
#define fetchea() \
{ \
rmdat = readmemb(cs + pc); \
pc++; \
reg = (rmdat >> 3) & 7; \
mod = (rmdat >> 6) & 3; \
rm = rmdat & 7; \
if (mod!=3) fetcheal(); }
if (mod != 3) \
fetcheal(); \
}
extern int optype;
#define JMP 1
@@ -243,15 +251,7 @@ extern int optype;
#define IRET 3
#define OPTYPE_INT 4
enum {
ABRT_NONE = 0,
ABRT_GEN,
ABRT_TS = 0xA,
ABRT_NP = 0xB,
ABRT_SS = 0xC,
ABRT_GPF = 0xD,
ABRT_PF = 0xE
};
enum { ABRT_NONE = 0, ABRT_GEN, ABRT_TS = 0xA, ABRT_NP = 0xB, ABRT_SS = 0xC, ABRT_GPF = 0xD, ABRT_PF = 0xE };
#define ABRT_MASK 0x7f
/*An 'expected' exception is one that would be expected to occur on every execution

160
includes/private/cpu/x86_flags.h
View File

@@ -85,7 +85,8 @@ static inline int ZF_SET() {
case FLAGS_ADC32:
case FLAGS_SBC8:
case FLAGS_SBC16:
case FLAGS_SBC32:return !cpu_state.flags_res;
case FLAGS_SBC32:
return !cpu_state.flags_res;
case FLAGS_ROL8:
case FLAGS_ROL16:
@@ -93,7 +94,8 @@ static inline int ZF_SET() {
case FLAGS_ROR8:
case FLAGS_ROR16:
case FLAGS_ROR32:
case FLAGS_UNKNOWN:return cpu_state.flags & Z_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & Z_FLAG;
}
return 0;
}
@@ -109,7 +111,8 @@ static inline int NF_SET() {
case FLAGS_INC8:
case FLAGS_DEC8:
case FLAGS_ADC8:
case FLAGS_SBC8:return cpu_state.flags_res & 0x80;
case FLAGS_SBC8:
return cpu_state.flags_res & 0x80;
case FLAGS_ZN16:
case FLAGS_ADD16:
@@ -120,7 +123,8 @@ static inline int NF_SET() {
case FLAGS_INC16:
case FLAGS_DEC16:
case FLAGS_ADC16:
case FLAGS_SBC16:return cpu_state.flags_res & 0x8000;
case FLAGS_SBC16:
return cpu_state.flags_res & 0x8000;
case FLAGS_ZN32:
case FLAGS_ADD32:
@@ -131,7 +135,8 @@ static inline int NF_SET() {
case FLAGS_INC32:
case FLAGS_DEC32:
case FLAGS_ADC32:
case FLAGS_SBC32:return cpu_state.flags_res & 0x80000000;
case FLAGS_SBC32:
return cpu_state.flags_res & 0x80000000;
case FLAGS_ROL8:
case FLAGS_ROL16:
@@ -139,7 +144,8 @@ static inline int NF_SET() {
case FLAGS_ROR8:
case FLAGS_ROR16:
case FLAGS_ROR32:
case FLAGS_UNKNOWN:return cpu_state.flags & N_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & N_FLAG;
}
return 0;
}
@@ -175,7 +181,8 @@ static inline int PF_SET() {
case FLAGS_ADC32:
case FLAGS_SBC8:
case FLAGS_SBC16:
case FLAGS_SBC32:return znptable8[cpu_state.flags_res & 0xff] & P_FLAG;
case FLAGS_SBC32:
return znptable8[cpu_state.flags_res & 0xff] & P_FLAG;
case FLAGS_ROL8:
case FLAGS_ROL16:
@@ -183,7 +190,8 @@ static inline int PF_SET() {
case FLAGS_ROR8:
case FLAGS_ROR16:
case FLAGS_ROR32:
case FLAGS_UNKNOWN:return cpu_state.flags & P_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & P_FLAG;
}
return 0;
}
@@ -195,45 +203,71 @@ static inline int VF_SET() {
case FLAGS_ZN32:
case FLAGS_SAR8:
case FLAGS_SAR16:
case FLAGS_SAR32:return 0;
case FLAGS_SAR32:
return 0;
case FLAGS_ADC8:
case FLAGS_ADD8:
case FLAGS_INC8:return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_INC8:
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80) &&
((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_ADC16:
case FLAGS_ADD16:
case FLAGS_INC16:return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x8000) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_INC16:
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x8000) &&
((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_ADC32:
case FLAGS_ADD32:
case FLAGS_INC32:return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80000000) && ((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_INC32:
return !((cpu_state.flags_op1 ^ cpu_state.flags_op2) & 0x80000000) &&
((cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_SBC8:
case FLAGS_SUB8:
case FLAGS_DEC8:return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_DEC8:
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80);
case FLAGS_SBC16:
case FLAGS_SUB16:
case FLAGS_DEC16:return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_DEC16:
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x8000);
case FLAGS_SBC32:
case FLAGS_SUB32:
case FLAGS_DEC32:return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_DEC32:
return ((cpu_state.flags_op1 ^ cpu_state.flags_op2) & (cpu_state.flags_op1 ^ cpu_state.flags_res) & 0x80000000);
case FLAGS_SHL8:return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x80);
case FLAGS_SHL16:return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x8000);
case FLAGS_SHL32:return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) & 0x80000000);
case FLAGS_SHL8:
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) &
0x80);
case FLAGS_SHL16:
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) &
0x8000);
case FLAGS_SHL32:
return (((cpu_state.flags_op1 << cpu_state.flags_op2) ^ (cpu_state.flags_op1 << (cpu_state.flags_op2 - 1))) &
0x80000000);
case FLAGS_SHR8:return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80));
case FLAGS_SHR16:return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x8000));
case FLAGS_SHR32:return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80000000));
case FLAGS_SHR8:
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80));
case FLAGS_SHR16:
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x8000));
case FLAGS_SHR32:
return ((cpu_state.flags_op2 == 1) && (cpu_state.flags_op1 & 0x80000000));
case FLAGS_ROL8:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 7)) & 1;
case FLAGS_ROL16:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 15)) & 1;
case FLAGS_ROL32:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 31)) & 1;
case FLAGS_ROL8:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 7)) & 1;
case FLAGS_ROL16:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 15)) & 1;
case FLAGS_ROL32:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 31)) & 1;
case FLAGS_ROR8:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x40;
case FLAGS_ROR16:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x4000;
case FLAGS_ROR32:return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x40000000;
case FLAGS_ROR8:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x40;
case FLAGS_ROR16:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x4000;
case FLAGS_ROR32:
return (cpu_state.flags_res ^ (cpu_state.flags_res >> 1)) & 0x40000000;
case FLAGS_UNKNOWN:return cpu_state.flags & V_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & V_FLAG;
}
return 0;
}
@@ -251,14 +285,16 @@ static inline int AF_SET() {
case FLAGS_SHR32:
case FLAGS_SAR8:
case FLAGS_SAR16:
case FLAGS_SAR32:return 0;
case FLAGS_SAR32:
return 0;
case FLAGS_ADD8:
case FLAGS_ADD16:
case FLAGS_ADD32:
case FLAGS_INC8:
case FLAGS_INC16:
case FLAGS_INC32:return ((cpu_state.flags_op1 & 0xF) + (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_INC32:
return ((cpu_state.flags_op1 & 0xF) + (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_ADC8:
return ((cpu_state.flags_res & 0xf) < (cpu_state.flags_op1 & 0xf)) ||
@@ -275,7 +311,8 @@ static inline int AF_SET() {
case FLAGS_SUB32:
case FLAGS_DEC8:
case FLAGS_DEC16:
case FLAGS_DEC32:return ((cpu_state.flags_op1 & 0xF) - (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_DEC32:
return ((cpu_state.flags_op1 & 0xF) - (cpu_state.flags_op2 & 0xF)) & 0x10;
case FLAGS_SBC8:
case FLAGS_SBC16:
@@ -289,16 +326,20 @@ static inline int AF_SET() {
case FLAGS_ROR8:
case FLAGS_ROR16:
case FLAGS_ROR32:
case FLAGS_UNKNOWN:return cpu_state.flags & A_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & A_FLAG;
}
return 0;
}
static inline int CF_SET() {
switch (cpu_state.flags_op) {
case FLAGS_ADD8:return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x100) ? 1 : 0;
case FLAGS_ADD16:return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x10000) ? 1 : 0;
case FLAGS_ADD32:return (cpu_state.flags_res < cpu_state.flags_op1);
case FLAGS_ADD8:
return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x100) ? 1 : 0;
case FLAGS_ADD16:
return ((cpu_state.flags_op1 + cpu_state.flags_op2) & 0x10000) ? 1 : 0;
case FLAGS_ADD32:
return (cpu_state.flags_res < cpu_state.flags_op1);
case FLAGS_ADC8:
return (cpu_state.flags_res < cpu_state.flags_op1) ||
@@ -312,7 +353,8 @@ static inline int CF_SET() {
case FLAGS_SUB8:
case FLAGS_SUB16:
case FLAGS_SUB32:return (cpu_state.flags_op1 < cpu_state.flags_op2);
case FLAGS_SUB32:
return (cpu_state.flags_op1 < cpu_state.flags_op2);
case FLAGS_SBC8:
case FLAGS_SBC16:
@@ -320,29 +362,41 @@ static inline int CF_SET() {
return (cpu_state.flags_op1 < cpu_state.flags_op2) ||
(cpu_state.flags_op1 == cpu_state.flags_op2 && cpu_state.flags_res != 0);
case FLAGS_SHL8:return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80) ? 1 : 0;
case FLAGS_SHL16:return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x8000) ? 1 : 0;
case FLAGS_SHL32:return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80000000) ? 1 : 0;
case FLAGS_SHL8:
return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80) ? 1 : 0;
case FLAGS_SHL16:
return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x8000) ? 1 : 0;
case FLAGS_SHL32:
return ((cpu_state.flags_op1 << (cpu_state.flags_op2 - 1)) & 0x80000000) ? 1 : 0;
case FLAGS_SHR8:
case FLAGS_SHR16:
case FLAGS_SHR32:return (cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SHR32:
return (cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR8:return ((int8_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR16:return ((int16_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR32:return ((int32_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR8:
return ((int8_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR16:
return ((int16_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_SAR32:
return ((int32_t)cpu_state.flags_op1 >> (cpu_state.flags_op2 - 1)) & 1;
case FLAGS_ZN8:
case FLAGS_ZN16:
case FLAGS_ZN32:return 0;
case FLAGS_ZN32:
return 0;
case FLAGS_ROL8:
case FLAGS_ROL16:
case FLAGS_ROL32:return cpu_state.flags_res & 1;
case FLAGS_ROL32:
return cpu_state.flags_res & 1;
case FLAGS_ROR8:return (cpu_state.flags_res & 0x80) ? 1 : 0;
case FLAGS_ROR16:return (cpu_state.flags_res & 0x8000) ? 1 : 0;
case FLAGS_ROR32:return (cpu_state.flags_res & 0x80000000) ? 1 : 0;
case FLAGS_ROR8:
return (cpu_state.flags_res & 0x80) ? 1 : 0;
case FLAGS_ROR16:
return (cpu_state.flags_res & 0x8000) ? 1 : 0;
case FLAGS_ROR32:
return (cpu_state.flags_res & 0x80000000) ? 1 : 0;
case FLAGS_DEC8:
case FLAGS_DEC16:
@@ -350,7 +404,8 @@ static inline int CF_SET() {
case FLAGS_INC8:
case FLAGS_INC16:
case FLAGS_INC32:
case FLAGS_UNKNOWN:return cpu_state.flags & C_FLAG;
case FLAGS_UNKNOWN:
return cpu_state.flags & C_FLAG;
}
return 0;
}
@@ -382,9 +437,7 @@ static inline void flags_rebuild() {
}
}
static inline void flags_extract() {
cpu_state.flags_op = FLAGS_UNKNOWN;
}
static inline void flags_extract() { cpu_state.flags_op = FLAGS_UNKNOWN; }
static inline void flags_rebuild_c() {
if (cpu_state.flags_op != FLAGS_UNKNOWN) {
@@ -396,8 +449,7 @@ static inline void flags_rebuild_c() {
}
static inline int flags_res_valid() {
if (cpu_state.flags_op == FLAGS_UNKNOWN ||
(cpu_state.flags_op >= FLAGS_ROL8 && cpu_state.flags_op <= FLAGS_ROR32))
if (cpu_state.flags_op == FLAGS_UNKNOWN || (cpu_state.flags_op >= FLAGS_ROL8 && cpu_state.flags_op <= FLAGS_ROR32))
return 0;
return 1;

66
includes/private/cpu/x86_ops_3dnow.h
View File

@@ -246,10 +246,14 @@ static int opPI2FD(uint32_t fetchdat) {
}
static int opPMULHRW(uint32_t fetchdat) {
if (cpu_mod == 3) {
cpu_state.MM[cpu_reg].w[0] = (((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[1] = (((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[2] = (((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[3] = (((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[0] =
(((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)cpu_state.MM[cpu_rm].sw[0]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[1] =
(((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)cpu_state.MM[cpu_rm].sw[1]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[2] =
(((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)cpu_state.MM[cpu_rm].sw[2]) + 0x8000) >> 16;
cpu_state.MM[cpu_reg].w[3] =
(((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)cpu_state.MM[cpu_rm].sw[3]) + 0x8000) >> 16;
CLOCK_CYCLES(1);
} else {
MMX_REG src;
@@ -268,28 +272,44 @@ static int opPMULHRW(uint32_t fetchdat) {
return 0;
}
OpFn OP_TABLE(3DNOW)[256] =
{
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPI2FD, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPF2ID, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
OpFn OP_TABLE(3DNOW)[256] = {
/* 00 01 02 03 04 05 06 07
08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPI2FD, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPF2ID, ILLEGAL, ILLEGAL,
/*20*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ opPFCMPGE, ILLEGAL, ILLEGAL, ILLEGAL, opPFMIN, ILLEGAL, opPFRCP, opPFRSQRT, ILLEGAL, ILLEGAL, opPFSUB, ILLEGAL, ILLEGAL, ILLEGAL, opPFADD, ILLEGAL,
/*a0*/ opPFCMPGT, ILLEGAL, ILLEGAL, ILLEGAL, opPFMAX, ILLEGAL, opPFRCPIT1, opPFRSQIT1, ILLEGAL, ILLEGAL, opPFSUBR, ILLEGAL, ILLEGAL, ILLEGAL, opPFACC, ILLEGAL,
/*b0*/ opPFCMPEQ, ILLEGAL, ILLEGAL, ILLEGAL, opPFMUL, ILLEGAL, opPFRCPIT2, opPMULHRW, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPAVGUSB,
/*80*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*90*/ opPFCMPGE, ILLEGAL, ILLEGAL, ILLEGAL, opPFMIN, ILLEGAL, opPFRCP, opPFRSQRT,
ILLEGAL, ILLEGAL, opPFSUB, ILLEGAL, ILLEGAL, ILLEGAL, opPFADD, ILLEGAL,
/*a0*/ opPFCMPGT, ILLEGAL, ILLEGAL, ILLEGAL, opPFMAX, ILLEGAL, opPFRCPIT1, opPFRSQIT1,
ILLEGAL, ILLEGAL, opPFSUBR, ILLEGAL, ILLEGAL, ILLEGAL, opPFACC, ILLEGAL,
/*b0*/ opPFCMPEQ, ILLEGAL, ILLEGAL, ILLEGAL, opPFMUL, ILLEGAL, opPFRCPIT2, opPMULHRW,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opPAVGUSB,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*c0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
static int op3DNOW_a16(uint32_t fetchdat) {

279
includes/private/cpu/x86_ops_arith.h
View File

@@ -1,52 +1,54 @@
#ifndef _X86_OPS_ARITH_H_
#define _X86_OPS_ARITH_H_
#define OP_ARITH(name, operation, setflags, flagops, gettempc) \
static int op ## name ## _b_rmw_a16(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_b_rmw_a16(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint8_t dst = getr8(cpu_rm); \
uint8_t src = getr8(cpu_reg); \
setflags##8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} \
else \
{ \
} else { \
uint8_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteab(); if (cpu_state.abrt) return 1; \
dst = geteab(); \
if (cpu_state.abrt) \
return 1; \
uint8_t src = getr8(cpu_reg); \
seteab(operation); if (cpu_state.abrt) return 1; \
seteab(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1, 0, 1, 0, 0); \
} \
return 0; \
} \
static int op ## name ## _b_rmw_a32(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_b_rmw_a32(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint8_t dst = getr8(cpu_rm); \
uint8_t src = getr8(cpu_reg); \
setflags##8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} \
else \
{ \
} else { \
uint8_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteab(); if (cpu_state.abrt) return 1; \
dst = geteab(); \
if (cpu_state.abrt) \
return 1; \
uint8_t src = getr8(cpu_reg); \
seteab(operation); if (cpu_state.abrt) return 1; \
seteab(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1, 0, 1, 0, 1); \
@@ -54,52 +56,54 @@
return 0; \
} \
\
static int op ## name ## _w_rmw_a16(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_w_rmw_a16(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint16_t dst = cpu_state.regs[cpu_rm].w; \
uint16_t src = cpu_state.regs[cpu_reg].w; \
setflags##16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} \
else \
{ \
} else { \
uint16_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteaw(); if (cpu_state.abrt) return 1; \
dst = geteaw(); \
if (cpu_state.abrt) \
return 1; \
uint16_t src = cpu_state.regs[cpu_reg].w; \
seteaw(operation); if (cpu_state.abrt) return 1; \
seteaw(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1, 0, 1, 0, 0); \
} \
return 0; \
} \
static int op ## name ## _w_rmw_a32(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_w_rmw_a32(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint16_t dst = cpu_state.regs[cpu_rm].w; \
uint16_t src = cpu_state.regs[cpu_reg].w; \
setflags##16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} \
else \
{ \
} else { \
uint16_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteaw(); if (cpu_state.abrt) return 1; \
dst = geteaw(); \
if (cpu_state.abrt) \
return 1; \
uint16_t src = cpu_state.regs[cpu_reg].w; \
seteaw(operation); if (cpu_state.abrt) return 1; \
seteaw(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1, 0, 1, 0, 1); \
@@ -107,52 +111,54 @@
return 0; \
} \
\
static int op ## name ## _l_rmw_a16(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_l_rmw_a16(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint32_t dst = cpu_state.regs[cpu_rm].l; \
uint32_t src = cpu_state.regs[cpu_reg].l; \
setflags##32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0); \
} \
else \
{ \
} else { \
uint32_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteal(); if (cpu_state.abrt) return 1; \
dst = geteal(); \
if (cpu_state.abrt) \
return 1; \
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
seteal(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 1, 0, 1, 0); \
} \
return 0; \
} \
static int op ## name ## _l_rmw_a32(uint32_t fetchdat) \
{ \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
static int op##name##_l_rmw_a32(uint32_t fetchdat) { \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
uint32_t dst = cpu_state.regs[cpu_rm].l; \
uint32_t src = cpu_state.regs[cpu_reg].l; \
setflags##32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1); \
} \
else \
{ \
} else { \
uint32_t dst; \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
dst = geteal(); if (cpu_state.abrt) return 1; \
dst = geteal(); \
if (cpu_state.abrt) \
return 1; \
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
seteal(operation); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 1, 0, 1, 1); \
@@ -160,30 +166,34 @@
return 0; \
} \
\
static int op ## name ## _b_rm_a16(uint32_t fetchdat) \
{ \
static int op##name##_b_rm_a16(uint32_t fetchdat) { \
uint8_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = getr8(cpu_reg); \
src = geteab(); if (cpu_state.abrt) return 1; \
src = geteab(); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0); \
return 0; \
} \
static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
{ \
static int op##name##_b_rm_a32(uint32_t fetchdat) { \
uint8_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = getr8(cpu_reg); \
src = geteab(); if (cpu_state.abrt) return 1; \
src = geteab(); \
if (cpu_state.abrt) \
return 1; \
setflags##8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
@@ -191,30 +201,34 @@
return 0; \
} \
\
static int op ## name ## _w_rm_a16(uint32_t fetchdat) \
{ \
static int op##name##_w_rm_a16(uint32_t fetchdat) { \
uint16_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].w; \
src = geteaw(); if (cpu_state.abrt) return 1; \
src = geteaw(); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0); \
return 0; \
} \
static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
{ \
static int op##name##_w_rm_a32(uint32_t fetchdat) { \
uint16_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].w; \
src = geteaw(); if (cpu_state.abrt) return 1; \
src = geteaw(); \
if (cpu_state.abrt) \
return 1; \
setflags##16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
@@ -222,30 +236,34 @@
return 0; \
} \
\
static int op ## name ## _l_rm_a16(uint32_t fetchdat) \
{ \
static int op##name##_l_rm_a16(uint32_t fetchdat) { \
uint32_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].l; \
src = geteal(); if (cpu_state.abrt) return 1; \
src = geteal(); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0); \
return 0; \
} \
static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
{ \
static int op##name##_l_rm_a32(uint32_t fetchdat) { \
uint32_t dst, src; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
dst = cpu_state.regs[cpu_reg].l; \
src = geteal(); if (cpu_state.abrt) return 1; \
src = geteal(); \
if (cpu_state.abrt) \
return 1; \
setflags##32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
@@ -253,11 +271,11 @@
return 0; \
} \
\
static int op ## name ## _AL_imm(uint32_t fetchdat) \
{ \
static int op##name##_AL_imm(uint32_t fetchdat) { \
uint8_t dst = AL; \
uint8_t src = getbytef(); \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##8 flagops; \
AL = operation; \
CLOCK_CYCLES(timing_rr); \
@@ -265,11 +283,11 @@
return 0; \
} \
\
static int op ## name ## _AX_imm(uint32_t fetchdat) \
{ \
static int op##name##_AX_imm(uint32_t fetchdat) { \
uint16_t dst = AX; \
uint16_t src = getwordf(); \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##16 flagops; \
AX = operation; \
CLOCK_CYCLES(timing_rr); \
@@ -277,11 +295,13 @@
return 0; \
} \
\
static int op ## name ## _EAX_imm(uint32_t fetchdat) \
{ \
static int op##name##_EAX_imm(uint32_t fetchdat) { \
uint32_t dst = EAX; \
uint32_t src = getlong(); if (cpu_state.abrt) return 1; \
if (gettempc) tempc = CF_SET() ? 1 : 0; \
uint32_t src = getlong(); \
if (cpu_state.abrt) \
return 1; \
if (gettempc) \
tempc = CF_SET() ? 1 : 0; \
setflags##32 flagops; \
EAX = operation; \
CLOCK_CYCLES(timing_rr); \
@@ -633,53 +653,70 @@ static int opTEST_EAX(uint32_t fetchdat) {
}
#define ARITH_MULTI(ea_width, flag_width) \
dst = getea ## ea_width(); if (cpu_state.abrt) return 1; \
switch (rmdat&0x38) \
{ \
dst = getea##ea_width(); \
if (cpu_state.abrt) \
return 1; \
switch (rmdat & 0x38) { \
case 0x00: /*ADD ea, #*/ \
setea ## ea_width(dst + src); if (cpu_state.abrt) return 1; \
setea##ea_width(dst + src); \
if (cpu_state.abrt) \
return 1; \
setadd##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x08: /*OR ea, #*/ \
dst |= src; \
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x10: /*ADC ea, #*/ \
tempc = CF_SET() ? 1 : 0; \
setea ## ea_width(dst + src + tempc); if (cpu_state.abrt) return 1; \
setea##ea_width(dst + src + tempc); \
if (cpu_state.abrt) \
return 1; \
setadc##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x18: /*SBB ea, #*/ \
tempc = CF_SET() ? 1 : 0; \
setea ## ea_width(dst - (src + tempc)); if (cpu_state.abrt) return 1; \
setea##ea_width(dst - (src + tempc)); \
if (cpu_state.abrt) \
return 1; \
setsbc##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x20: /*AND ea, #*/ \
dst &= src; \
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x28: /*SUB ea, #*/ \
setea ## ea_width(dst - src); if (cpu_state.abrt) return 1; \
setea##ea_width(dst - src); \
if (cpu_state.abrt) \
return 1; \
setsub##flag_width(dst, src); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x30: /*XOR ea, #*/ \
dst ^= src; \
setea ## ea_width(dst); if (cpu_state.abrt) return 1; \
setea##ea_width(dst); \
if (cpu_state.abrt) \
return 1; \
setznp##flag_width(dst); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mr); \
break; \
case 0x38: /*CMP ea, #*/ \
setsub##flag_width(dst, src); \
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
if (is486) \
CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
else \
CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
break; \
}
@@ -696,7 +733,8 @@ static int op80_a16(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
return 0;
}
@@ -713,7 +751,8 @@ static int op80_a32(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
return 0;
}
@@ -730,7 +769,8 @@ static int op81_w_a16(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
return 0;
}
@@ -747,7 +787,8 @@ static int op81_w_a32(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
return 0;
}
@@ -764,7 +805,8 @@ static int op81_l_a16(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
return 0;
}
@@ -781,7 +823,8 @@ static int op81_l_a32(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
return 0;
}
@@ -801,7 +844,8 @@ static int op83_w_a16(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
return 0;
}
@@ -820,7 +864,8 @@ static int op83_w_a32(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
return 0;
}
@@ -840,7 +885,8 @@ static int op83_l_a16(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
return 0;
}
@@ -859,7 +905,8 @@ static int op83_l_a32(uint32_t fetchdat) {
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
return 0;
}

96
includes/private/cpu/x86_ops_bit.h
View File

@@ -82,94 +82,116 @@ static int opBT_l_r_a32(uint32_t fetchdat) {
}
#define opBT(name, operation) \
static int opBT ## name ## _w_r_a16(uint32_t fetchdat) \
{ \
static int opBT##name##_w_r_a16(uint32_t fetchdat) { \
int tempc; \
uint16_t temp; \
\
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
temp = geteaw(); if (cpu_state.abrt) return 1; \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); \
eal_r = eal_w = 0; \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
temp operation(1 << (cpu_state.regs[cpu_reg].w & 15)); \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
else \
cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1, 0, 1, 0, 0); \
return 0; \
} \
static int opBT ## name ## _w_r_a32(uint32_t fetchdat) \
{ \
static int opBT##name##_w_r_a32(uint32_t fetchdat) { \
int tempc; \
uint16_t temp; \
\
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = eal_w = 0; \
temp = geteaw(); if (cpu_state.abrt) return 1; \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); \
eal_r = eal_w = 0; \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
temp operation(1 << (cpu_state.regs[cpu_reg].w & 15)); \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
else \
cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 1, 0, 1, 0, 1); \
return 0; \
} \
static int opBT ## name ## _l_r_a16(uint32_t fetchdat) \
{ \
static int opBT##name##_l_r_a16(uint32_t fetchdat) { \
int tempc; \
uint32_t temp; \
\
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
temp = geteal(); if (cpu_state.abrt) return 1; \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); \
eal_r = eal_w = 0; \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
temp operation(1 << (cpu_state.regs[cpu_reg].l & 31)); \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
else \
cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0, 1, 0, 1, 0); \
return 0; \
} \
static int opBT ## name ## _l_r_a32(uint32_t fetchdat) \
{ \
static int opBT##name##_l_r_a32(uint32_t fetchdat) { \
int tempc; \
uint32_t temp; \
\
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_WRITE(cpu_state.ea_seg); \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = eal_w = 0; \
temp = geteal(); if (cpu_state.abrt) return 1; \
cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); \
eal_r = eal_w = 0; \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
tempc = (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) ? 1 : 0; \
temp operation(1 << (cpu_state.regs[cpu_reg].l & 31)); \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
else cpu_state.flags &= ~C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
else \
cpu_state.flags &= ~C_FLAG; \
\
CLOCK_CYCLES(6); \
PREFETCH_RUN(6, 2, rmdat, 0, 1, 0, 1, 1); \
return 0; \
}
opBT(C, ^=)
opBT(R, &=~)
opBT(S, |=)
opBT(C, ^=) opBT(R, &= ~) opBT(S, |=)
static int opBA_w_a16(uint32_t fetchdat) {
int tempc, count;
@@ -204,7 +226,8 @@ static int opBA_w_a16(uint32_t fetchdat) {
temp ^= (1 << count);
break;
default:pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -253,7 +276,8 @@ static int opBA_w_a32(uint32_t fetchdat) {
temp ^= (1 << count);
break;
default:pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -303,7 +327,8 @@ static int opBA_l_a16(uint32_t fetchdat) {
temp ^= (1 << count);
break;
default:pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -352,7 +377,8 @@ static int opBA_l_a32(uint32_t fetchdat) {
temp ^= (1 << count);
break;
default:pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F BA opcode %02X\n", rmdat & 0x38);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;

12
includes/private/cpu/x86_ops_bitscan.h
View File

@@ -3,22 +3,18 @@
#define BS_common(start, end, dir, dest, time) \
flags_rebuild(); \
instr_cycles = 0; \
if (temp) \
{ \
if (temp) { \
int c; \
cpu_state.flags &= ~Z_FLAG; \
for (c = start; c != end; c += dir) \
{ \
for (c = start; c != end; c += dir) { \
CLOCK_CYCLES(time); \
instr_cycles += time; \
if (temp & (1 << c)) \
{ \
if (temp & (1 << c)) { \
dest = c; \
break; \
} \
} \
} \
else \
} else \
cpu_state.flags |= Z_FLAG;
static int opBSF_w_a16(uint32_t fetchdat) {

120
includes/private/cpu/x86_ops_call.h
View File

@@ -6,26 +6,46 @@
cpu_state.pc = new_pc; \
optype = CALL; \
cgate16 = cgate32 = 0; \
if (msw & 1) loadcscall(new_seg, old_pc); \
else \
{ \
if (msw & 1) \
loadcscall(new_seg, old_pc); \
else { \
loadcs(new_seg); \
cycles -= timing_call_rm; \
} \
optype = 0; \
if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
oldss = ss; \
if (cgate32) \
{ \
uint32_t old_esp = ESP; \
PUSH_L(old_cs); if (cpu_state.abrt) { CS = old_cs; cgate16 = cgate32 = 0; return 1; } \
PUSH_L(old_pc); if (cpu_state.abrt) { CS = old_cs; ESP = old_esp; return 1; } \
if (cpu_state.abrt) { \
cgate16 = cgate32 = 0; \
return 1; \
} \
else \
{ \
oldss = ss; \
if (cgate32) { \
uint32_t old_esp = ESP; \
PUSH_W(old_cs); if (cpu_state.abrt) { CS = old_cs; cgate16 = cgate32 = 0; return 1; } \
PUSH_W(old_pc); if (cpu_state.abrt) { CS = old_cs; ESP = old_esp; return 1; } \
PUSH_L(old_cs); \
if (cpu_state.abrt) { \
CS = old_cs; \
cgate16 = cgate32 = 0; \
return 1; \
} \
PUSH_L(old_pc); \
if (cpu_state.abrt) { \
CS = old_cs; \
ESP = old_esp; \
return 1; \
} \
} else { \
uint32_t old_esp = ESP; \
PUSH_W(old_cs); \
if (cpu_state.abrt) { \
CS = old_cs; \
cgate16 = cgate32 = 0; \
return 1; \
} \
PUSH_W(old_pc); \
if (cpu_state.abrt) { \
CS = old_cs; \
ESP = old_esp; \
return 1; \
} \
}
#define CALL_FAR_l(new_seg, new_pc) \
@@ -34,26 +54,46 @@
cpu_state.pc = new_pc; \
optype = CALL; \
cgate16 = cgate32 = 0; \
if (msw & 1) loadcscall(new_seg, old_pc); \
else \
{ \
if (msw & 1) \
loadcscall(new_seg, old_pc); \
else { \
loadcs(new_seg); \
cycles -= timing_call_rm; \
} \
optype = 0; \
if (cpu_state.abrt) { cgate16 = cgate32 = 0; return 1; } \
oldss = ss; \
if (cgate16) \
{ \
uint32_t old_esp = ESP; \
PUSH_W(old_cs); if (cpu_state.abrt) { CS = old_cs; cgate16 = cgate32 = 0; return 1; } \
PUSH_W(old_pc); if (cpu_state.abrt) { CS = old_cs; ESP = old_esp; return 1; } \
if (cpu_state.abrt) { \
cgate16 = cgate32 = 0; \
return 1; \
} \
else \
{ \
oldss = ss; \
if (cgate16) { \
uint32_t old_esp = ESP; \
PUSH_L(old_cs); if (cpu_state.abrt) { CS = old_cs; cgate16 = cgate32 = 0; return 1; } \
PUSH_L(old_pc); if (cpu_state.abrt) { CS = old_cs; ESP = old_esp; return 1; } \
PUSH_W(old_cs); \
if (cpu_state.abrt) { \
CS = old_cs; \
cgate16 = cgate32 = 0; \
return 1; \
} \
PUSH_W(old_pc); \
if (cpu_state.abrt) { \
CS = old_cs; \
ESP = old_esp; \
return 1; \
} \
} else { \
uint32_t old_esp = ESP; \
PUSH_L(old_cs); \
if (cpu_state.abrt) { \
CS = old_cs; \
cgate16 = cgate32 = 0; \
return 1; \
} \
PUSH_L(old_pc); \
if (cpu_state.abrt) { \
CS = old_cs; \
ESP = old_esp; \
return 1; \
} \
}
static int opCALL_far_w(uint32_t fetchdat) {
@@ -115,7 +155,8 @@ static int opFF_w_a16(uint32_t fetchdat) {
return 1;
setadd16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x08: /*DEC w*/
if (cpu_mod != 3)
@@ -128,7 +169,8 @@ static int opFF_w_a16(uint32_t fetchdat) {
return 1;
setsub16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x10: /*CALL*/
if (cpu_mod != 3)
@@ -229,7 +271,8 @@ static int opFF_w_a32(uint32_t fetchdat) {
return 1;
setadd16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x08: /*DEC w*/
if (cpu_mod != 3)
@@ -242,7 +285,8 @@ static int opFF_w_a32(uint32_t fetchdat) {
return 1;
setsub16nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x10: /*CALL*/
if (cpu_mod != 3)
@@ -344,7 +388,8 @@ static int opFF_l_a16(uint32_t fetchdat) {
return 1;
setadd32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
break;
case 0x08: /*DEC l*/
if (cpu_mod != 3)
@@ -357,7 +402,8 @@ static int opFF_l_a16(uint32_t fetchdat) {
return 1;
setsub32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
break;
case 0x10: /*CALL*/
if (cpu_mod != 3)
@@ -458,7 +504,8 @@ static int opFF_l_a32(uint32_t fetchdat) {
return 1;
setadd32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
break;
case 0x08: /*DEC l*/
if (cpu_mod != 3)
@@ -471,7 +518,8 @@ static int opFF_l_a32(uint32_t fetchdat) {
return 1;
setsub32nc(temp, 1);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
break;
case 0x10: /*CALL*/
if (cpu_mod != 3)

6
includes/private/cpu/x86_ops_cyrix.h
View File

@@ -29,7 +29,8 @@ static void opSVDC_common(uint32_t fetchdat) {
cyrix_write_seg_descriptor(easeg + cpu_state.eaaddr, &cpu_state.seg_gs);
writememw(0, easeg + cpu_state.eaaddr + 8, GS);
break;
default:pclog("opSVDC: unknown rmdat %02x\n", rmdat);
default:
pclog("opSVDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}
@@ -71,7 +72,8 @@ static void opRSDC_common(uint32_t fetchdat) {
case 0x28: /*GS*/
cyrix_load_seg_descriptor(easeg + cpu_state.eaaddr, &cpu_state.seg_gs);
break;
default:pclog("opRSDC: unknown rmdat %02x\n", rmdat);
default:
pclog("opRSDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}

6
includes/private/cpu/x86_ops_flag.h
View File

@@ -23,8 +23,7 @@ static int opCLD(uint32_t fetchdat) {
}
static int opCLI(uint32_t fetchdat) {
if (!IOPLp) {
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME))) {
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) || ((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME))) {
cpu_state.eflags &= ~VIF_FLAG;
} else {
x86gpf(NULL, 0);
@@ -53,8 +52,7 @@ static int opSTD(uint32_t fetchdat) {
}
static int opSTI(uint32_t fetchdat) {
if (!IOPLp) {
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME))) {
if ((!(cpu_state.eflags & VM_FLAG) && (cr4 & CR4_PVI)) || ((cpu_state.eflags & VM_FLAG) && (cr4 & CR4_VME))) {
if (cpu_state.eflags & VIP_FLAG) {
x86gpf(NULL, 0);
return 1;

64
includes/private/cpu/x86_ops_fpu.h
View File

@@ -1,60 +1,28 @@
#ifndef _X86_OPS_FPU_H_
#define _X86_OPS_FPU_H_
static int opESCAPE_d8_a16(uint32_t fetchdat) {
return x86_opcodes_d8_a16[(fetchdat >> 3) & 0x1f](fetchdat);
}
static int opESCAPE_d8_a32(uint32_t fetchdat) {
return x86_opcodes_d8_a32[(fetchdat >> 3) & 0x1f](fetchdat);
}
static int opESCAPE_d8_a16(uint32_t fetchdat) { return x86_opcodes_d8_a16[(fetchdat >> 3) & 0x1f](fetchdat); }
static int opESCAPE_d8_a32(uint32_t fetchdat) { return x86_opcodes_d8_a32[(fetchdat >> 3) & 0x1f](fetchdat); }
static int opESCAPE_d9_a16(uint32_t fetchdat) {
return x86_opcodes_d9_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_d9_a32(uint32_t fetchdat) {
return x86_opcodes_d9_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_d9_a16(uint32_t fetchdat) { return x86_opcodes_d9_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_d9_a32(uint32_t fetchdat) { return x86_opcodes_d9_a32[fetchdat & 0xff](fetchdat); }
static int opESCAPE_da_a16(uint32_t fetchdat) {
return x86_opcodes_da_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_da_a32(uint32_t fetchdat) {
return x86_opcodes_da_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_da_a16(uint32_t fetchdat) { return x86_opcodes_da_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_da_a32(uint32_t fetchdat) { return x86_opcodes_da_a32[fetchdat & 0xff](fetchdat); }
static int opESCAPE_db_a16(uint32_t fetchdat) {
return x86_opcodes_db_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_db_a32(uint32_t fetchdat) {
return x86_opcodes_db_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_db_a16(uint32_t fetchdat) { return x86_opcodes_db_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_db_a32(uint32_t fetchdat) { return x86_opcodes_db_a32[fetchdat & 0xff](fetchdat); }
static int opESCAPE_dc_a16(uint32_t fetchdat) {
return x86_opcodes_dc_a16[(fetchdat >> 3) & 0x1f](fetchdat);
}
static int opESCAPE_dc_a32(uint32_t fetchdat) {
return x86_opcodes_dc_a32[(fetchdat >> 3) & 0x1f](fetchdat);
}
static int opESCAPE_dc_a16(uint32_t fetchdat) { return x86_opcodes_dc_a16[(fetchdat >> 3) & 0x1f](fetchdat); }
static int opESCAPE_dc_a32(uint32_t fetchdat) { return x86_opcodes_dc_a32[(fetchdat >> 3) & 0x1f](fetchdat); }
static int opESCAPE_dd_a16(uint32_t fetchdat) {
return x86_opcodes_dd_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_dd_a32(uint32_t fetchdat) {
return x86_opcodes_dd_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_dd_a16(uint32_t fetchdat) { return x86_opcodes_dd_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_dd_a32(uint32_t fetchdat) { return x86_opcodes_dd_a32[fetchdat & 0xff](fetchdat); }
static int opESCAPE_de_a16(uint32_t fetchdat) {
return x86_opcodes_de_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_de_a32(uint32_t fetchdat) {
return x86_opcodes_de_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_de_a16(uint32_t fetchdat) { return x86_opcodes_de_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_de_a32(uint32_t fetchdat) { return x86_opcodes_de_a32[fetchdat & 0xff](fetchdat); }
static int opESCAPE_df_a16(uint32_t fetchdat) {
return x86_opcodes_df_a16[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_df_a32(uint32_t fetchdat) {
return x86_opcodes_df_a32[fetchdat & 0xff](fetchdat);
}
static int opESCAPE_df_a16(uint32_t fetchdat) { return x86_opcodes_df_a16[fetchdat & 0xff](fetchdat); }
static int opESCAPE_df_a32(uint32_t fetchdat) { return x86_opcodes_df_a32[fetchdat & 0xff](fetchdat); }
static int opWAIT(uint32_t fetchdat) {
if ((cr0 & 0xa) == 0xa) {

3
includes/private/cpu/x86_ops_inc_dec.h
View File

@@ -1,8 +1,7 @@
#ifndef _X86_OPS_INC_DEC_H_
#define _X86_OPS_INC_DEC_H_
#define INC_DEC_OP(name, reg, inc, setflags) \
static int op ## name (uint32_t fetchdat) \
{ \
static int op##name(uint32_t fetchdat) { \
setflags(reg, 1); \
reg += inc; \
CLOCK_CYCLES(timing_rr); \

4
includes/private/cpu/x86_ops_int.h
View File

@@ -60,8 +60,8 @@ static int opINT(uint32_t fetchdat) {
x86gpf_expected(NULL, 0);
return 1;
}
// /*if (temp == 0x10 && AH == 0xe) */pclog("INT %02X : %04X %04X %04X %04X %c %04X:%04X\n", temp, AX, BX, CX, DX, (AL < 32) ? ' ' : AL, CS, pc);
// if (CS == 0x0028 && pc == 0xC03813C0)
// /*if (temp == 0x10 && AH == 0xe) */pclog("INT %02X : %04X %04X %04X %04X %c %04X:%04X\n", temp, AX, BX, CX,
// DX, (AL < 32) ? ' ' : AL, CS, pc); if (CS == 0x0028 && pc == 0xC03813C0)
// output = 3;
/* if (pc == 0x8028009A)
output = 3;

41
includes/private/cpu/x86_ops_jump.h
View File

@@ -18,12 +18,10 @@
#define cond_NLE (((NF_SET()) ? 1 : 0) == ((VF_SET()) ? 1 : 0) && (!ZF_SET()))
#define opJ(condition) \
static int opJ ## condition(uint32_t fetchdat) \
{ \
static int opJ##condition(uint32_t fetchdat) { \
int8_t offset = (int8_t)getbytef(); \
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
cpu_state.pc += offset; \
if (!(cpu_state.op32 & 0x100)) \
cpu_state.pc &= 0xffff; \
@@ -37,12 +35,10 @@
return 0; \
} \
\
static int opJ ## condition ## _w(uint32_t fetchdat) \
{ \
static int opJ##condition##_w(uint32_t fetchdat) { \
int16_t offset = (int16_t)getwordf(); \
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
cpu_state.pc += offset; \
cpu_state.pc &= 0xffff; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
@@ -55,12 +51,12 @@
return 0; \
} \
\
static int opJ ## condition ## _l(uint32_t fetchdat) \
{ \
uint32_t offset = getlong(); if (cpu_state.abrt) return 1; \
static int opJ##condition##_l(uint32_t fetchdat) { \
uint32_t offset = getlong(); \
if (cpu_state.abrt) \
return 1; \
CLOCK_CYCLES(timing_bnt); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
@@ -70,24 +66,9 @@
} \
PREFETCH_RUN(timing_bnt, 5, -1, 0, 0, 0, 0, 0); \
return 0; \
} \
}
opJ(O)
opJ(NO)
opJ(B)
opJ(NB)
opJ(E)
opJ(NE)
opJ(BE)
opJ(NBE)
opJ(S)
opJ(NS)
opJ(P)
opJ(NP)
opJ(L)
opJ(NL)
opJ(LE)
opJ(NLE)
opJ(O) opJ(NO) opJ(B) opJ(NB) opJ(E) opJ(NE) opJ(BE) opJ(NBE) opJ(S) opJ(NS) opJ(P) opJ(NP) opJ(L) opJ(NL) opJ(LE) opJ(NLE)
static int opLOOPNE_w(uint32_t fetchdat) {
int8_t offset = (int8_t)getbytef();

75
includes/private/cpu/x86_ops_misc.h
View File

@@ -54,7 +54,8 @@ static int opF6_a16(uint32_t fetchdat) {
return 1;
switch (rmdat & 0x38) {
case 0x00: /*TEST b,#8*/
case 0x08:src = readmemb(cs, cpu_state.pc);
case 0x08:
src = readmemb(cs, cpu_state.pc);
cpu_state.pc++;
if (cpu_state.abrt)
return 1;
@@ -72,7 +73,8 @@ static int opF6_a16(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x18: /*NEG b*/
if (cpu_mod != 3)
@@ -82,7 +84,8 @@ static int opF6_a16(uint32_t fetchdat) {
return 1;
setsub8(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x20: /*MUL AL,b*/
AX = AL * dst;
@@ -146,7 +149,8 @@ static int opF6_a16(uint32_t fetchdat) {
PREFETCH_RUN(19, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
break;
default:pclog("Bad F6 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F6 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -165,7 +169,8 @@ static int opF6_a32(uint32_t fetchdat) {
return 1;
switch (rmdat & 0x38) {
case 0x00: /*TEST b,#8*/
case 0x08:src = readmemb(cs, cpu_state.pc);
case 0x08:
src = readmemb(cs, cpu_state.pc);
cpu_state.pc++;
if (cpu_state.abrt)
return 1;
@@ -183,7 +188,8 @@ static int opF6_a32(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x18: /*NEG b*/
if (cpu_mod != 3)
@@ -193,7 +199,8 @@ static int opF6_a32(uint32_t fetchdat) {
return 1;
setsub8(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x20: /*MUL AL,b*/
AX = AL * dst;
@@ -257,7 +264,8 @@ static int opF6_a32(uint32_t fetchdat) {
PREFETCH_RUN(19, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
break;
default:pclog("Bad F6 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F6 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -277,7 +285,8 @@ static int opF7_w_a16(uint32_t fetchdat) {
return 1;
switch (rmdat & 0x38) {
case 0x00: /*TEST w*/
case 0x08:src = getword();
case 0x08:
src = getword();
if (cpu_state.abrt)
return 1;
setznp16(src & dst);
@@ -294,7 +303,8 @@ static int opF7_w_a16(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x18: /*NEG w*/
if (cpu_mod != 3)
@@ -304,7 +314,8 @@ static int opF7_w_a16(uint32_t fetchdat) {
return 1;
setsub16(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 0);
break;
case 0x20: /*MUL AX,w*/
templ = AX * dst;
@@ -366,7 +377,8 @@ static int opF7_w_a16(uint32_t fetchdat) {
PREFETCH_RUN(27, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 0);
break;
default:pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -385,7 +397,8 @@ static int opF7_w_a32(uint32_t fetchdat) {
return 1;
switch (rmdat & 0x38) {
case 0x00: /*TEST w*/
case 0x08:src = getword();
case 0x08:
src = getword();
if (cpu_state.abrt)
return 1;
setznp16(src & dst);
@@ -402,7 +415,8 @@ static int opF7_w_a32(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x18: /*NEG w*/
if (cpu_mod != 3)
@@ -412,7 +426,8 @@ static int opF7_w_a32(uint32_t fetchdat) {
return 1;
setsub16(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1,
0, 1);
break;
case 0x20: /*MUL AX,w*/
templ = AX * dst;
@@ -474,7 +489,8 @@ static int opF7_w_a32(uint32_t fetchdat) {
PREFETCH_RUN(27, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, 0, 0, 1);
break;
default:pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -493,7 +509,8 @@ static int opF7_l_a16(uint32_t fetchdat) {
switch (rmdat & 0x38) {
case 0x00: /*TEST l*/
case 0x08:src = getlong();
case 0x08:
src = getlong();
if (cpu_state.abrt)
return 1;
setznp32(src & dst);
@@ -510,7 +527,8 @@ static int opF7_l_a16(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
break;
case 0x18: /*NEG l*/
if (cpu_mod != 3)
@@ -520,7 +538,8 @@ static int opF7_l_a16(uint32_t fetchdat) {
return 1;
setsub32(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 0);
break;
case 0x20: /*MUL EAX,l*/
temp64 = (uint64_t)EAX * (uint64_t)dst;
@@ -563,7 +582,8 @@ static int opF7_l_a16(uint32_t fetchdat) {
PREFETCH_RUN(43, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 0);
break;
default:pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -581,7 +601,8 @@ static int opF7_l_a32(uint32_t fetchdat) {
switch (rmdat & 0x38) {
case 0x00: /*TEST l*/
case 0x08:src = getlong();
case 0x08:
src = getlong();
if (cpu_state.abrt)
return 1;
setznp32(src & dst);
@@ -598,7 +619,8 @@ static int opF7_l_a32(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
break;
case 0x18: /*NEG l*/
if (cpu_mod != 3)
@@ -608,7 +630,8 @@ static int opF7_l_a32(uint32_t fetchdat) {
return 1;
setsub32(0, dst);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_mml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0,
(cpu_mod == 3) ? 0 : 1, 1);
break;
case 0x20: /*MUL EAX,l*/
temp64 = (uint64_t)EAX * (uint64_t)dst;
@@ -651,7 +674,8 @@ static int opF7_l_a32(uint32_t fetchdat) {
PREFETCH_RUN(43, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, 0, 1);
break;
default:pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad F7 opcode %02X\n", rmdat & 0x38);
x86illegal();
}
return 0;
@@ -987,7 +1011,8 @@ static int opSYSENTER(uint32_t fetchdat) {
x86gpf(NULL, 0);
return 1;
}
// pclog("opSYSENTER: CS=%04x EIP=%08x ESP=%08x %04x:%08x %i\n", sysenter_cs, sysenter_eip, sysenter_esp, CS,cpu_state.pc, times);
// pclog("opSYSENTER: CS=%04x EIP=%08x ESP=%08x %04x:%08x %i\n", sysenter_cs, sysenter_eip, sysenter_esp,
// CS,cpu_state.pc, times);
sysenter();
CPU_BLOCK_END();
return 0;

17
includes/private/cpu/x86_ops_mmx.h
View File

@@ -6,27 +6,24 @@
#define USATW(val) (((val) < 0) ? 0 : (((val) > 65535) ? 65535 : (val)))
#define MMX_GETSRC() \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
src = cpu_state.MM[cpu_rm]; \
CLOCK_CYCLES(1); \
} \
else \
{ \
} else { \
SEG_CHECK_READ(cpu_state.ea_seg); \
src.q = readmemq(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 1; \
src.q = readmemq(easeg, cpu_state.eaaddr); \
if (cpu_state.abrt) \
return 1; \
CLOCK_CYCLES(2); \
}
#define MMX_ENTER() \
if (!cpu_has_feature(CPU_FEATURE_MMX)) \
{ \
if (!cpu_has_feature(CPU_FEATURE_MMX)) { \
cpu_state.pc = cpu_state.oldpc; \
x86illegal(); \
return 1; \
} \
if (cr0 & 0xc) \
{ \
if (cr0 & 0xc) { \
x86_int(7); \
return 1; \
} \

12
includes/private/cpu/x86_ops_mmx_arith.h
View File

@@ -233,12 +233,14 @@ static int opPMADDWD_a16(uint32_t fetchdat) {
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
else
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) +
((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
else
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) +
((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
return 0;
}
@@ -252,12 +254,14 @@ static int opPMADDWD_a32(uint32_t fetchdat) {
if (cpu_state.MM[cpu_reg].l[0] == 0x80008000 && src.l[0] == 0x80008000)
cpu_state.MM[cpu_reg].l[0] = 0x80000000;
else
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) + ((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
cpu_state.MM[cpu_reg].sl[0] = ((int32_t)cpu_state.MM[cpu_reg].sw[0] * (int32_t)src.sw[0]) +
((int32_t)cpu_state.MM[cpu_reg].sw[1] * (int32_t)src.sw[1]);
if (cpu_state.MM[cpu_reg].l[1] == 0x80008000 && src.l[1] == 0x80008000)
cpu_state.MM[cpu_reg].l[1] = 0x80000000;
else
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) + ((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
cpu_state.MM[cpu_reg].sl[1] = ((int32_t)cpu_state.MM[cpu_reg].sw[2] * (int32_t)src.sw[2]) +
((int32_t)cpu_state.MM[cpu_reg].sw[3] * (int32_t)src.sw[3]);
return 0;
}

20
includes/private/cpu/x86_ops_mmx_shift.h
View File

@@ -1,15 +1,14 @@
#ifndef _X86_OPS_MMX_SHIFT_H_
#define _X86_OPS_MMX_SHIFT_H_
#define MMX_GETSHIFT() \
if (cpu_mod == 3) \
{ \
if (cpu_mod == 3) { \
shift = cpu_state.MM[cpu_rm].b[0]; \
CLOCK_CYCLES(1); \
} \
else \
{ \
} else { \
SEG_CHECK_READ(cpu_state.ea_seg); \
shift = readmemb(easeg, cpu_state.eaaddr); if (cpu_state.abrt) return 0; \
shift = readmemb(easeg, cpu_state.eaaddr); \
if (cpu_state.abrt) \
return 0; \
CLOCK_CYCLES(2); \
}
@@ -50,7 +49,8 @@ static int opPSxxW_imm(uint32_t fetchdat) {
cpu_state.MM[reg].w[3] <<= shift;
}
break;
default:pclog("Bad PSxxW (0F 71) instruction %02X\n", op);
default:
pclog("Bad PSxxW (0F 71) instruction %02X\n", op);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
return 0;
@@ -206,7 +206,8 @@ static int opPSxxD_imm(uint32_t fetchdat) {
cpu_state.MM[reg].l[1] <<= shift;
}
break;
default:pclog("Bad PSxxD (0F 72) instruction %02X\n", op);
default:
pclog("Bad PSxxD (0F 72) instruction %02X\n", op);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
return 0;
@@ -345,7 +346,8 @@ static int opPSxxQ_imm(uint32_t fetchdat) {
else
cpu_state.MM[reg].q <<= shift;
break;
default:pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
default:
pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
return 0;

70
includes/private/cpu/x86_ops_mov.h
View File

@@ -653,76 +653,72 @@ static int opMOV_r_l_a32(uint32_t fetchdat) {
}
#define opCMOV(condition) \
static int opCMOV ## condition ## _w_a16(uint32_t fetchdat) \
{ \
static int opCMOV##condition##_w_a16(uint32_t fetchdat) { \
fetch_ea_16(fetchdat); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else \
{ \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); if (cpu_state.abrt) return 1; \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV ## condition ## _w_a32(uint32_t fetchdat) \
{ \
static int opCMOV##condition##_w_a32(uint32_t fetchdat) { \
fetch_ea_32(fetchdat); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else \
{ \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); if (cpu_state.abrt) return 1; \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV ## condition ## _l_a16(uint32_t fetchdat) \
{ \
static int opCMOV##condition##_l_a16(uint32_t fetchdat) { \
fetch_ea_16(fetchdat); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else \
{ \
else { \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
temp = geteal(); if (cpu_state.abrt) return 1; \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV ## condition ## _l_a32(uint32_t fetchdat) \
{ \
static int opCMOV##condition##_l_a32(uint32_t fetchdat) { \
fetch_ea_32(fetchdat); \
if (cond_ ## condition) \
{ \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else \
{ \
else { \
uint32_t temp; \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = geteal(); if (cpu_state.abrt) return 1; \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
@@ -730,21 +726,7 @@ static int opMOV_r_l_a32(uint32_t fetchdat) {
return 0; \
}
opCMOV(O)
opCMOV(NO)
opCMOV(B)
opCMOV(NB)
opCMOV(E)
opCMOV(NE)
opCMOV(BE)
opCMOV(NBE)
opCMOV(S)
opCMOV(NS)
opCMOV(P)
opCMOV(NP)
opCMOV(L)
opCMOV(NL)
opCMOV(LE)
opCMOV(NLE)
opCMOV(O) opCMOV(NO) opCMOV(B) opCMOV(NB) opCMOV(E) opCMOV(NE) opCMOV(BE) opCMOV(NBE) opCMOV(S) opCMOV(NS) opCMOV(P) opCMOV(NP)
opCMOV(L) opCMOV(NL) opCMOV(LE) opCMOV(NLE)
#endif /* _X86_OPS_MOV_H_ */

42
includes/private/cpu/x86_ops_mov_ctrl.h
View File

@@ -8,20 +8,24 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat) {
}
fetch_ea_16(fetchdat);
switch (cpu_reg) {
case 0:cpu_state.regs[cpu_rm].l = cr0;
case 0:
cpu_state.regs[cpu_rm].l = cr0;
if (is486)
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:cpu_state.regs[cpu_rm].l = cr2;
case 2:
cpu_state.regs[cpu_rm].l = cr2;
break;
case 3:cpu_state.regs[cpu_rm].l = cr3;
case 3:
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_has_feature(CPU_FEATURE_CR4)) {
cpu_state.regs[cpu_rm].l = cr4;
break;
}
default:pclog("Bad read of CR%i %i\n", rmdat & 7, cpu_reg);
default:
pclog("Bad read of CR%i %i\n", rmdat & 7, cpu_reg);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -38,20 +42,24 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat) {
}
fetch_ea_32(fetchdat);
switch (cpu_reg) {
case 0:cpu_state.regs[cpu_rm].l = cr0;
case 0:
cpu_state.regs[cpu_rm].l = cr0;
if (is486)
cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/
break;
case 2:cpu_state.regs[cpu_rm].l = cr2;
case 2:
cpu_state.regs[cpu_rm].l = cr2;
break;
case 3:cpu_state.regs[cpu_rm].l = cr3;
case 3:
cpu_state.regs[cpu_rm].l = cr3;
break;
case 4:
if (cpu_has_feature(CPU_FEATURE_CR4)) {
cpu_state.regs[cpu_rm].l = cr4;
break;
}
default:pclog("Bad read of CR%i %i\n", rmdat & 7, cpu_reg);
default:
pclog("Bad read of CR%i %i\n", rmdat & 7, cpu_reg);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -115,9 +123,11 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat) {
else
cpu_cur_status &= ~CPU_STATUS_PMODE;
break;
case 2:cr2 = cpu_state.regs[cpu_rm].l;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
break;
case 3:cr3 = cpu_state.regs[cpu_rm].l;
case 3:
cr3 = cpu_state.regs[cpu_rm].l;
flushmmucache();
break;
case 4:
@@ -126,7 +136,8 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat) {
break;
}
default:pclog("Bad load CR%i\n", cpu_reg);
default:
pclog("Bad load CR%i\n", cpu_reg);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;
@@ -164,9 +175,11 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat) {
else
cpu_cur_status &= ~CPU_STATUS_PMODE;
break;
case 2:cr2 = cpu_state.regs[cpu_rm].l;
case 2:
cr2 = cpu_state.regs[cpu_rm].l;
break;
case 3:cr3 = cpu_state.regs[cpu_rm].l;
case 3:
cr3 = cpu_state.regs[cpu_rm].l;
flushmmucache();
break;
case 4:
@@ -175,7 +188,8 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat) {
break;
}
default:pclog("Bad load CR%i\n", cpu_reg);
default:
pclog("Bad load CR%i\n", cpu_reg);
cpu_state.pc = cpu_state.oldpc;
x86illegal();
break;

84
includes/private/cpu/x86_ops_mov_seg.h
View File

@@ -70,32 +70,38 @@ static int opMOV_l_seg_a16(uint32_t fetchdat) {
case 0x00: /*ES*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = ES;
else seteaw(ES);
else
seteaw(ES);
break;
case 0x08: /*CS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = CS;
else seteaw(CS);
else
seteaw(CS);
break;
case 0x18: /*DS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = DS;
else seteaw(DS);
else
seteaw(DS);
break;
case 0x10: /*SS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = SS;
else seteaw(SS);
else
seteaw(SS);
break;
case 0x20: /*FS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = FS;
else seteaw(FS);
else
seteaw(FS);
break;
case 0x28: /*GS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = GS;
else seteaw(GS);
else
seteaw(GS);
break;
}
@@ -112,32 +118,38 @@ static int opMOV_l_seg_a32(uint32_t fetchdat) {
case 0x00: /*ES*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = ES;
else seteaw(ES);
else
seteaw(ES);
break;
case 0x08: /*CS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = CS;
else seteaw(CS);
else
seteaw(CS);
break;
case 0x18: /*DS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = DS;
else seteaw(DS);
else
seteaw(DS);
break;
case 0x10: /*SS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = SS;
else seteaw(SS);
else
seteaw(SS);
break;
case 0x20: /*FS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = FS;
else seteaw(FS);
else
seteaw(FS);
break;
case 0x28: /*GS*/
if (cpu_mod == 3)
cpu_state.regs[cpu_rm].l = GS;
else seteaw(GS);
else
seteaw(GS);
break;
}
@@ -392,16 +404,19 @@ static int opLSS_l_a32(uint32_t fetchdat) {
}
#define opLsel(name, sel) \
static int opL ## name ## _w_a16(uint32_t fetchdat) \
{ \
static int opL##name##_w_a16(uint32_t fetchdat) { \
uint16_t addr, seg; \
\
fetch_ea_16(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmemw(easeg, cpu_state.eaaddr); \
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
seg = readmemw(easeg, cpu_state.eaaddr + 2); \
if (cpu_state.abrt) \
return 1; \
loadseg(seg, &sel); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
@@ -409,16 +424,19 @@ static int opLSS_l_a32(uint32_t fetchdat) {
return 0; \
} \
\
static int opL ## name ## _w_a32(uint32_t fetchdat) \
{ \
static int opL##name##_w_a32(uint32_t fetchdat) { \
uint16_t addr, seg; \
\
fetch_ea_32(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmemw(easeg, cpu_state.eaaddr); \
seg = readmemw(easeg, cpu_state.eaaddr + 2); if (cpu_state.abrt) return 1; \
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
seg = readmemw(easeg, cpu_state.eaaddr + 2); \
if (cpu_state.abrt) \
return 1; \
loadseg(seg, &sel); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = addr; \
\
CLOCK_CYCLES(7); \
@@ -426,8 +444,7 @@ static int opLSS_l_a32(uint32_t fetchdat) {
return 0; \
} \
\
static int opL ## name ## _l_a16(uint32_t fetchdat) \
{ \
static int opL##name##_l_a16(uint32_t fetchdat) { \
uint32_t addr; \
uint16_t seg; \
\
@@ -435,8 +452,12 @@ static int opLSS_l_a32(uint32_t fetchdat) {
SEG_CHECK_READ(cpu_state.ea_seg); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmeml(easeg, cpu_state.eaaddr); \
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
seg = readmemw(easeg, cpu_state.eaaddr + 4); \
if (cpu_state.abrt) \
return 1; \
loadseg(seg, &sel); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
@@ -444,8 +465,7 @@ static int opLSS_l_a32(uint32_t fetchdat) {
return 0; \
} \
\
static int opL ## name ## _l_a32(uint32_t fetchdat) \
{ \
static int opL##name##_l_a32(uint32_t fetchdat) { \
uint32_t addr; \
uint16_t seg; \
\
@@ -453,8 +473,12 @@ static int opLSS_l_a32(uint32_t fetchdat) {
SEG_CHECK_READ(cpu_state.ea_seg); \
ILLEGAL_ON(cpu_mod == 3); \
addr = readmeml(easeg, cpu_state.eaaddr); \
seg = readmemw(easeg, cpu_state.eaaddr + 4); if (cpu_state.abrt) return 1; \
loadseg(seg, &sel); if (cpu_state.abrt) return 1; \
seg = readmemw(easeg, cpu_state.eaaddr + 4); \
if (cpu_state.abrt) \
return 1; \
loadseg(seg, &sel); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = addr; \
\
CLOCK_CYCLES(7); \
@@ -462,8 +486,6 @@ static int opLSS_l_a32(uint32_t fetchdat) {
return 0; \
}
opLsel(ES, cpu_state.seg_es)
opLsel(FS, cpu_state.seg_fs)
opLsel(GS, cpu_state.seg_gs)
opLsel(ES, cpu_state.seg_es) opLsel(FS, cpu_state.seg_fs) opLsel(GS, cpu_state.seg_gs)
#endif /* _X86_OPS_MOV_SEG_H_ */

105
includes/private/cpu/x86_ops_pmode.h
View File

@@ -54,8 +54,7 @@ static int opARPL_a32(uint32_t fetchdat) {
}
#define opLAR(name, fetch_ea, is32, ea32) \
static int opLAR_ ## name(uint32_t fetchdat) \
{ \
static int opLAR_##name(uint32_t fetchdat) { \
int valid; \
uint16_t sel, desc = 0; \
\
@@ -64,35 +63,47 @@ static int opARPL_a32(uint32_t fetchdat) {
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
\
sel = geteaw(); if (cpu_state.abrt) return 1; \
sel = geteaw(); \
if (cpu_state.abrt) \
return 1; \
\
flags_rebuild(); \
if (!(sel & 0xfffc)) { cpu_state.flags &= ~Z_FLAG; return 0; } /*Null selector*/ \
if (!(sel & 0xfffc)) { \
cpu_state.flags &= ~Z_FLAG; \
return 0; \
} /*Null selector*/ \
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
if (valid) \
{ \
if (valid) { \
cpl_override = 1; \
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
cpl_override = 0; if (cpu_state.abrt) return 1; \
cpl_override = 0; \
if (cpu_state.abrt) \
return 1; \
} \
cpu_state.flags &= ~Z_FLAG; \
if ((desc & 0x1f00) == 0x000) valid = 0; \
if ((desc & 0x1f00) == 0x800) valid = 0; \
if ((desc & 0x1f00) == 0xa00) valid = 0; \
if ((desc & 0x1f00) == 0xd00) valid = 0; \
if ((desc & 0x1f00) == 0x000) \
valid = 0; \
if ((desc & 0x1f00) == 0x800) \
valid = 0; \
if ((desc & 0x1f00) == 0xa00) \
valid = 0; \
if ((desc & 0x1f00) == 0xd00) \
valid = 0; \
if ((desc & 0x1c00) < 0x1c00) /*Exclude conforming code segments*/ \
{ \
int dpl = (desc >> 13) & 3; \
if (dpl < CPL || dpl < (sel & 3)) valid = 0; \
if (dpl < CPL || dpl < (sel & 3)) \
valid = 0; \
} \
if (valid) \
{ \
if (valid) { \
cpu_state.flags |= Z_FLAG; \
cpl_override = 1; \
if (is32) \
cpu_state.regs[cpu_reg].l = readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
cpu_state.regs[cpu_reg].l = \
readmeml(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xffff00; \
else \
cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
cpu_state.regs[cpu_reg].w = \
readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4) & 0xff00; \
cpl_override = 0; \
} \
CLOCK_CYCLES(11); \
@@ -100,14 +111,10 @@ static int opARPL_a32(uint32_t fetchdat) {
return cpu_state.abrt; \
}
opLAR(w_a16, fetch_ea_16, 0, 0)
opLAR(w_a32, fetch_ea_32, 0, 1)
opLAR(l_a16, fetch_ea_16, 1, 0)
opLAR(l_a32, fetch_ea_32, 1, 1)
opLAR(w_a16, fetch_ea_16, 0, 0) opLAR(w_a32, fetch_ea_32, 0, 1) opLAR(l_a16, fetch_ea_16, 1, 0) opLAR(l_a32, fetch_ea_32, 1, 1)
#define opLSL(name, fetch_ea, is32, ea32) \
static int opLSL_ ## name(uint32_t fetchdat) \
{ \
static int opLSL_##name(uint32_t fetchdat) { \
int valid; \
uint16_t sel, desc = 0; \
\
@@ -116,40 +123,45 @@ opLAR(l_a32, fetch_ea_32, 1, 1)
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
\
sel = geteaw(); if (cpu_state.abrt) return 1; \
sel = geteaw(); \
if (cpu_state.abrt) \
return 1; \
flags_rebuild(); \
cpu_state.flags &= ~Z_FLAG; \
if (!(sel & 0xfffc)) return 0; /*Null selector*/ \
if (!(sel & 0xfffc)) \
return 0; /*Null selector*/ \
valid = (sel & ~7) < ((sel & 4) ? ldt.limit : gdt.limit); \
if (valid) \
{ \
if (valid) { \
cpl_override = 1; \
desc = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 4); \
cpl_override = 0; if (cpu_state.abrt) return 1; \
cpl_override = 0; \
if (cpu_state.abrt) \
return 1; \
} \
if ((desc & 0x1400) == 0x400) valid = 0; /*Interrupt or trap or call gate*/ \
if ((desc & 0x1f00) == 0x000) valid = 0; /*Invalid*/ \
if ((desc & 0x1f00) == 0xa00) valid = 0; /*Invalid*/ \
if ((desc & 0x1400) == 0x400) \
valid = 0; /*Interrupt or trap or call gate*/ \
if ((desc & 0x1f00) == 0x000) \
valid = 0; /*Invalid*/ \
if ((desc & 0x1f00) == 0xa00) \
valid = 0; /*Invalid*/ \
if ((desc & 0x1c00) != 0x1c00) /*Exclude conforming code segments*/ \
{ \
int rpl = (desc >> 13) & 3; \
if (rpl < CPL || rpl < (sel & 3)) valid = 0; \
if (rpl < CPL || rpl < (sel & 3)) \
valid = 0; \
} \
if (valid) \
{ \
if (valid) { \
cpu_state.flags |= Z_FLAG; \
cpl_override = 1; \
if (is32) \
{ \
if (is32) { \
cpu_state.regs[cpu_reg].l = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
cpu_state.regs[cpu_reg].l |= (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
if (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0x80) \
{ \
cpu_state.regs[cpu_reg].l |= \
(readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0xF) << 16; \
if (readmemb(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7) + 6) & 0x80) { \
cpu_state.regs[cpu_reg].l <<= 12; \
cpu_state.regs[cpu_reg].l |= 0xFFF; \
} \
} \
else \
} else \
cpu_state.regs[cpu_reg].w = readmemw(0, ((sel & 4) ? ldt.base : gdt.base) + (sel & ~7)); \
cpl_override = 0; \
} \
@@ -158,9 +170,7 @@ opLAR(l_a32, fetch_ea_32, 1, 1)
return cpu_state.abrt; \
}
opLSL(w_a16, fetch_ea_16, 0, 0)
opLSL(w_a32, fetch_ea_32, 0, 1)
opLSL(l_a16, fetch_ea_16, 1, 0)
opLSL(w_a16, fetch_ea_16, 0, 0) opLSL(w_a32, fetch_ea_32, 0, 1) opLSL(l_a16, fetch_ea_16, 1, 0)
opLSL(l_a32, fetch_ea_32, 1, 1)
static int op0F00_common(uint32_t fetchdat, int ea32) {
@@ -315,7 +325,8 @@ static int op0F00_common(uint32_t fetchdat, int ea32) {
PREFETCH_RUN(20, 2, rmdat, (cpu_mod == 3) ? 1 : 2, 0, 0, 0, ea32);
break;
default:pclog("Bad 0F 00 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F 00 opcode %02X\n", rmdat & 0x38);
cpu_state.pc -= 3;
x86illegal();
break;
@@ -415,7 +426,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) {
seteaw(msw);
else if (is386)
seteaw(msw | 0xFF00);
else seteaw(msw | 0xFFF0);
else
seteaw(msw | 0xFFF0);
CLOCK_CYCLES(2);
PREFETCH_RUN(2, 2, rmdat, 0, 0, (cpu_mod == 3) ? 0 : 1, 0, ea32);
break;
@@ -459,7 +471,8 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) {
break;
}
default:pclog("Bad 0F 01 opcode %02X\n", rmdat & 0x38);
default:
pclog("Bad 0F 01 opcode %02X\n", rmdat & 0x38);
cpu_state.pc -= 3;
x86illegal();
break;

49
includes/private/cpu/x86_ops_prefix.h
View File

@@ -1,10 +1,10 @@
#ifndef _X86_OPS_PREFIX_H_
#define _X86_OPS_PREFIX_H_
#define op_seg(name, seg, opcode_table, normal_opcode_table) \
static int op ## name ## _w_a16(uint32_t fetchdat) \
{ \
static int op##name##_w_a16(uint32_t fetchdat) { \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (cpu_state.abrt) return 1; \
if (cpu_state.abrt) \
return 1; \
cpu_state.pc++; \
\
cpu_state.ea_seg = &seg; \
@@ -17,10 +17,10 @@ static int op ## name ## _w_a16(uint32_t fetchdat) \
return normal_opcode_table[fetchdat & 0xff](fetchdat >> 8); \
} \
\
static int op ## name ## _l_a16(uint32_t fetchdat) \
{ \
static int op##name##_l_a16(uint32_t fetchdat) { \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (cpu_state.abrt) return 1; \
if (cpu_state.abrt) \
return 1; \
cpu_state.pc++; \
\
cpu_state.ea_seg = &seg; \
@@ -33,10 +33,10 @@ static int op ## name ## _l_a16(uint32_t fetchdat) \
return normal_opcode_table[(fetchdat & 0xff) | 0x100](fetchdat >> 8); \
} \
\
static int op ## name ## _w_a32(uint32_t fetchdat) \
{ \
static int op##name##_w_a32(uint32_t fetchdat) { \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (cpu_state.abrt) return 1; \
if (cpu_state.abrt) \
return 1; \
cpu_state.pc++; \
\
cpu_state.ea_seg = &seg; \
@@ -49,10 +49,10 @@ static int op ## name ## _w_a32(uint32_t fetchdat) \
return normal_opcode_table[(fetchdat & 0xff) | 0x200](fetchdat >> 8); \
} \
\
static int op ## name ## _l_a32(uint32_t fetchdat) \
{ \
static int op##name##_l_a32(uint32_t fetchdat) { \
fetchdat = fastreadl(cs + cpu_state.pc); \
if (cpu_state.abrt) return 1; \
if (cpu_state.abrt) \
return 1; \
cpu_state.pc++; \
\
cpu_state.ea_seg = &seg; \
@@ -65,22 +65,19 @@ static int op ## name ## _l_a32(uint32_t fetchdat) \
return normal_opcode_table[(fetchdat & 0xff) | 0x300](fetchdat >> 8); \
}
op_seg(CS, cpu_state.seg_cs, x86_opcodes, x86_opcodes)
op_seg(DS, cpu_state.seg_ds, x86_opcodes, x86_opcodes)
op_seg(ES, cpu_state.seg_es, x86_opcodes, x86_opcodes)
op_seg(FS, cpu_state.seg_fs, x86_opcodes, x86_opcodes)
op_seg(GS, cpu_state.seg_gs, x86_opcodes, x86_opcodes)
op_seg(SS, cpu_state.seg_ss, x86_opcodes, x86_opcodes)
op_seg(CS, cpu_state.seg_cs, x86_opcodes, x86_opcodes) op_seg(DS, cpu_state.seg_ds, x86_opcodes, x86_opcodes)
op_seg(ES, cpu_state.seg_es, x86_opcodes, x86_opcodes) op_seg(FS, cpu_state.seg_fs, x86_opcodes, x86_opcodes) op_seg(
GS, cpu_state.seg_gs, x86_opcodes, x86_opcodes) op_seg(SS, cpu_state.seg_ss, x86_opcodes, x86_opcodes)
op_seg(CS_REPE, cpu_state.seg_cs, x86_opcodes_REPE, x86_opcodes)
op_seg(DS_REPE, cpu_state.seg_ds, x86_opcodes_REPE, x86_opcodes)
op_seg(ES_REPE, cpu_state.seg_es, x86_opcodes_REPE, x86_opcodes)
op_seg(FS_REPE, cpu_state.seg_fs, x86_opcodes_REPE, x86_opcodes)
op_seg(GS_REPE, cpu_state.seg_gs, x86_opcodes_REPE, x86_opcodes)
op_seg(SS_REPE, cpu_state.seg_ss, x86_opcodes_REPE, x86_opcodes)
op_seg(CS_REPE, cpu_state.seg_cs, x86_opcodes_REPE,
x86_opcodes) op_seg(DS_REPE, cpu_state.seg_ds, x86_opcodes_REPE,
x86_opcodes) op_seg(ES_REPE, cpu_state.seg_es, x86_opcodes_REPE, x86_opcodes)
op_seg(FS_REPE, cpu_state.seg_fs, x86_opcodes_REPE,
x86_opcodes) op_seg(GS_REPE, cpu_state.seg_gs, x86_opcodes_REPE,
x86_opcodes) op_seg(SS_REPE, cpu_state.seg_ss, x86_opcodes_REPE, x86_opcodes)
op_seg(CS_REPNE, cpu_state.seg_cs, x86_opcodes_REPNE, x86_opcodes)
op_seg(DS_REPNE, cpu_state.seg_ds, x86_opcodes_REPNE, x86_opcodes)
op_seg(CS_REPNE, cpu_state.seg_cs, x86_opcodes_REPNE,
x86_opcodes) op_seg(DS_REPNE, cpu_state.seg_ds, x86_opcodes_REPNE, x86_opcodes)
op_seg(ES_REPNE, cpu_state.seg_es, x86_opcodes_REPNE, x86_opcodes)
op_seg(FS_REPNE, cpu_state.seg_fs, x86_opcodes_REPNE, x86_opcodes)
op_seg(GS_REPNE, cpu_state.seg_gs, x86_opcodes_REPNE, x86_opcodes)

514
includes/private/cpu/x86_ops_rep.h
View File

@@ -1,69 +1,73 @@
#ifndef _X86_OPS_REP_H_
#define _X86_OPS_REP_H_
#define REP_OPS(size, CNT_REG, SRC_REG, DEST_REG) \
static int opREP_INSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_INSB_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint8_t temp; \
\
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
temp = inb(DX); \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
writememb(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
if (cpu_state.flags & D_FLAG) \
DEST_REG--; \
else \
DEST_REG++; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
reads++; \
writes++; \
total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_INSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_INSW_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint16_t temp; \
\
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
check_io_perm(DX + 1); \
temp = inw(DX); \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
writememw(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 2; \
else \
DEST_REG += 2; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
reads++; \
writes++; \
total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_INSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_INSL_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint32_t temp; \
\
SEG_CHECK_WRITE(&cpu_state.seg_es); \
@@ -72,17 +76,22 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
check_io_perm(DX + 2); \
check_io_perm(DX + 3); \
temp = inl(DX); \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
writememl(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 4; \
else \
DEST_REG += 4; \
CNT_REG--; \
cycles -= 15; \
reads++; writes++; total_cycles += 15; \
reads++; \
writes++; \
total_cycles += 15; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
@@ -90,82 +99,91 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
return cpu_state.abrt; \
} \
\
static int opREP_OUTSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_OUTSB_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint8_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
check_io_perm(DX); \
outb(DX, temp); \
if (cpu_state.flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
if (cpu_state.flags & D_FLAG) \
SRC_REG--; \
else \
SRC_REG++; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
reads++; \
writes++; \
total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_OUTSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_OUTSW_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
check_io_perm(DX); \
check_io_perm(DX + 1); \
outw(DX, temp); \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
if (cpu_state.flags & D_FLAG) \
SRC_REG -= 2; \
else \
SRC_REG += 2; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
reads++; \
writes++; \
total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_OUTSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_OUTSL_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
\
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
check_io_perm(DX); \
check_io_perm(DX + 1); \
check_io_perm(DX + 2); \
check_io_perm(DX + 3); \
outl(DX, temp); \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
if (cpu_state.flags & D_FLAG) \
SRC_REG -= 4; \
else \
SRC_REG += 4; \
CNT_REG--; \
cycles -= 14; \
reads++; writes++; total_cycles += 14; \
reads++; \
writes++; \
total_cycles += 14; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
@@ -173,114 +191,135 @@ static int opREP_OUTSL_ ## size(uint32_t fetchdat)
return cpu_state.abrt; \
} \
\
static int opREP_MOVSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_MOVSB_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
uint8_t temp; \
\
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememb(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
writememb(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG--; \
SRC_REG--; \
} else { \
DEST_REG++; \
SRC_REG++; \
} \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
reads++; \
writes++; \
total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_MOVSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_MOVSW_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
uint16_t temp; \
\
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememw(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
writememw(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG -= 2; \
SRC_REG -= 2; \
} else { \
DEST_REG += 2; \
SRC_REG += 2; \
} \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
reads++; \
writes++; \
total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_MOVSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_MOVSL_##size(uint32_t fetchdat) { \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
uint32_t temp; \
\
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
writememl(es, DEST_REG, temp); if (cpu_state.abrt) return 1; \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
writememl(es, DEST_REG, temp); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG -= 4; \
SRC_REG -= 4; \
} else { \
DEST_REG += 4; \
SRC_REG += 4; \
} \
CNT_REG--; \
cycles -= is486 ? 3 : 4; \
ins++; \
reads++; writes++; total_cycles += is486 ? 3 : 4; \
reads++; \
writes++; \
total_cycles += is486 ? 3 : 4; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
@@ -288,91 +327,96 @@ static int opREP_MOVSL_ ## size(uint32_t fetchdat)
return cpu_state.abrt; \
} \
\
\
static int opREP_STOSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_STOSB_##size(uint32_t fetchdat) { \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
writememb(es, DEST_REG, AL); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
writememb(es, DEST_REG, AL); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
DEST_REG--; \
else \
DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
writes++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_STOSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_STOSW_##size(uint32_t fetchdat) { \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
writememw(es, DEST_REG, AX); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 2; \
else \
DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
writes++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, writes, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_STOSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_STOSL_##size(uint32_t fetchdat) { \
int writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
while (CNT_REG > 0) { \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
writememl(es, DEST_REG, EAX); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 4; \
else \
DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
writes++; total_cycles += is486 ? 4 : 5; \
writes++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, 0, 0, writes, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
@@ -380,180 +424,200 @@ static int opREP_STOSL_ ## size(uint32_t fetchdat)
return cpu_state.abrt; \
} \
\
static int opREP_LODSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_LODSB_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG--; \
else SRC_REG++; \
while (CNT_REG > 0) { \
AL = readmemb(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
SRC_REG--; \
else \
SRC_REG++; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
reads++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_LODSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_LODSW_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
while (CNT_REG > 0) { \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
SRC_REG -= 2; \
else \
SRC_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
reads++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_LODSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_LODSL_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
cycles_end = cycles + 1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
while (CNT_REG > 0) { \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); \
if (cpu_state.abrt) \
return 1; \
if (cpu_state.flags & D_FLAG) \
SRC_REG -= 4; \
else \
SRC_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 4 : 5; \
reads++; total_cycles += is486 ? 4 : 5; \
reads++; \
total_cycles += is486 ? 4 : 5; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if (CNT_REG > 0) \
{ \
if (CNT_REG > 0) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
}
#define REP_OPS_CMPS_SCAS(size, CNT_REG, SRC_REG, DEST_REG, FV) \
static int opREP_CMPSB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_CMPSB_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
uint8_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
temp = readmemb(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmemb(es, DEST_REG); if (cpu_state.abrt) return 1; \
temp2 = readmemb(es, DEST_REG); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG--; \
SRC_REG--; \
} else { \
DEST_REG++; \
SRC_REG++; \
} \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
reads += 2; \
total_cycles += is486 ? 7 : 9; \
setsub8(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_CMPSW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_CMPSW_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
uint16_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmemw(es, DEST_REG); if (cpu_state.abrt) return 1; \
temp2 = readmemw(es, DEST_REG); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG -= 2; \
SRC_REG -= 2; \
} else { \
DEST_REG += 2; \
SRC_REG += 2; \
} \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
reads += 2; \
total_cycles += is486 ? 7 : 9; \
setsub16(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_CMPSL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_CMPSL_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
uint32_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); \
temp2 = readmeml(es, DEST_REG); if (cpu_state.abrt) return 1; \
temp2 = readmeml(es, DEST_REG); \
if (cpu_state.abrt) \
return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
if (cpu_state.flags & D_FLAG) { \
DEST_REG -= 4; \
SRC_REG -= 4; \
} else { \
DEST_REG += 4; \
SRC_REG += 4; \
} \
CNT_REG--; \
cycles -= is486 ? 7 : 9; \
reads += 2; total_cycles += is486 ? 7 : 9; \
reads += 2; \
total_cycles += is486 ? 7 : 9; \
setsub32(temp, temp2); \
tempz = (ZF_SET()) ? 1 : 0; \
} \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
@@ -561,8 +625,7 @@ static int opREP_CMPSL_ ## size(uint32_t fetchdat)
return cpu_state.abrt; \
} \
\
static int opREP_SCASB_ ## size(uint32_t fetchdat) \
{ \
static int opREP_SCASB_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
@@ -570,32 +633,34 @@ static int opREP_SCASB_ ## size(uint32_t fetchdat)
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint8_t temp = readmemb(es, DEST_REG); if (cpu_state.abrt) break;\
while ((CNT_REG > 0) && (FV == tempz)) { \
uint8_t temp = readmemb(es, DEST_REG); \
if (cpu_state.abrt) \
break; \
setsub8(AL, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (cpu_state.flags & D_FLAG) DEST_REG--; \
else DEST_REG++; \
if (cpu_state.flags & D_FLAG) \
DEST_REG--; \
else \
DEST_REG++; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
reads++; \
total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_SCASW_ ## size(uint32_t fetchdat) \
{ \
static int opREP_SCASW_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
@@ -603,32 +668,34 @@ static int opREP_SCASW_ ## size(uint32_t fetchdat)
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
while ((CNT_REG > 0) && (FV == tempz)) { \
uint16_t temp = readmemw(es, DEST_REG); \
if (cpu_state.abrt) \
break; \
setsub16(AX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 2; \
else \
DEST_REG += 2; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
reads++; \
total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, reads, 0, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \
} \
return cpu_state.abrt; \
} \
static int opREP_SCASL_ ## size(uint32_t fetchdat) \
{ \
static int opREP_SCASL_##size(uint32_t fetchdat) { \
int reads = 0, total_cycles = 0, tempz; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
if (trap) \
@@ -636,24 +703,27 @@ static int opREP_SCASL_ ## size(uint32_t fetchdat)
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
while ((CNT_REG > 0) && (FV == tempz)) { \
uint32_t temp = readmeml(es, DEST_REG); \
if (cpu_state.abrt) \
break; \
setsub32(EAX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
if (cpu_state.flags & D_FLAG) \
DEST_REG -= 4; \
else \
DEST_REG += 4; \
CNT_REG--; \
cycles -= is486 ? 5 : 8; \
reads++; total_cycles += is486 ? 5 : 8; \
reads++; \
total_cycles += is486 ? 5 : 8; \
ins++; \
if (cycles < cycles_end) \
break; \
} \
ins--; \
PREFETCH_RUN(total_cycles, 1, -1, 0, reads, 0, 0, 0); \
if ((CNT_REG > 0) && (FV == tempz)) \
{ \
if ((CNT_REG > 0) && (FV == tempz)) { \
CPU_BLOCK_END(); \
cpu_state.pc = cpu_state.oldpc; \
return 1; \

38
includes/private/cpu/x86_ops_ret.h
View File

@@ -1,45 +1,43 @@
#ifndef _X86_OPS_RET_H_
#define _X86_OPS_RET_H_
#define RETF_a16(stack_offset) \
if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
{ \
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG)) { \
pmoderetf(0, stack_offset); \
return 1; \
} \
if (stack32) \
{ \
if (stack32) { \
cpu_state.pc = readmemw(ss, ESP); \
loadcs(readmemw(ss, ESP + 2)); \
} \
else \
{ \
} else { \
cpu_state.pc = readmemw(ss, SP); \
loadcs(readmemw(ss, SP + 2)); \
} \
if (cpu_state.abrt) return 1; \
if (stack32) ESP += 4 + stack_offset; \
else SP += 4 + stack_offset; \
if (cpu_state.abrt) \
return 1; \
if (stack32) \
ESP += 4 + stack_offset; \
else \
SP += 4 + stack_offset; \
cycles -= timing_retf_rm;
#define RETF_a32(stack_offset) \
if ((msw&1) && !(cpu_state.eflags&VM_FLAG)) \
{ \
if ((msw & 1) && !(cpu_state.eflags & VM_FLAG)) { \
pmoderetf(1, stack_offset); \
return 1; \
} \
if (stack32) \
{ \
if (stack32) { \
cpu_state.pc = readmeml(ss, ESP); \
loadcs(readmeml(ss, ESP + 4) & 0xffff); \
} \
else \
{ \
} else { \
cpu_state.pc = readmeml(ss, SP); \
loadcs(readmeml(ss, SP + 4) & 0xffff); \
} \
if (cpu_state.abrt) return 1; \
if (stack32) ESP += 8 + stack_offset; \
else SP += 8 + stack_offset; \
if (cpu_state.abrt) \
return 1; \
if (stack32) \
ESP += 8 + stack_offset; \
else \
SP += 8 + stack_offset; \
cycles -= timing_retf_rm;
static int opRETF_a16(uint32_t fetchdat) {

24
includes/private/cpu/x86_ops_set.h
View File

@@ -1,8 +1,7 @@
#ifndef _X86_OPS_SET_H_
#define _X86_OPS_SET_H_
#define opSET(condition) \
static int opSET ## condition ## _a16(uint32_t fetchdat) \
{ \
static int opSET##condition##_a16(uint32_t fetchdat) { \
fetch_ea_16(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
@@ -11,8 +10,7 @@
return cpu_state.abrt; \
} \
\
static int opSET ## condition ## _a32(uint32_t fetchdat) \
{ \
static int opSET##condition##_a32(uint32_t fetchdat) { \
fetch_ea_32(fetchdat); \
if (cpu_mod != 3) \
SEG_CHECK_READ(cpu_state.ea_seg); \
@@ -21,21 +19,7 @@
return cpu_state.abrt; \
}
opSET(O)
opSET(NO)
opSET(B)
opSET(NB)
opSET(E)
opSET(NE)
opSET(BE)
opSET(NBE)
opSET(S)
opSET(NS)
opSET(P)
opSET(NP)
opSET(L)
opSET(NL)
opSET(LE)
opSET(NLE)
opSET(O) opSET(NO) opSET(B) opSET(NB) opSET(E) opSET(NE) opSET(BE) opSET(NBE) opSET(S) opSET(NS) opSET(P) opSET(NP) opSET(L)
opSET(NL) opSET(LE) opSET(NLE)
#endif /* _X86_OPS_SET_H_ */

325
includes/private/cpu/x86_ops_shift.h
View File

@@ -3,76 +3,102 @@
#define OP_SHIFT_b(c, ea32) \
{ \
uint8_t temp_orig = temp; \
if (!c) return 0; \
if (!c) \
return 0; \
flags_rebuild(); \
switch (rmdat & 0x38) \
{ \
switch (rmdat & 0x38) { \
case 0x00: /*ROL b, c*/ \
temp = (temp << (c & 7)) | (temp >> (8 - (c & 7))); \
seteab(temp); if (cpu_state.abrt) return 1; \
seteab(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROL8, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x08: /*ROR b,CL*/ \
temp = (temp >> (c & 7)) | (temp << (8 - (c & 7))); \
seteab(temp); if (cpu_state.abrt) return 1; \
seteab(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROR8, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x10: /*RCL b,CL*/ \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 1 : 0; \
temp2 = temp & 0x80; \
temp = (temp << 1) | tempc; \
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
seteab(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 7)) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x18: /*RCR b,CL*/ \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 0x80 : 0; \
temp2 = temp & 1; \
temp = (temp >> 1) | tempc; \
c--; \
} \
seteab(temp); if (cpu_state.abrt) return 1; \
seteab(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x20: case 0x30: /*SHL b,CL*/ \
seteab(temp << c); if (cpu_state.abrt) return 1; \
case 0x20: \
case 0x30: /*SHL b,CL*/ \
seteab(temp << c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHL8, temp_orig, c, (temp << c) & 0xff); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x28: /*SHR b,CL*/ \
seteab(temp >> c); if (cpu_state.abrt) return 1; \
seteab(temp >> c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHR8, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x38: /*SAR b,CL*/ \
temp = (int8_t)temp >> c; \
seteab(temp); if (cpu_state.abrt) return 1; \
seteab(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SAR8, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
} \
}
@@ -80,76 +106,102 @@
#define OP_SHIFT_w(c, ea32) \
{ \
uint16_t temp_orig = temp; \
if (!c) return 0; \
if (!c) \
return 0; \
flags_rebuild(); \
switch (rmdat & 0x38) \
{ \
switch (rmdat & 0x38) { \
case 0x00: /*ROL w, c*/ \
temp = (temp << (c & 15)) | (temp >> (16 - (c & 15))); \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROL16, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x08: /*ROR w,CL*/ \
temp = (temp >> (c & 15)) | (temp << (16 - (c & 15))); \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROR16, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x10: /*RCL w, c*/ \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 1 : 0; \
temp2 = temp & 0x8000; \
temp = (temp << 1) | tempc; \
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 15)) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x18: /*RCR w, c*/ \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 0x8000 : 0; \
temp2 = temp & 1; \
temp = (temp >> 1) | tempc; \
c--; \
} \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x4000) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x20: case 0x30: /*SHL w, c*/ \
seteaw(temp << c); if (cpu_state.abrt) return 1; \
case 0x20: \
case 0x30: /*SHL w, c*/ \
seteaw(temp << c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHL16, temp_orig, c, (temp << c) & 0xffff); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x28: /*SHR w, c*/ \
seteaw(temp >> c); if (cpu_state.abrt) return 1; \
seteaw(temp >> c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHR16, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x38: /*SAR w, c*/ \
temp = (int16_t)temp >> c; \
seteaw(temp); if (cpu_state.abrt) return 1; \
seteaw(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SAR16, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
} \
}
@@ -157,76 +209,102 @@
#define OP_SHIFT_l(c, ea32) \
{ \
uint32_t temp_orig = temp; \
if (!c) return 0; \
if (!c) \
return 0; \
flags_rebuild(); \
switch (rmdat & 0x38) \
{ \
switch (rmdat & 0x38) { \
case 0x00: /*ROL l, c*/ \
temp = (temp << c) | (temp >> (32 - c)); \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROL32, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x08: /*ROR l,CL*/ \
temp = (temp >> c) | (temp << (32 - c)); \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_rotate(FLAGS_ROR32, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0, \
ea32); \
break; \
case 0x10: /*RCL l, c*/ \
temp2 = CF_SET(); \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 1 : 0; \
temp2 = temp & 0x80000000; \
temp = (temp << 1) | tempc; \
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((cpu_state.flags & C_FLAG) ^ (temp >> 31)) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, \
ea32); \
break; \
case 0x18: /*RCR l, c*/ \
temp2 = cpu_state.flags & C_FLAG; \
if (is486) CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) \
{ \
if (is486) \
CLOCK_CYCLES_ALWAYS(c); \
while (c > 0) { \
tempc = temp2 ? 0x80000000 : 0; \
temp2 = temp & 1; \
temp = (temp >> 1) | tempc; \
c--; \
} \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
cpu_state.flags &= ~(C_FLAG | V_FLAG); \
if (temp2) cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) cpu_state.flags |= V_FLAG; \
if (temp2) \
cpu_state.flags |= C_FLAG; \
if ((temp ^ (temp >> 1)) & 0x40000000) \
cpu_state.flags |= V_FLAG; \
CLOCK_CYCLES((cpu_mod == 3) ? 9 : 10); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 9 : 10, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, \
ea32); \
break; \
case 0x20: case 0x30: /*SHL l, c*/ \
seteal(temp << c); if (cpu_state.abrt) return 1; \
case 0x20: \
case 0x30: /*SHL l, c*/ \
seteal(temp << c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHL32, temp_orig, c, temp << c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, \
ea32); \
break; \
case 0x28: /*SHR l, c*/ \
seteal(temp >> c); if (cpu_state.abrt) return 1; \
seteal(temp >> c); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SHR32, temp_orig, c, temp >> c); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, \
ea32); \
break; \
case 0x38: /*SAR l, c*/ \
temp = (int32_t)temp >> c; \
seteal(temp); if (cpu_state.abrt) return 1; \
seteal(temp); \
if (cpu_state.abrt) \
return 1; \
set_flags_shift(FLAGS_SAR32, temp_orig, c, temp); \
CLOCK_CYCLES((cpu_mod == 3) ? 3 : 7); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, ea32); \
PREFETCH_RUN((cpu_mod == 3) ? 3 : 7, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, \
ea32); \
break; \
} \
}
@@ -511,59 +589,76 @@ static int opD3_l_a32(uint32_t fetchdat) {
}
#define SHLD_w() \
if (count) \
{ \
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
if (count) { \
uint16_t tempw = geteaw(); \
if (cpu_state.abrt) \
return 1; \
int tempc = ((tempw << (count - 1)) & (1 << 15)) ? 1 : 0; \
uint32_t templ = (tempw << 16) | cpu_state.regs[cpu_reg].w; \
if (count <= 16) tempw = templ >> (16 - count); \
else tempw = (templ << count) >> 16; \
seteaw(tempw); if (cpu_state.abrt) return 1; \
if (count <= 16) \
tempw = templ >> (16 - count); \
else \
tempw = (templ << count) >> 16; \
seteaw(tempw); \
if (cpu_state.abrt) \
return 1; \
setznp16(tempw); \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
}
#define SHLD_l() \
if (count) \
{ \
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
if (count) { \
uint32_t templ = geteal(); \
if (cpu_state.abrt) \
return 1; \
int tempc = ((templ << (count - 1)) & (1 << 31)) ? 1 : 0; \
templ = (templ << count) | (cpu_state.regs[cpu_reg].l >> (32 - count)); \
seteal(templ); if (cpu_state.abrt) return 1; \
seteal(templ); \
if (cpu_state.abrt) \
return 1; \
setznp32(templ); \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
}
#define SHRD_w() \
if (count) \
{ \
uint16_t tempw = geteaw(); if (cpu_state.abrt) return 1; \
if (count) { \
uint16_t tempw = geteaw(); \
if (cpu_state.abrt) \
return 1; \
int tempc = (tempw >> (count - 1)) & 1; \
uint32_t templ = tempw | (cpu_state.regs[cpu_reg].w << 16); \
tempw = templ >> count; \
seteaw(tempw); if (cpu_state.abrt) return 1; \
seteaw(tempw); \
if (cpu_state.abrt) \
return 1; \
setznp16(tempw); \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
}
#define SHRD_l() \
if (count) \
{ \
uint32_t templ = geteal(); if (cpu_state.abrt) return 1; \
if (count) { \
uint32_t templ = geteal(); \
if (cpu_state.abrt) \
return 1; \
int tempc = (templ >> (count - 1)) & 1; \
templ = (templ >> count) | (cpu_state.regs[cpu_reg].l << (32 - count)); \
seteal(templ); if (cpu_state.abrt) return 1; \
seteal(templ); \
if (cpu_state.abrt) \
return 1; \
setznp32(templ); \
flags_rebuild(); \
if (tempc) cpu_state.flags |= C_FLAG; \
if (tempc) \
cpu_state.flags |= C_FLAG; \
}
#define opSHxD(operation) \
static int op ## operation ## _i_a16(uint32_t fetchdat) \
{ \
static int op##operation##_i_a16(uint32_t fetchdat) { \
int count; \
\
fetch_ea_16(fetchdat); \
@@ -576,8 +671,7 @@ static int opD3_l_a32(uint32_t fetchdat) {
PREFETCH_RUN(3, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0); \
return 0; \
} \
static int op ## operation ## _CL_a16(uint32_t fetchdat) \
{ \
static int op##operation##_CL_a16(uint32_t fetchdat) { \
int count; \
\
fetch_ea_16(fetchdat); \
@@ -590,8 +684,7 @@ static int opD3_l_a32(uint32_t fetchdat) {
PREFETCH_RUN(3, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 0); \
return 0; \
} \
static int op ## operation ## _i_a32(uint32_t fetchdat) \
{ \
static int op##operation##_i_a32(uint32_t fetchdat) { \
int count; \
\
fetch_ea_32(fetchdat); \
@@ -604,8 +697,7 @@ static int opD3_l_a32(uint32_t fetchdat) {
PREFETCH_RUN(3, 3, rmdat, 0, (cpu_mod == 3) ? 0 : 1, 0, (cpu_mod == 3) ? 0 : 1, 1); \
return 0; \
} \
static int op ## operation ## _CL_a32(uint32_t fetchdat) \
{ \
static int op##operation##_CL_a32(uint32_t fetchdat) { \
int count; \
\
fetch_ea_32(fetchdat); \
@@ -619,9 +711,6 @@ static int opD3_l_a32(uint32_t fetchdat) {
return 0; \
}
opSHxD(SHLD_w)
opSHxD(SHLD_l)
opSHxD(SHRD_w)
opSHxD(SHRD_l)
opSHxD(SHLD_w) opSHxD(SHLD_l) opSHxD(SHRD_w) opSHxD(SHRD_l)
#endif /* _X86_OPS_SHIFT_H_ */

40
includes/private/cpu/x86_ops_stack.h
View File

@@ -1,8 +1,7 @@
#ifndef _X86_OPS_STACK_H_
#define _X86_OPS_STACK_H_
#define PUSH_W_OP(reg) \
static int opPUSH_ ## reg (uint32_t fetchdat) \
{ \
static int opPUSH_##reg(uint32_t fetchdat) { \
PUSH_W(reg); \
CLOCK_CYCLES((is486) ? 1 : 2); \
PREFETCH_RUN(2, 1, -1, 0, 0, 1, 0, 0); \
@@ -10,8 +9,7 @@
}
#define PUSH_L_OP(reg) \
static int opPUSH_ ## reg (uint32_t fetchdat) \
{ \
static int opPUSH_##reg(uint32_t fetchdat) { \
PUSH_L(reg); \
CLOCK_CYCLES((is486) ? 1 : 2); \
PREFETCH_RUN(2, 1, -1, 0, 0, 0, 1, 0); \
@@ -19,8 +17,7 @@
}
#define POP_W_OP(reg) \
static int opPOP_ ## reg (uint32_t fetchdat) \
{ \
static int opPOP_##reg(uint32_t fetchdat) { \
reg = POP_W(); \
CLOCK_CYCLES((is486) ? 1 : 4); \
PREFETCH_RUN(4, 1, -1, 1, 0, 0, 0, 0); \
@@ -28,8 +25,7 @@
}
#define POP_L_OP(reg) \
static int opPOP_ ## reg (uint32_t fetchdat) \
{ \
static int opPOP_##reg(uint32_t fetchdat) { \
reg = POP_L(); \
CLOCK_CYCLES((is486) ? 1 : 4); \
PREFETCH_RUN(4, 1, -1, 0, 1, 0, 0, 0); \
@@ -521,15 +517,13 @@ static int opLEAVE_l(uint32_t fetchdat) {
}
#define PUSH_SEG_OPS(seg) \
static int opPUSH_ ## seg ## _w(uint32_t fetchdat) \
{ \
static int opPUSH_##seg##_w(uint32_t fetchdat) { \
PUSH_W(seg); \
CLOCK_CYCLES(2); \
PREFETCH_RUN(2, 1, -1, 0, 0, 1, 0, 0); \
return cpu_state.abrt; \
} \
static int opPUSH_ ## seg ## _l(uint32_t fetchdat) \
{ \
static int opPUSH_##seg##_l(uint32_t fetchdat) { \
PUSH_L(seg); \
CLOCK_CYCLES(2); \
PREFETCH_RUN(2, 1, -1, 0, 0, 0, 1, 0); \
@@ -537,22 +531,28 @@ static int opLEAVE_l(uint32_t fetchdat) {
}
#define POP_SEG_OPS(seg, realseg) \
static int opPOP_ ## seg ## _w(uint32_t fetchdat) \
{ \
static int opPOP_##seg##_w(uint32_t fetchdat) { \
uint16_t temp_seg; \
uint32_t temp_esp = ESP; \
temp_seg = POP_W(); if (cpu_state.abrt) return 1; \
loadseg(temp_seg, realseg); if (cpu_state.abrt) ESP = temp_esp; \
temp_seg = POP_W(); \
if (cpu_state.abrt) \
return 1; \
loadseg(temp_seg, realseg); \
if (cpu_state.abrt) \
ESP = temp_esp; \
CLOCK_CYCLES(is486 ? 3 : 7); \
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0, 0, 1, 0, 0); \
return cpu_state.abrt; \
} \
static int opPOP_ ## seg ## _l(uint32_t fetchdat) \
{ \
static int opPOP_##seg##_l(uint32_t fetchdat) { \
uint32_t temp_seg; \
uint32_t temp_esp = ESP; \
temp_seg = POP_L(); if (cpu_state.abrt) return 1; \
loadseg(temp_seg & 0xffff, realseg); if (cpu_state.abrt) ESP = temp_esp; \
temp_seg = POP_L(); \
if (cpu_state.abrt) \
return 1; \
loadseg(temp_seg & 0xffff, realseg); \
if (cpu_state.abrt) \
ESP = temp_esp; \
CLOCK_CYCLES(is486 ? 3 : 7); \
PREFETCH_RUN(is486 ? 3 : 7, 1, -1, 0, 0, 1, 0, 0); \
return cpu_state.abrt; \

12
includes/private/cpu/x86_ops_xchg.h
View File

@@ -220,21 +220,13 @@ static int opXCHG_EAX_ESP(uint32_t fetchdat) {
}
#define opBSWAP(reg) \
static int opBSWAP_ ## reg(uint32_t fetchdat) \
{ \
static int opBSWAP_##reg(uint32_t fetchdat) { \
reg = (reg >> 24) | ((reg >> 8) & 0xff00) | ((reg << 8) & 0xff0000) | ((reg << 24) & 0xff000000); \
CLOCK_CYCLES(1); \
PREFETCH_RUN(1, 1, -1, 0, 0, 0, 0, 0); \
return 0; \
}
opBSWAP(EAX)
opBSWAP(EBX)
opBSWAP(ECX)
opBSWAP(EDX)
opBSWAP(ESI)
opBSWAP(EDI)
opBSWAP(EBP)
opBSWAP(ESP)
opBSWAP(EAX) opBSWAP(EBX) opBSWAP(ECX) opBSWAP(EDX) opBSWAP(ESI) opBSWAP(EDI) opBSWAP(EBP) opBSWAP(ESP)
#endif /* _X86_OPS_XCHG_H_ */

149
includes/private/cpu/x87_ops.h
View File

@@ -14,26 +14,22 @@ static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZ
#define FPCW_DISI (1 << 7)
#define x87_div(dst, src1, src2) do \
{ \
if (((double)src2) == 0.0) \
{ \
#define x87_div(dst, src1, src2) \
do { \
if (((double)src2) == 0.0) { \
cpu_state.npxs |= STATUS_ZERODIVIDE; \
if (cpu_state.npxc & STATUS_ZERODIVIDE) \
dst = src1 / (double)src2; \
else \
{ \
else { \
pclog("FPU : divide by zero\n"); \
picint(1 << 13); \
return 1; \
} \
} \
else \
} else \
dst = src1 / (double)src2; \
} while (0)
static inline void x87_checkexceptions() {
}
static inline void x87_checkexceptions() {}
static inline void x87_push(double i) {
cpu_state.TOP--;
@@ -198,15 +194,13 @@ static inline uint16_t x87_compare(double a, double b) {
* before the compare rather than after */
asm volatile("" : : : "memory");
asm(
"fldl %2\n"
asm("fldl %2\n"
"fldl %1\n"
"fclex\n"
"fcompp\n"
"fnstsw %0\n"
: "=m"(out)
: "m" (a), "m" (b)
);
: "m"(a), "m"(b));
return out & (C0 | C2 | C3);
#else
@@ -231,15 +225,13 @@ static inline uint16_t x87_ucompare(double a, double b) {
* before the compare rather than after */
asm volatile("" : : : "memory");
asm(
"fldl %2\n"
asm("fldl %2\n"
"fldl %1\n"
"fclex\n"
"fucompp\n"
"fnstsw %0\n"
: "=m"(out)
: "m" (a), "m" (b)
);
: "m"(a), "m"(b));
return out & (C0 | C2 | C3);
#else
@@ -269,10 +261,9 @@ typedef union {
#ifdef X8087
#define FP_ENTER() fpucount++
#else
#define FP_ENTER() do \
{ \
if (cr0 & 0xc) \
{ \
#define FP_ENTER() \
do { \
if (cr0 & 0xc) { \
x86_int(7); \
return 1; \
} \
@@ -316,24 +307,19 @@ static int FPU_ILLEGAL_a32(uint32_t fetchdat) {
return 0;
}
OpFn OP_TABLE(fpu_d8_a16)[32] =
{
opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16,
opFADD, opFMUL, opFCOM, opFCOMP, opFSUB, opFSUBR, opFDIV, opFDIVR
};
OpFn OP_TABLE(fpu_d8_a32)[32] =
{
opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32,
opFADD, opFMUL, opFCOM, opFCOMP, opFSUB, opFSUBR, opFDIV, opFDIVR
};
OpFn OP_TABLE(fpu_d8_a16)[32] = {opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16, opFDIVs_a16,
opFDIVRs_a16, opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16, opFSUBRs_a16,
opFDIVs_a16, opFDIVRs_a16, opFADDs_a16, opFMULs_a16, opFCOMs_a16, opFCOMPs_a16, opFSUBs_a16,
opFSUBRs_a16, opFDIVs_a16, opFDIVRs_a16, opFADD, opFMUL, opFCOM, opFCOMP,
opFSUB, opFSUBR, opFDIV, opFDIVR};
OpFn OP_TABLE(fpu_d8_a32)[32] = {opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32, opFDIVs_a32,
opFDIVRs_a32, opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32, opFSUBRs_a32,
opFDIVs_a32, opFDIVRs_a32, opFADDs_a32, opFMULs_a32, opFCOMs_a32, opFCOMPs_a32, opFSUBs_a32,
opFSUBRs_a32, opFDIVs_a32, opFDIVRs_a32, opFADD, opFMUL, opFCOM, opFCOMP,
opFSUB, opFSUBR, opFDIV, opFDIVR};
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_d9_a16)[256] =
{
OpFn OP_TABLE(fpu_d9_a16)[256] = {
opFLDs_a16, opFLDs_a16, opFLDs_a16, opFLDs_a16, opFLDs_a16, opFLDs_a16, opFLDs_a16, opFLDs_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFSTs_a16, opFSTs_a16, opFSTs_a16, opFSTs_a16, opFSTs_a16, opFSTs_a16, opFSTs_a16, opFSTs_a16,
@@ -368,12 +354,10 @@ OpFn OP_TABLE(fpu_d9_a16)[256] =
opFCHS, opFABS, ILLEGAL, ILLEGAL, opFTST, opFXAM, ILLEGAL, ILLEGAL,
opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS
};
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_d9_a32)[256] =
{
OpFn OP_TABLE(fpu_d9_a32)[256] = {
opFLDs_a32, opFLDs_a32, opFLDs_a32, opFLDs_a32, opFLDs_a32, opFLDs_a32, opFLDs_a32, opFLDs_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFSTs_a32, opFSTs_a32, opFSTs_a32, opFSTs_a32, opFSTs_a32, opFSTs_a32, opFSTs_a32, opFSTs_a32,
@@ -408,13 +392,11 @@ OpFn OP_TABLE(fpu_d9_a32)[256] =
opFCHS, opFABS, ILLEGAL, ILLEGAL, opFTST, opFXAM, ILLEGAL, ILLEGAL,
opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS
};
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_da_a16)[256] =
{
OpFn OP_TABLE(fpu_da_a16)[256] = {
opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16,
opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16,
opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16,
@@ -453,8 +435,7 @@ OpFn OP_TABLE(fpu_da_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_da_a32)[256] =
{
OpFn OP_TABLE(fpu_da_a32)[256] = {
opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32,
opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32,
opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32,
@@ -494,8 +475,7 @@ OpFn OP_TABLE(fpu_da_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_686_da_a16)[256] =
{
OpFn OP_TABLE(fpu_686_da_a16)[256] = {
opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16,
opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16, opFMULil_a16,
opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16, opFCOMil_a16,
@@ -534,8 +514,7 @@ OpFn OP_TABLE(fpu_686_da_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_686_da_a32)[256] =
{
OpFn OP_TABLE(fpu_686_da_a32)[256] = {
opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32, opFADDil_a32,
opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32, opFMULil_a32,
opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32, opFCOMil_a32,
@@ -575,8 +554,7 @@ OpFn OP_TABLE(fpu_686_da_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_db_a16)[256] =
{
OpFn OP_TABLE(fpu_db_a16)[256] = {
opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16,
@@ -615,8 +593,7 @@ OpFn OP_TABLE(fpu_db_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_db_a32)[256] =
{
OpFn OP_TABLE(fpu_db_a32)[256] = {
opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32,
@@ -656,8 +633,7 @@ OpFn OP_TABLE(fpu_db_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_686_db_a16)[256] =
{
OpFn OP_TABLE(fpu_686_db_a16)[256] = {
opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16, opFISTil_a16,
@@ -696,8 +672,7 @@ OpFn OP_TABLE(fpu_686_db_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_686_db_a32)[256] =
{
OpFn OP_TABLE(fpu_686_db_a32)[256] = {
opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32, opFILDil_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32, opFISTil_a32,
@@ -736,24 +711,19 @@ OpFn OP_TABLE(fpu_686_db_a32)[256] =
};
#undef ILLEGAL
OpFn OP_TABLE(fpu_dc_a16)[32] =
{
opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16,
opFADDr, opFMULr, opFCOM, opFCOMP, opFSUBRr, opFSUBr, opFDIVRr, opFDIVr
};
OpFn OP_TABLE(fpu_dc_a32)[32] =
{
opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32,
opFADDr, opFMULr, opFCOM, opFCOMP, opFSUBRr, opFSUBr, opFDIVRr, opFDIVr
};
OpFn OP_TABLE(fpu_dc_a16)[32] = {opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16, opFDIVd_a16,
opFDIVRd_a16, opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16, opFSUBRd_a16,
opFDIVd_a16, opFDIVRd_a16, opFADDd_a16, opFMULd_a16, opFCOMd_a16, opFCOMPd_a16, opFSUBd_a16,
opFSUBRd_a16, opFDIVd_a16, opFDIVRd_a16, opFADDr, opFMULr, opFCOM, opFCOMP,
opFSUBRr, opFSUBr, opFDIVRr, opFDIVr};
OpFn OP_TABLE(fpu_dc_a32)[32] = {opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32, opFDIVd_a32,
opFDIVRd_a32, opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32, opFSUBRd_a32,
opFDIVd_a32, opFDIVRd_a32, opFADDd_a32, opFMULd_a32, opFCOMd_a32, opFCOMPd_a32, opFSUBd_a32,
opFSUBRd_a32, opFDIVd_a32, opFDIVRd_a32, opFADDr, opFMULr, opFCOM, opFCOMP,
opFSUBRr, opFSUBr, opFDIVRr, opFDIVr};
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_dd_a16)[256] =
{
OpFn OP_TABLE(fpu_dd_a16)[256] = {
opFLDd_a16, opFLDd_a16, opFLDd_a16, opFLDd_a16, opFLDd_a16, opFLDd_a16, opFLDd_a16, opFLDd_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFSTd_a16, opFSTd_a16, opFSTd_a16, opFSTd_a16, opFSTd_a16, opFSTd_a16, opFSTd_a16, opFSTd_a16,
@@ -792,8 +762,7 @@ OpFn OP_TABLE(fpu_dd_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_dd_a32)[256] =
{
OpFn OP_TABLE(fpu_dd_a32)[256] = {
opFLDd_a32, opFLDd_a32, opFLDd_a32, opFLDd_a32, opFLDd_a32, opFLDd_a32, opFLDd_a32, opFLDd_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFSTd_a32, opFSTd_a32, opFSTd_a32, opFSTd_a32, opFSTd_a32, opFSTd_a32, opFSTd_a32, opFSTd_a32,
@@ -833,8 +802,7 @@ OpFn OP_TABLE(fpu_dd_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_de_a16)[256] =
{
OpFn OP_TABLE(fpu_de_a16)[256] = {
opFADDiw_a16, opFADDiw_a16, opFADDiw_a16, opFADDiw_a16, opFADDiw_a16, opFADDiw_a16, opFADDiw_a16, opFADDiw_a16,
opFMULiw_a16, opFMULiw_a16, opFMULiw_a16, opFMULiw_a16, opFMULiw_a16, opFMULiw_a16, opFMULiw_a16, opFMULiw_a16,
opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16, opFCOMiw_a16,
@@ -873,8 +841,7 @@ OpFn OP_TABLE(fpu_de_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_de_a32)[256] =
{
OpFn OP_TABLE(fpu_de_a32)[256] = {
opFADDiw_a32, opFADDiw_a32, opFADDiw_a32, opFADDiw_a32, opFADDiw_a32, opFADDiw_a32, opFADDiw_a32, opFADDiw_a32,
opFMULiw_a32, opFMULiw_a32, opFMULiw_a32, opFMULiw_a32, opFMULiw_a32, opFMULiw_a32, opFMULiw_a32, opFMULiw_a32,
opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32, opFCOMiw_a32,
@@ -914,8 +881,7 @@ OpFn OP_TABLE(fpu_de_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_df_a16)[256] =
{
OpFn OP_TABLE(fpu_df_a16)[256] = {
opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16,
@@ -954,8 +920,7 @@ OpFn OP_TABLE(fpu_df_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_df_a32)[256] =
{
OpFn OP_TABLE(fpu_df_a32)[256] = {
opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32,
@@ -995,8 +960,7 @@ OpFn OP_TABLE(fpu_df_a32)[256] =
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a16
OpFn OP_TABLE(fpu_686_df_a16)[256] =
{
OpFn OP_TABLE(fpu_686_df_a16)[256] = {
opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16, opFISTiw_a16,
@@ -1035,8 +999,7 @@ OpFn OP_TABLE(fpu_686_df_a16)[256] =
};
#undef ILLEGAL
#define ILLEGAL FPU_ILLEGAL_a32
OpFn OP_TABLE(fpu_686_df_a32)[256] =
{
OpFn OP_TABLE(fpu_686_df_a32)[256] = {
opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32, opFILDiw_a32,
ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32, opFISTiw_a32,
@@ -1075,8 +1038,7 @@ OpFn OP_TABLE(fpu_686_df_a32)[256] =
};
#undef ILLEGAL
OpFn OP_TABLE(nofpu_a16)[256] =
{
OpFn OP_TABLE(nofpu_a16)[256] = {
op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
@@ -1113,8 +1075,7 @@ OpFn OP_TABLE(nofpu_a16)[256] =
op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16, op_nofpu_a16,
};
OpFn OP_TABLE(nofpu_a32)[256] =
{
OpFn OP_TABLE(nofpu_a32)[256] = {
op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,
op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32, op_nofpu_a32,

62
includes/private/cpu/x87_ops_arith.h
View File

@@ -1,13 +1,14 @@
#ifndef _X87_OPS_ARITH_H_
#define _X87_OPS_ARITH_H_
#define opFPU(name, optype, a_size, load_var, get, use_var, cycle_postfix) \
static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFADD##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
if ((cpu_state.npxc >> 10) & 3) \
fesetround(rounding_modes[(cpu_state.npxc >> 10) & 3]); \
ST(0) += use_var; \
@@ -17,96 +18,101 @@ static int opFADD ## name ## _a ## a_size(uint32_t fetchdat) \
CLOCK_CYCLES(x87_timings.fadd##cycle_postfix); \
return 0; \
} \
static int opFCOM ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFCOM##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.npxs &= ~(C0 | C2 | C3); \
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
CLOCK_CYCLES(x87_timings.fcom##cycle_postfix); \
return 0; \
} \
static int opFCOMP ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFCOMP##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.npxs &= ~(C0 | C2 | C3); \
cpu_state.npxs |= x87_compare(ST(0), (double)use_var); \
x87_pop(); \
CLOCK_CYCLES(x87_timings.fcom##cycle_postfix); \
return 0; \
} \
static int opFDIV ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFDIV##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
x87_div(ST(0), ST(0), use_var); \
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID; \
CLOCK_CYCLES(x87_timings.fdiv##cycle_postfix); \
return 0; \
} \
static int opFDIVR ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFDIVR##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
x87_div(ST(0), use_var, ST(0)); \
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID; \
CLOCK_CYCLES(x87_timings.fdiv##cycle_postfix); \
return 0; \
} \
static int opFMUL ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFMUL##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
ST(0) *= use_var; \
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID; \
CLOCK_CYCLES(x87_timings.fmul##cycle_postfix); \
return 0; \
} \
static int opFSUB ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFSUB##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
ST(0) -= use_var; \
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID; \
CLOCK_CYCLES(x87_timings.fadd##cycle_postfix); \
return 0; \
} \
static int opFSUBR ## name ## _a ## a_size(uint32_t fetchdat) \
{ \
static int opFSUBR##name##_a##a_size(uint32_t fetchdat) { \
optype t; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = get(); if (cpu_state.abrt) return 1; \
load_var = get(); \
if (cpu_state.abrt) \
return 1; \
ST(0) = use_var - ST(0); \
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID; \
CLOCK_CYCLES(x87_timings.fadd##cycle_postfix); \
return 0; \
}
opFPU(s, x87_ts, 16, t.i, geteal, t.s, _32)
opFPU(s, x87_ts, 32, t.i, geteal, t.s, _32)
opFPU(d, x87_td, 16, t.i, geteaq, t.d, _64)
opFPU(d, x87_td, 32, t.i, geteaq, t.d, _64)
opFPU(s, x87_ts, 16, t.i, geteal, t.s, _32) opFPU(s, x87_ts, 32, t.i, geteal, t.s, _32)
opFPU(d, x87_td, 16, t.i, geteaq, t.d, _64) opFPU(d, x87_td, 32, t.i, geteaq, t.d, _64)
opFPU(iw, uint16_t, 16, t, geteaw, (double)(int16_t)t, _i16)
opFPU(iw, uint16_t, 32, t, geteaw, (double)(int16_t)t, _i16)

6
includes/private/cpu/x87_ops_loadstore.h
View File

@@ -108,7 +108,8 @@ static int opFILDiq_a16(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
if (fplog)
pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg, cpu_state.eaaddr), readmeml(easeg, cpu_state.eaaddr + 4));
pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg, cpu_state.eaaddr),
readmeml(easeg, cpu_state.eaaddr + 4));
x87_push((double)temp64);
cpu_state.MM[cpu_state.TOP & 7].q = temp64;
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID | TAG_UINT64;
@@ -127,7 +128,8 @@ static int opFILDiq_a32(uint32_t fetchdat) {
if (cpu_state.abrt)
return 1;
if (fplog)
pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg, cpu_state.eaaddr), readmeml(easeg, cpu_state.eaaddr + 4));
pclog(" %f %08X %08X\n", (double)temp64, readmeml(easeg, cpu_state.eaaddr),
readmeml(easeg, cpu_state.eaaddr + 4));
x87_push((double)temp64);
cpu_state.MM[cpu_state.TOP & 7].q = temp64;
cpu_state.tag[cpu_state.TOP & 7] = TAG_VALID | TAG_UINT64;

25
includes/private/cpu/x87_ops_misc.h
View File

@@ -137,9 +137,10 @@ static int FSTOR() {
cpu_state.ismmx = 0;
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
something like this is needed*/
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
!cpu_state.TOP && (*(uint64_t *)cpu_state.tag == 0x0101010101010101ull))
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff &&
cpu_state.MM_w4[3] == 0xffff && cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff &&
cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff && !cpu_state.TOP &&
(*(uint64_t *)cpu_state.tag == 0x0101010101010101ull))
cpu_state.ismmx = 1;
CLOCK_CYCLES(x87_timings.frstor);
@@ -904,13 +905,12 @@ static int opFSTCW_a32(uint32_t fetchdat) {
}
#define opFCMOV(condition) \
static int opFCMOV ## condition(uint32_t fetchdat) \
{ \
static int opFCMOV##condition(uint32_t fetchdat) { \
FP_ENTER(); \
cpu_state.pc++; \
if (fplog) pclog("FCMOV %f\n", ST(fetchdat & 7)); \
if (cond_ ## condition) \
{ \
if (fplog) \
pclog("FCMOV %f\n", ST(fetchdat & 7)); \
if (cond_##condition) { \
cpu_state.tag[cpu_state.TOP & 7] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7]; \
cpu_state.MM[cpu_state.TOP & 7].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q; \
ST(0) = ST(fetchdat & 7); \
@@ -922,13 +922,6 @@ static int opFSTCW_a32(uint32_t fetchdat) {
#define cond_U (PF_SET())
#define cond_NU (!PF_SET())
opFCMOV(B)
opFCMOV(E)
opFCMOV(BE)
opFCMOV(U)
opFCMOV(NB)
opFCMOV(NE)
opFCMOV(NBE)
opFCMOV(NU)
opFCMOV(B) opFCMOV(E) opFCMOV(BE) opFCMOV(U) opFCMOV(NB) opFCMOV(NE) opFCMOV(NBE) opFCMOV(NU)
#endif /* _X87_OPS_MISC_H_ */

1
includes/private/devices/cassette.h
View File

@@ -32,5 +32,4 @@ void cassette_load(const char *filename);
extern char cassettefn[256];
#endif /* _CASSETTE_H_ */

1
includes/private/devices/esdi_at.h
View File

@@ -2,5 +2,4 @@
#define _ESDI_AT_H_
extern device_t wd1007vse1_device;
#endif /* _ESDI_AT_H_ */

2
includes/private/devices/f82c710_upc.h
View File

@@ -6,6 +6,4 @@ void upc_set_mouse(void (*mouse_write)(uint8_t val, void *p), void *p);
extern device_t f82c710_upc_device;
#endif /* _F82C710_UPC_H_ */

1
includes/private/devices/nvr.h
View File

@@ -17,5 +17,4 @@ extern uint8_t nvrram[128];
extern int nvrmask;
extern int oldromset;
#endif /* _NVR_H_ */

1
includes/private/devices/nvr_tc8521.h
View File

@@ -13,5 +13,4 @@ void tc8521_nvr_recalc();
FILE *nvrfopen(char *fn, char *mode);
#endif /* _NVR_TC8521_H_ */

1
includes/private/devices/ps2_nvr.h
View File

@@ -2,5 +2,4 @@
#define _PS2_NVR_H_
extern device_t ps2_nvr_device;
#endif /* _PS2_NVR_H_ */

1
includes/private/devices/sis496.h
View File

@@ -2,5 +2,4 @@
#define _SIS496_H_
extern device_t sis496_device;
#endif /* _SIS496_H_ */

14
includes/private/dosbox/cdrom.h
View File

@@ -52,7 +52,8 @@ typedef size_t PhysPt;
#define AUDIO_TRACK 0x10
#define CD_FPS 75
#define FRAMES_TO_MSF(f, M,S,F) { \
#define FRAMES_TO_MSF(f, M, S, F) \
{ \
int value = f; \
*(F) = value % CD_FPS; \
value /= CD_FPS; \
@@ -62,7 +63,6 @@ typedef size_t PhysPt;
}
#define MSF_TO_FRAMES(M, S, F) ((M)*60 * CD_FPS + (S)*CD_FPS + (F))
typedef struct SMSF {
unsigned char min;
unsigned char sec;
@@ -76,8 +76,7 @@ typedef struct SCtrl {
extern int CDROM_GetMountType(char *path, int force);
class CDROM_Interface
{
class CDROM_Interface {
public:
// CDROM_Interface (void);
virtual ~CDROM_Interface(void){};
@@ -88,7 +87,8 @@ public:
virtual bool GetAudioTracks(int &stTrack, int &end, TMSF &leadOut) = 0;
virtual bool GetAudioTrackInfo(int track, int &number, TMSF &start, unsigned char &attr) = 0;
virtual bool GetAudioSub (int sector, unsigned char& attr, unsigned char& track, unsigned char& index, TMSF& relPos, TMSF& absPos) = 0;
virtual bool GetAudioSub(int sector, unsigned char &attr, unsigned char &track, unsigned char &index, TMSF &relPos,
TMSF &absPos) = 0;
virtual bool GetMediaTrayStatus(bool &mediaPresent, bool &mediaChanged, bool &trayOpen) = 0;
virtual bool ReadSectors(PhysPt buffer, bool raw, unsigned long sector, unsigned long num) = 0;
@@ -98,8 +98,7 @@ public:
virtual void InitNewMedia(void){};
};
class CDROM_Interface_Image : public CDROM_Interface
{
class CDROM_Interface_Image : public CDROM_Interface {
private:
class TrackFile {
public:
@@ -114,6 +113,7 @@ private:
~BinaryFile();
bool read(Bit8u *buffer, int seek, int count);
int getLength();
private:
BinaryFile();
std::ifstream *file;

20
includes/private/dosbox/dbopl.h
View File

@@ -136,11 +136,13 @@ public:
Bit8u vibStrength;
// Keep track of the calculated KSR so we can check for changes
Bit8u ksr;
private:
void SetState(Bit8u s);
void UpdateAttack(const Chip *chip);
void UpdateRelease(const Chip *chip);
void UpdateDecay(const Chip *chip);
public:
void UpdateAttenuation();
void UpdateRates(const Chip *chip);
@@ -158,8 +160,7 @@ public:
void KeyOn(Bit8u mask);
void KeyOff(Bit8u mask);
template< State state>
Bits TemplateVolume( );
template <State state> Bits TemplateVolume();
Bit32s RateForward(Bit32u add);
Bitu ForwardWave();
@@ -167,15 +168,14 @@ public:
Bits GetSample(Bits modulation);
Bits GetWave(Bitu index, Bitu vol);
public:
Operator();
};
struct Channel {
Operator op[2];
inline Operator* Op( Bitu index ) {
return &( ( this + (index >> 1) )->op[ index & 1 ]);
}
inline Operator *Op(Bitu index) { return &((this + (index >> 1))->op[index & 1]); }
SynthHandler synthHandler;
Bit32u chanData; // Frequency/octave and derived values
Bit32s old[2]; // Old data for feedback
@@ -198,12 +198,10 @@ struct Channel {
void ResetC0(const Chip *chip);
// call this for the first channel
template< bool opl3Mode >
void GeneratePercussion( Chip* chip, Bit32s* output );
template <bool opl3Mode> void GeneratePercussion(Chip *chip, Bit32s *output);
// Generate blocks of data in specific modes
template<SynthMode mode>
Channel* BlockTemplate( Chip* chip, Bit32u samples, Bit32s* output );
template <SynthMode mode> Channel *BlockTemplate(Chip *chip, Bit32u samples, Bit32s *output);
Channel();
};
@@ -212,7 +210,6 @@ struct Chip {
Bit32u lfoCounter;
Bit32u lfoAdd;
Bit32u noiseCounter;
Bit32u noiseAdd;
Bit32u noiseValue;
@@ -273,7 +270,6 @@ struct Chip {
void InitTables(void);
}; //Namespace
}; // namespace DBOPL
#endif /* _DBOPL_H_ */

1
includes/private/dosbox/vid_cga_comp.h
View File

@@ -9,5 +9,4 @@ void update_cga16_color(uint8_t cgamode);
void cga_comp_init(int revision);
Bit8u *Composite_Process(uint8_t cgamode, Bit8u border, Bit32u blocks /*, bool doublewidth*/, Bit8u *TempLine);
#endif /* _VID_CGA_COMP_H_ */

3
includes/private/fdi2raw.h
View File

@@ -13,7 +13,8 @@ typedef struct fdi FDI;
extern "C" {
#endif
extern int fdi2raw_loadtrack (FDI*, uae_u16 *mfmbuf, uae_u16 *tracktiming, int track, int *tracklength, int *indexoffset, int *multirev, int mfm);
extern int fdi2raw_loadtrack(FDI *, uae_u16 *mfmbuf, uae_u16 *tracktiming, int track, int *tracklength, int *indexoffset,
int *multirev, int mfm);
extern int fdi2raw_loadrevolution(FDI *, uae_u16 *mfmbuf, uae_u16 *tracktiming, int track, int *tracklength, int mfm);

129
includes/private/filters.h
View File

@@ -4,17 +4,9 @@
// fc=350Hz
static inline float low_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.00049713569693400649,
0.00099427139386801299,
0.00049713569693400649
};
float ACoef[NCoef + 1] = {0.00049713569693400649, 0.00099427139386801299, 0.00049713569693400649};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.93522955470669530000,
0.93726236021404663000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.93522955470669530000, 0.93726236021404663000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
@@ -37,17 +29,9 @@ static inline float low_iir(int i, float NewSample) {
// fc=350Hz
static inline float low_cut_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.96839970114733542000,
-1.93679940229467080000,
0.96839970114733542000
};
float ACoef[NCoef + 1] = {0.96839970114733542000, -1.93679940229467080000, 0.96839970114733542000};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.93522955471202770000,
0.93726236021916731000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.93522955471202770000, 0.93726236021916731000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
@@ -70,17 +54,9 @@ static inline float low_cut_iir(int i, float NewSample) {
// fc=3.5kHz
static inline float high_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.72248704753064896000,
-1.44497409506129790000,
0.72248704753064896000
};
float ACoef[NCoef + 1] = {0.72248704753064896000, -1.44497409506129790000, 0.72248704753064896000};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.36640781670578510000,
0.52352474706139873000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.36640781670578510000, 0.52352474706139873000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
int n;
@@ -102,17 +78,9 @@ static inline float high_iir(int i, float NewSample) {
// fc=3.5kHz
static inline float high_cut_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.03927726802250377400,
0.07855453604500754700,
0.03927726802250377400
};
float ACoef[NCoef + 1] = {0.03927726802250377400, 0.07855453604500754700, 0.03927726802250377400};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.36640781666419950000,
0.52352474703279628000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.36640781666419950000, 0.52352474703279628000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
int n;
@@ -132,23 +100,14 @@ static inline float high_cut_iir(int i, float NewSample) {
return y[i][0];
}
#undef NCoef
#define NCoef 2
// fc=3.2kHz
static inline float sb_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.03356837051492005100,
0.06713674102984010200,
0.03356837051492005100
};
float ACoef[NCoef + 1] = {0.03356837051492005100, 0.06713674102984010200, 0.03356837051492005100};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.41898265221812010000,
0.55326988968868285000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.41898265221812010000, 0.55326988968868285000};
/* float ACoef[NCoef+1] = {
0.17529642630084405000,
@@ -178,24 +137,14 @@ static inline float sb_iir(int i, float NewSample) {
return y[i][0];
}
#undef NCoef
#define NCoef 2
// fc=150Hz
static inline float adgold_highpass_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.98657437157334349000,
-1.97314874314668700000,
0.98657437157334349000
};
float ACoef[NCoef + 1] = {0.98657437157334349000, -1.97314874314668700000, 0.98657437157334349000};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.97223372919758360000,
0.97261396931534050000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.97223372919758360000, 0.97261396931534050000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
@@ -218,17 +167,9 @@ static inline float adgold_highpass_iir(int i, float NewSample) {
// fc=150Hz
static inline float adgold_lowpass_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.00009159473951071446,
0.00018318947902142891,
0.00009159473951071446
};
float ACoef[NCoef + 1] = {0.00009159473951071446, 0.00018318947902142891, 0.00009159473951071446};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.97223372919526560000,
0.97261396931306277000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.97223372919526560000, 0.97261396931306277000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
@@ -251,17 +192,9 @@ static inline float adgold_lowpass_iir(int i, float NewSample) {
// fc=56Hz
static inline float adgold_pseudo_stereo_iir(float NewSample) {
float ACoef[NCoef+1] = {
0.00001409030866231767,
0.00002818061732463533,
0.00001409030866231767
};
float ACoef[NCoef + 1] = {0.00001409030866231767, 0.00002818061732463533, 0.00001409030866231767};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.98733021473466760000,
0.98738361004063568000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.98733021473466760000, 0.98738361004063568000};
static float y[NCoef + 1]; // output samples
static float x[NCoef + 1]; // input samples
@@ -284,17 +217,9 @@ static inline float adgold_pseudo_stereo_iir(float NewSample) {
// fc=3.2kHz - probably incorrect
static inline float dss_iir(float NewSample) {
float ACoef[NCoef+1] = {
0.03356837051492005100,
0.06713674102984010200,
0.03356837051492005100
};
float ACoef[NCoef + 1] = {0.03356837051492005100, 0.06713674102984010200, 0.03356837051492005100};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-1.41898265221812010000,
0.55326988968868285000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -1.41898265221812010000, 0.55326988968868285000};
static float y[NCoef + 1]; // output samples
static float x[NCoef + 1]; // input samples
@@ -319,15 +244,9 @@ static inline float dss_iir(float NewSample) {
#define NCoef 1
/*Basic high pass to remove DC bias. fc=10Hz*/
static inline float dac_iir(int i, float NewSample) {
float ACoef[NCoef+1] = {
0.99901119820285345000,
-0.99901119820285345000
};
float ACoef[NCoef + 1] = {0.99901119820285345000, -0.99901119820285345000};
float BCoef[NCoef+1] = {
1.00000000000000000000,
-0.99869185905052738000
};
float BCoef[NCoef + 1] = {1.00000000000000000000, -0.99869185905052738000};
static float y[2][NCoef + 1]; // output samples
static float x[2][NCoef + 1]; // input samples
@@ -348,13 +267,11 @@ static inline float dac_iir(int i, float NewSample) {
return y[i][0];
}
#define SB16_NCoef 51
extern float low_fir_sb16_coef[SB16_NCoef];
static inline float low_fir_sb16(int i, float NewSample)
{
static inline float low_fir_sb16(int i, float NewSample) {
static float x[2][SB16_NCoef + 1]; // input samples
static int pos = 0;
float out = 0.0;
@@ -368,8 +285,7 @@ static inline float low_fir_sb16(int i, float NewSample)
for (; n < SB16_NCoef; n++)
out += low_fir_sb16_coef[n] * x[i][(n + pos) - (SB16_NCoef + 1)];
if (i == 1)
{
if (i == 1) {
pos++;
if (pos > SB16_NCoef)
pos = 0;
@@ -378,5 +294,4 @@ static inline float low_fir_sb16(int i, float NewSample)
return out;
}
#endif /* _FILTERS_H_ */

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