mirror of
https://github.com/sarah-walker-pcem/pcem.git
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231 lines
11 KiB
C
231 lines
11 KiB
C
#ifndef _X86_OPS_RET_H_
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#define _X86_OPS_RET_H_
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#define RETF_a16(stack_offset) \
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if ((msw & 1) && !(cpu_state.eflags & VM_FLAG)) { \
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pmoderetf(0, stack_offset); \
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return 1; \
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} \
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if (stack32) { \
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cpu_state.pc = readmemw(ss, ESP); \
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loadcs(readmemw(ss, ESP + 2)); \
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} else { \
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cpu_state.pc = readmemw(ss, SP); \
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loadcs(readmemw(ss, SP + 2)); \
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} \
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if (cpu_state.abrt) \
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return 1; \
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if (stack32) \
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ESP += 4 + stack_offset; \
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else \
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SP += 4 + stack_offset; \
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cycles -= timing_retf_rm;
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#define RETF_a32(stack_offset) \
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if ((msw & 1) && !(cpu_state.eflags & VM_FLAG)) { \
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pmoderetf(1, stack_offset); \
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return 1; \
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} \
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if (stack32) { \
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cpu_state.pc = readmeml(ss, ESP); \
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loadcs(readmeml(ss, ESP + 4) & 0xffff); \
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} else { \
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cpu_state.pc = readmeml(ss, SP); \
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loadcs(readmeml(ss, SP + 4) & 0xffff); \
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} \
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if (cpu_state.abrt) \
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return 1; \
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if (stack32) \
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ESP += 8 + stack_offset; \
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else \
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SP += 8 + stack_offset; \
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cycles -= timing_retf_rm;
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static int opRETF_a16(uint32_t fetchdat) {
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int cycles_old = cycles;
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UNUSED(cycles_old);
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CPU_BLOCK_END();
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RETF_a16(0);
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PREFETCH_RUN(cycles_old - cycles, 1, -1, 2, 0, 0, 0, 0);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a32(uint32_t fetchdat) {
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int cycles_old = cycles;
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UNUSED(cycles_old);
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CPU_BLOCK_END();
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RETF_a32(0);
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PREFETCH_RUN(cycles_old - cycles, 1, -1, 0, 2, 0, 0, 1);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a16_imm(uint32_t fetchdat) {
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uint16_t offset = getwordf();
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int cycles_old = cycles;
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UNUSED(cycles_old);
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CPU_BLOCK_END();
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RETF_a16(offset);
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PREFETCH_RUN(cycles_old - cycles, 3, -1, 2, 0, 0, 0, 0);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opRETF_a32_imm(uint32_t fetchdat) {
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uint16_t offset = getwordf();
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int cycles_old = cycles;
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UNUSED(cycles_old);
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CPU_BLOCK_END();
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RETF_a32(offset);
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PREFETCH_RUN(cycles_old - cycles, 3, -1, 0, 2, 0, 0, 1);
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PREFETCH_FLUSH();
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return 0;
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}
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static int opIRET_286(uint32_t fetchdat) {
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int cycles_old = cycles;
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UNUSED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3)) {
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x86gpf(NULL, 0);
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return 1;
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}
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if (msw & 1) {
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optype = IRET;
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pmodeiret(0);
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optype = 0;
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} else {
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uint16_t new_cs;
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if (stack32) {
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cpu_state.pc = readmemw(ss, ESP);
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new_cs = readmemw(ss, ESP + 2);
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cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ESP + 4) & 0xffd5) | 2;
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ESP += 6;
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} else {
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cpu_state.pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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cpu_state.flags = (cpu_state.flags & 0x7000) | (readmemw(ss, ((SP + 4) & 0xffff)) & 0x0fd5) | 2;
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SP += 6;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old - cycles, 1, -1, 2, 0, 0, 0, 0);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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static int opIRET(uint32_t fetchdat) {
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int cycles_old = cycles;
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UNUSED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3)) {
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if (cr4 & CR4_VME) {
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uint16_t new_pc, new_cs, new_flags;
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new_pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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new_flags = readmemw(ss, ((SP + 4) & 0xffff));
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if (cpu_state.abrt)
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return 1;
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if ((new_flags & T_FLAG) || ((new_flags & I_FLAG) && (cpu_state.eflags & VIP_FLAG))) {
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x86gpf(NULL, 0);
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return 1;
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}
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SP += 6;
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if (new_flags & I_FLAG)
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cpu_state.eflags |= VIF_FLAG;
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else
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cpu_state.eflags &= ~VIF_FLAG;
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cpu_state.flags = (cpu_state.flags & 0x3300) | (new_flags & 0x4cd5) | 2;
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loadcs(new_cs);
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cpu_state.pc = new_pc;
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cycles -= timing_iret_rm;
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} else {
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x86gpf_expected(NULL, 0);
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return 1;
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}
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} else {
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if (msw & 1) {
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optype = IRET;
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pmodeiret(0);
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optype = 0;
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} else {
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uint16_t new_cs;
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if (stack32) {
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cpu_state.pc = readmemw(ss, ESP);
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new_cs = readmemw(ss, ESP + 2);
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cpu_state.flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
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ESP += 6;
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} else {
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cpu_state.pc = readmemw(ss, SP);
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new_cs = readmemw(ss, ((SP + 2) & 0xffff));
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cpu_state.flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
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SP += 6;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old - cycles, 1, -1, 2, 0, 0, 0, 0);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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static int opIRETD(uint32_t fetchdat) {
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int cycles_old = cycles;
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UNUSED(cycles_old);
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if ((cr0 & 1) && (cpu_state.eflags & VM_FLAG) && (IOPL != 3)) {
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x86gpf_expected(NULL, 0);
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return 1;
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}
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if (msw & 1) {
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optype = IRET;
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pmodeiret(1);
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optype = 0;
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} else {
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uint16_t new_cs;
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if (stack32) {
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cpu_state.pc = readmeml(ss, ESP);
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new_cs = readmemw(ss, ESP + 4);
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cpu_state.flags = (readmemw(ss, ESP + 8) & 0xffd5) | 2;
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cpu_state.eflags = readmemw(ss, ESP + 10);
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ESP += 12;
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} else {
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cpu_state.pc = readmeml(ss, SP);
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new_cs = readmemw(ss, ((SP + 4) & 0xffff));
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cpu_state.flags = (readmemw(ss, (SP + 8) & 0xffff) & 0xffd5) | 2;
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cpu_state.eflags = readmemw(ss, (SP + 10) & 0xffff);
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SP += 12;
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}
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loadcs(new_cs);
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cycles -= timing_iret_rm;
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}
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flags_extract();
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nmi_enable = 1;
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CPU_BLOCK_END();
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PREFETCH_RUN(cycles_old - cycles, 1, -1, 0, 2, 0, 0, 1);
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PREFETCH_FLUSH();
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return cpu_state.abrt;
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}
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#endif /* _X86_OPS_RET_H_ */
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