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https://github.com/sarah-walker-pcem/pcem.git
synced 2025-07-23 03:33:02 +02:00
423 lines
11 KiB
C
423 lines
11 KiB
C
#ifndef _X86_OPS_MMX_SHIFT_H_
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#define _X86_OPS_MMX_SHIFT_H_
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#define MMX_GETSHIFT() \
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if (cpu_mod == 3) { \
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shift = cpu_state.MM[cpu_rm].b[0]; \
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CLOCK_CYCLES(1); \
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} else { \
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SEG_CHECK_READ(cpu_state.ea_seg); \
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shift = readmemb(easeg, cpu_state.eaaddr); \
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if (cpu_state.abrt) \
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return 0; \
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CLOCK_CYCLES(2); \
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}
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static int opPSxxW_imm(uint32_t fetchdat) {
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int reg = fetchdat & 7;
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int op = fetchdat & 0x38;
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int shift = (fetchdat >> 8) & 0xff;
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cpu_state.pc += 2;
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MMX_ENTER();
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switch (op) {
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case 0x10: /*PSRLW*/
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if (shift > 15)
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cpu_state.MM[reg].q = 0;
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else {
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cpu_state.MM[reg].w[0] >>= shift;
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cpu_state.MM[reg].w[1] >>= shift;
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cpu_state.MM[reg].w[2] >>= shift;
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cpu_state.MM[reg].w[3] >>= shift;
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}
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break;
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case 0x20: /*PSRAW*/
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if (shift > 15)
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shift = 15;
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cpu_state.MM[reg].sw[0] >>= shift;
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cpu_state.MM[reg].sw[1] >>= shift;
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cpu_state.MM[reg].sw[2] >>= shift;
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cpu_state.MM[reg].sw[3] >>= shift;
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break;
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case 0x30: /*PSLLW*/
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if (shift > 15)
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cpu_state.MM[reg].q = 0;
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else {
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cpu_state.MM[reg].w[0] <<= shift;
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cpu_state.MM[reg].w[1] <<= shift;
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cpu_state.MM[reg].w[2] <<= shift;
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cpu_state.MM[reg].w[3] <<= shift;
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}
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break;
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default:
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pclog("Bad PSxxW (0F 71) instruction %02X\n", op);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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return 0;
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}
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CLOCK_CYCLES(1);
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return 0;
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}
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static int opPSLLW_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].w[0] <<= shift;
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cpu_state.MM[cpu_reg].w[1] <<= shift;
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cpu_state.MM[cpu_reg].w[2] <<= shift;
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cpu_state.MM[cpu_reg].w[3] <<= shift;
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}
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return 0;
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}
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static int opPSLLW_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].w[0] <<= shift;
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cpu_state.MM[cpu_reg].w[1] <<= shift;
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cpu_state.MM[cpu_reg].w[2] <<= shift;
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cpu_state.MM[cpu_reg].w[3] <<= shift;
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}
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return 0;
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}
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static int opPSRLW_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].w[0] >>= shift;
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cpu_state.MM[cpu_reg].w[1] >>= shift;
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cpu_state.MM[cpu_reg].w[2] >>= shift;
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cpu_state.MM[cpu_reg].w[3] >>= shift;
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}
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return 0;
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}
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static int opPSRLW_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].w[0] >>= shift;
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cpu_state.MM[cpu_reg].w[1] >>= shift;
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cpu_state.MM[cpu_reg].w[2] >>= shift;
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cpu_state.MM[cpu_reg].w[3] >>= shift;
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}
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return 0;
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}
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static int opPSRAW_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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shift = 15;
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cpu_state.MM[cpu_reg].sw[0] >>= shift;
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cpu_state.MM[cpu_reg].sw[1] >>= shift;
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cpu_state.MM[cpu_reg].sw[2] >>= shift;
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cpu_state.MM[cpu_reg].sw[3] >>= shift;
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return 0;
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}
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static int opPSRAW_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 15)
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shift = 15;
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cpu_state.MM[cpu_reg].sw[0] >>= shift;
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cpu_state.MM[cpu_reg].sw[1] >>= shift;
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cpu_state.MM[cpu_reg].sw[2] >>= shift;
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cpu_state.MM[cpu_reg].sw[3] >>= shift;
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return 0;
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}
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static int opPSxxD_imm(uint32_t fetchdat) {
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int reg = fetchdat & 7;
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int op = fetchdat & 0x38;
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int shift = (fetchdat >> 8) & 0xff;
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cpu_state.pc += 2;
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MMX_ENTER();
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switch (op) {
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case 0x10: /*PSRLD*/
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if (shift > 31)
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cpu_state.MM[reg].q = 0;
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else {
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cpu_state.MM[reg].l[0] >>= shift;
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cpu_state.MM[reg].l[1] >>= shift;
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}
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break;
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case 0x20: /*PSRAD*/
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if (shift > 31)
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shift = 31;
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cpu_state.MM[reg].sl[0] >>= shift;
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cpu_state.MM[reg].sl[1] >>= shift;
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break;
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case 0x30: /*PSLLD*/
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if (shift > 31)
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cpu_state.MM[reg].q = 0;
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else {
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cpu_state.MM[reg].l[0] <<= shift;
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cpu_state.MM[reg].l[1] <<= shift;
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}
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break;
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default:
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pclog("Bad PSxxD (0F 72) instruction %02X\n", op);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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return 0;
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}
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CLOCK_CYCLES(1);
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return 0;
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}
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static int opPSLLD_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].l[0] <<= shift;
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cpu_state.MM[cpu_reg].l[1] <<= shift;
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}
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return 0;
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}
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static int opPSLLD_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].l[0] <<= shift;
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cpu_state.MM[cpu_reg].l[1] <<= shift;
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}
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return 0;
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}
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static int opPSRLD_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].l[0] >>= shift;
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cpu_state.MM[cpu_reg].l[1] >>= shift;
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}
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return 0;
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}
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static int opPSRLD_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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cpu_state.MM[cpu_reg].q = 0;
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else {
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cpu_state.MM[cpu_reg].l[0] >>= shift;
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cpu_state.MM[cpu_reg].l[1] >>= shift;
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}
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return 0;
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}
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static int opPSRAD_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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shift = 31;
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cpu_state.MM[cpu_reg].sl[0] >>= shift;
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cpu_state.MM[cpu_reg].sl[1] >>= shift;
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return 0;
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}
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static int opPSRAD_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 31)
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shift = 31;
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cpu_state.MM[cpu_reg].sl[0] >>= shift;
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cpu_state.MM[cpu_reg].sl[1] >>= shift;
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return 0;
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}
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static int opPSxxQ_imm(uint32_t fetchdat) {
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int reg = fetchdat & 7;
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int op = fetchdat & 0x38;
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int shift = (fetchdat >> 8) & 0xff;
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cpu_state.pc += 2;
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MMX_ENTER();
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switch (op) {
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case 0x10: /*PSRLW*/
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if (shift > 63)
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cpu_state.MM[reg].q = 0;
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else
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cpu_state.MM[reg].q >>= shift;
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break;
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case 0x20: /*PSRAW*/
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if (shift > 63)
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shift = 63;
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cpu_state.MM[reg].sq >>= shift;
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break;
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case 0x30: /*PSLLW*/
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if (shift > 63)
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cpu_state.MM[reg].q = 0;
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else
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cpu_state.MM[reg].q <<= shift;
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break;
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default:
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pclog("Bad PSxxQ (0F 73) instruction %02X\n", op);
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cpu_state.pc = cpu_state.oldpc;
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x86illegal();
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return 0;
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}
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CLOCK_CYCLES(1);
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return 0;
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}
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static int opPSLLQ_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 63)
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cpu_state.MM[cpu_reg].q = 0;
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else
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cpu_state.MM[cpu_reg].q <<= shift;
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return 0;
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}
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static int opPSLLQ_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 63)
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cpu_state.MM[cpu_reg].q = 0;
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else
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cpu_state.MM[cpu_reg].q <<= shift;
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return 0;
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}
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static int opPSRLQ_a16(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_16(fetchdat);
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MMX_GETSHIFT();
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if (shift > 63)
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cpu_state.MM[cpu_reg].q = 0;
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else
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cpu_state.MM[cpu_reg].q >>= shift;
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return 0;
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}
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static int opPSRLQ_a32(uint32_t fetchdat) {
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int shift;
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MMX_ENTER();
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fetch_ea_32(fetchdat);
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MMX_GETSHIFT();
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if (shift > 63)
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cpu_state.MM[cpu_reg].q = 0;
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else
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cpu_state.MM[cpu_reg].q >>= shift;
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return 0;
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}
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#endif /* _X86_OPS_MMX_SHIFT_H_ */
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