mirror of
https://github.com/sarah-walker-pcem/pcem.git
synced 2025-07-23 03:33:02 +02:00
733 lines
31 KiB
C
733 lines
31 KiB
C
#ifndef _X86_OPS_MOV_H_
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#define _X86_OPS_MOV_H_
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static int opMOV_AL_imm(uint32_t fetchdat) {
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AL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_AH_imm(uint32_t fetchdat) {
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AH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_BL_imm(uint32_t fetchdat) {
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BL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_BH_imm(uint32_t fetchdat) {
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BH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_CL_imm(uint32_t fetchdat) {
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CL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_CH_imm(uint32_t fetchdat) {
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CH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_DL_imm(uint32_t fetchdat) {
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DL = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_DH_imm(uint32_t fetchdat) {
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DH = getbytef();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_AX_imm(uint32_t fetchdat) {
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AX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_BX_imm(uint32_t fetchdat) {
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BX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_CX_imm(uint32_t fetchdat) {
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CX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_DX_imm(uint32_t fetchdat) {
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DX = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_SI_imm(uint32_t fetchdat) {
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SI = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_DI_imm(uint32_t fetchdat) {
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DI = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_BP_imm(uint32_t fetchdat) {
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BP = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_SP_imm(uint32_t fetchdat) {
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SP = getwordf();
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_EAX_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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EAX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_EBX_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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EBX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_ECX_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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ECX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_EDX_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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EDX = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_ESI_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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ESI = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_EDI_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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EDI = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_EBP_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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EBP = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_ESP_imm(uint32_t fetchdat) {
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uint32_t templ = getlong();
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if (cpu_state.abrt)
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return 1;
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ESP = templ;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 5, -1, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_b_imm_a16(uint32_t fetchdat) {
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uint8_t temp;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = readmemb(cs, cpu_state.pc);
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cpu_state.pc++;
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if (cpu_state.abrt)
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return 1;
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CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
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seteab(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, rmdat, 0, 0, (cpu_mod == 3) ? 1 : 0, 0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_b_imm_a32(uint32_t fetchdat) {
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uint8_t temp;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = getbyte();
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if (cpu_state.abrt)
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return 1;
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seteab(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 3, rmdat, 0, 0, (cpu_mod == 3) ? 1 : 0, 0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_w_imm_a16(uint32_t fetchdat) {
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uint16_t temp;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = getword();
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if (cpu_state.abrt)
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return 1;
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seteaw(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 4, rmdat, 0, 0, (cpu_mod == 3) ? 1 : 0, 0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_w_imm_a32(uint32_t fetchdat) {
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uint16_t temp;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = getword();
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if (cpu_state.abrt)
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return 1;
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seteaw(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 4, rmdat, 0, 0, (cpu_mod == 3) ? 1 : 0, 0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_l_imm_a16(uint32_t fetchdat) {
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uint32_t temp;
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fetch_ea_16(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = getlong();
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if (cpu_state.abrt)
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return 1;
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seteal(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 6, rmdat, 0, 0, 0, (cpu_mod == 3) ? 1 : 0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_l_imm_a32(uint32_t fetchdat) {
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uint32_t temp;
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fetch_ea_32(fetchdat);
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ILLEGAL_ON((rmdat & 0x38) != 0);
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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temp = getlong();
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if (cpu_state.abrt)
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return 1;
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seteal(temp);
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 6, rmdat, 0, 0, 0, (cpu_mod == 3) ? 1 : 0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_AL_a16(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr);
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temp = readmemb(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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AL = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_AL_a32(uint32_t fetchdat) {
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uint32_t addr = getlong();
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr);
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temp = readmemb(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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AL = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 1, 0, 0, 0, 1);
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return 0;
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}
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static int opMOV_AX_a16(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr + 1);
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temp = readmemw(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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AX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opMOV_AX_a32(uint32_t fetchdat) {
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uint32_t addr = getlong();
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr + 1);
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temp = readmemw(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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AX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 1, 0, 0, 0, 1);
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return 0;
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}
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static int opMOV_EAX_a16(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr + 3);
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temp = readmeml(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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EAX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 3, -1, 0, 1, 0, 0, 0);
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return 0;
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}
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static int opMOV_EAX_a32(uint32_t fetchdat) {
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uint32_t addr = getlong();
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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CHECK_READ(cpu_state.ea_seg, addr, addr + 3);
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temp = readmeml(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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EAX = temp;
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CLOCK_CYCLES((is486) ? 1 : 4);
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PREFETCH_RUN(4, 5, -1, 0, 1, 0, 0, 1);
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return 0;
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}
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static int opMOV_a16_AL(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememb(cpu_state.ea_seg->base, addr, AL);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0, 0, 1, 0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_AL(uint32_t fetchdat) {
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uint32_t addr = getlong();
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememb(cpu_state.ea_seg->base, addr, AL);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0, 0, 1, 0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_a16_AX(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememw(cpu_state.ea_seg->base, addr, AX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0, 0, 1, 0, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_AX(uint32_t fetchdat) {
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uint32_t addr = getlong();
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if (cpu_state.abrt)
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return 1;
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememw(cpu_state.ea_seg->base, addr, AX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0, 0, 1, 0, 1);
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return cpu_state.abrt;
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}
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static int opMOV_a16_EAX(uint32_t fetchdat) {
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uint16_t addr = getwordf();
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememl(cpu_state.ea_seg->base, addr, EAX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 3, -1, 0, 0, 0, 1, 0);
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return cpu_state.abrt;
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}
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static int opMOV_a32_EAX(uint32_t fetchdat) {
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uint32_t addr = getlong();
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if (cpu_state.abrt)
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return 1;
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SEG_CHECK_WRITE(cpu_state.ea_seg);
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writememl(cpu_state.ea_seg->base, addr, EAX);
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CLOCK_CYCLES((is486) ? 1 : 2);
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PREFETCH_RUN(2, 5, -1, 0, 0, 0, 1, 1);
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return cpu_state.abrt;
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}
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static int opLEA_w_a16(uint32_t fetchdat) {
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opLEA_w_a32(uint32_t fetchdat) {
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].w = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
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return 0;
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}
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static int opLEA_l_a16(uint32_t fetchdat) {
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fetch_ea_16(fetchdat);
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].l = cpu_state.eaaddr & 0xffff;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
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return 0;
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}
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static int opLEA_l_a32(uint32_t fetchdat) {
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fetch_ea_32(fetchdat);
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ILLEGAL_ON(cpu_mod == 3);
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cpu_state.regs[cpu_reg].l = cpu_state.eaaddr;
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CLOCK_CYCLES(timing_rr);
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PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
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return 0;
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}
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static int opXLAT_a16(uint32_t fetchdat) {
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uint32_t addr = (BX + AL) & 0xFFFF;
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmemb(cpu_state.ea_seg->base, addr);
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if (cpu_state.abrt)
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return 1;
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AL = temp;
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CLOCK_CYCLES(5);
|
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PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opXLAT_a32(uint32_t fetchdat) {
|
|
uint32_t addr = EBX + AL;
|
|
uint8_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmemb(cpu_state.ea_seg->base, addr);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
AL = temp;
|
|
CLOCK_CYCLES(5);
|
|
PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opMOV_b_r_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
setr8(cpu_rm, getr8(cpu_reg));
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
seteab(getr8(cpu_reg));
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 1, 0, 0);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
static int opMOV_b_r_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
setr8(cpu_rm, getr8(cpu_reg));
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
seteab(getr8(cpu_reg));
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 1, 0, 1);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
static int opMOV_w_r_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1);
|
|
seteaw(cpu_state.regs[cpu_reg].w);
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 1, 0, 0);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
static int opMOV_w_r_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_rm].w = cpu_state.regs[cpu_reg].w;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1);
|
|
seteaw(cpu_state.regs[cpu_reg].w);
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 1, 0, 1);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
static int opMOV_l_r_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
|
seteal(cpu_state.regs[cpu_reg].l);
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 0);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
static int opMOV_l_r_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_rm].l = cpu_state.regs[cpu_reg].l;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
SEG_CHECK_WRITE(cpu_state.ea_seg);
|
|
CHECK_WRITE(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
|
seteal(cpu_state.regs[cpu_reg].l);
|
|
CLOCK_CYCLES(is486 ? 1 : 2);
|
|
PREFETCH_RUN(2, 2, rmdat, 0, 0, 0, 1, 1);
|
|
}
|
|
return cpu_state.abrt;
|
|
}
|
|
|
|
static int opMOV_r_b_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
setr8(cpu_reg, getr8(cpu_rm));
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
uint8_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
temp = geteab();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
setr8(cpu_reg, temp);
|
|
CLOCK_CYCLES(is486 ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 1, 0, 0, 0, 0);
|
|
}
|
|
return 0;
|
|
}
|
|
static int opMOV_r_b_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
setr8(cpu_reg, getr8(cpu_rm));
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
uint8_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
|
|
temp = geteab();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
setr8(cpu_reg, temp);
|
|
CLOCK_CYCLES(is486 ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 1, 0, 0, 0, 1);
|
|
}
|
|
return 0;
|
|
}
|
|
static int opMOV_r_w_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
uint16_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1);
|
|
temp = geteaw();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
cpu_state.regs[cpu_reg].w = temp;
|
|
CLOCK_CYCLES((is486) ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 1, 0, 0, 0, 0);
|
|
}
|
|
return 0;
|
|
}
|
|
static int opMOV_r_w_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
uint16_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1);
|
|
temp = geteaw();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
cpu_state.regs[cpu_reg].w = temp;
|
|
CLOCK_CYCLES((is486) ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 1, 0, 0, 0, 1);
|
|
}
|
|
return 0;
|
|
}
|
|
static int opMOV_r_l_a16(uint32_t fetchdat) {
|
|
fetch_ea_16(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 0);
|
|
} else {
|
|
uint32_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
|
temp = geteal();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
cpu_state.regs[cpu_reg].l = temp;
|
|
CLOCK_CYCLES(is486 ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 0);
|
|
}
|
|
return 0;
|
|
}
|
|
static int opMOV_r_l_a32(uint32_t fetchdat) {
|
|
fetch_ea_32(fetchdat);
|
|
if (cpu_mod == 3) {
|
|
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l;
|
|
CLOCK_CYCLES(timing_rr);
|
|
PREFETCH_RUN(timing_rr, 2, rmdat, 0, 0, 0, 0, 1);
|
|
} else {
|
|
uint32_t temp;
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3);
|
|
temp = geteal();
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
cpu_state.regs[cpu_reg].l = temp;
|
|
CLOCK_CYCLES(is486 ? 1 : 4);
|
|
PREFETCH_RUN(4, 2, rmdat, 0, 1, 0, 0, 1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#define opCMOV(condition) \
|
|
static int opCMOV##condition##_w_a16(uint32_t fetchdat) { \
|
|
fetch_ea_16(fetchdat); \
|
|
if (cond_##condition) { \
|
|
if (cpu_mod == 3) \
|
|
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
|
|
else { \
|
|
uint16_t temp; \
|
|
SEG_CHECK_READ(cpu_state.ea_seg); \
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
|
|
temp = geteaw(); \
|
|
if (cpu_state.abrt) \
|
|
return 1; \
|
|
cpu_state.regs[cpu_reg].w = temp; \
|
|
} \
|
|
} \
|
|
CLOCK_CYCLES(1); \
|
|
return 0; \
|
|
} \
|
|
static int opCMOV##condition##_w_a32(uint32_t fetchdat) { \
|
|
fetch_ea_32(fetchdat); \
|
|
if (cond_##condition) { \
|
|
if (cpu_mod == 3) \
|
|
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
|
|
else { \
|
|
uint16_t temp; \
|
|
SEG_CHECK_READ(cpu_state.ea_seg); \
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
|
|
temp = geteaw(); \
|
|
if (cpu_state.abrt) \
|
|
return 1; \
|
|
cpu_state.regs[cpu_reg].w = temp; \
|
|
} \
|
|
} \
|
|
CLOCK_CYCLES(1); \
|
|
return 0; \
|
|
} \
|
|
static int opCMOV##condition##_l_a16(uint32_t fetchdat) { \
|
|
fetch_ea_16(fetchdat); \
|
|
if (cond_##condition) { \
|
|
if (cpu_mod == 3) \
|
|
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
|
|
else { \
|
|
uint32_t temp; \
|
|
SEG_CHECK_READ(cpu_state.ea_seg); \
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
|
|
temp = geteal(); \
|
|
if (cpu_state.abrt) \
|
|
return 1; \
|
|
cpu_state.regs[cpu_reg].l = temp; \
|
|
} \
|
|
} \
|
|
CLOCK_CYCLES(1); \
|
|
return 0; \
|
|
} \
|
|
static int opCMOV##condition##_l_a32(uint32_t fetchdat) { \
|
|
fetch_ea_32(fetchdat); \
|
|
if (cond_##condition) { \
|
|
if (cpu_mod == 3) \
|
|
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
|
|
else { \
|
|
uint32_t temp; \
|
|
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
|
|
SEG_CHECK_READ(cpu_state.ea_seg); \
|
|
temp = geteal(); \
|
|
if (cpu_state.abrt) \
|
|
return 1; \
|
|
cpu_state.regs[cpu_reg].l = temp; \
|
|
} \
|
|
} \
|
|
CLOCK_CYCLES(1); \
|
|
return 0; \
|
|
}
|
|
|
|
opCMOV(O) opCMOV(NO) opCMOV(B) opCMOV(NB) opCMOV(E) opCMOV(NE) opCMOV(BE) opCMOV(NBE) opCMOV(S) opCMOV(NS) opCMOV(P) opCMOV(NP)
|
|
opCMOV(L) opCMOV(NL) opCMOV(LE) opCMOV(NLE)
|
|
|
|
#endif /* _X86_OPS_MOV_H_ */
|