CyrIng d1a61cb80d [aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

..

bitasm.h

uBench: Code clean-up

2025-03-22 09:18:09 +01:00

corefreq-api.h

[riscv64] Fill with the Machine Architecture ID Register marchid

2025-03-29 12:46:48 +01:00

corefreq-cli-extra.c

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-extra.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-json.c

[riscv64][ppc64] Improving Hybrid processor detection

2025-03-28 19:58:14 +01:00

corefreq-cli-json.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-rsc-en.h

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-cli-rsc-fr.h

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-cli-rsc-theme-dflt.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-rsc-theme-usr1.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-rsc-theme-usr2.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-cli-rsc.c

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-cli-rsc.h

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-cli.c

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-cli.h

[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state

2025-06-23 09:14:59 +02:00

corefreq-ui.c

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq-ui.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

corefreq.h

[riscv64] Fill with the Machine Architecture ID Register marchid

2025-03-29 12:46:48 +01:00

corefreqd.c

[Doc] Obfuscate support email format in README and CLI usage

2025-05-29 09:12:38 +02:00

corefreqk.c

[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16

2025-06-05 20:46:55 +02:00

corefreqk.h

[aarch64][riscv64][ppc64] Improving DT integration to detect VM

2025-03-16 12:55:00 +01:00

corefreqm.c

[riscv64] Restore PMU counter delta calculation

2025-03-09 09:57:46 +01:00

corefreqm.h

[RISC-V] Preliminary port of the riscv64 architecture

2025-02-22 11:12:48 +01:00

coretypes.h

[Code Review] Refactored variable names for inclusivity

2025-05-08 11:17:40 +02:00

risc_reg.h

[riscv64] mvendorid & marchid based architecture qualification

2025-03-08 17:01:47 +01:00