36 Commits

Author	SHA1	Message	Date
CyrIng	d1a61cb80d	[aarch64][riscv64][ppc64] Optimize POWERED() macro with branchless 3-state	2025-06-23 09:14:59 +02:00
CyrIng	3a7c7033f2	[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16	2025-06-05 20:46:55 +02:00
CyrIng	90d4825ad0	[Kernel][6.15] Fix missing cpufreq_get_policy and asm/amd/nb.h	2025-05-31 10:05:27 +02:00
CyrIng	dfac22ae8a	[Doc] Obfuscate support email format in README and CLI usage	2025-05-29 09:12:38 +02:00
CyrIng	6b7ea15142	[aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables	2025-05-28 15:17:58 +02:00
CyrIng	6b176cd026	[Kernel] Use VM_DONTEXPAND in mmap() for stability and isolation	2025-05-28 07:01:03 +02:00
CyrIng	a3b978a2d3	[Code Review] Make module parameters load-time only (#547)	2025-05-22 19:19:09 +02:00
CyrIng	2569ef0518	[aarch64][riscv64][ppc64] Improving the CPU topology to detect BSP	2025-05-19 20:50:18 +02:00
CyrIng	e684e642d0	[UI] Increased length of L3 cache digits in header	2025-05-12 12:12:29 +02:00
CyrIng	93c7096e2b	[Code Review] Refactored variable names for inclusivity	2025-05-08 11:17:40 +02:00
CyrIng	d94626d276	[IMC] Can display Twelve Channel memory controller ... * Renamed `Disabled` to `Undefined` channels	2025-05-03 17:48:32 +02:00
CyrIng	c508b7d3f1	[CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number	2025-04-18 14:48:51 +02:00
CyrIng	2cce3ed28d	[Build] Prevent module loading if detected CPU count > CORE_COUNT	2025-04-12 09:37:20 +02:00
CyrIng	812f297a22	[Build] Kernel 6.15 is switching to use hrtimer_setup()	2025-04-09 09:54:20 +02:00
CyrIng	5c620b7f42	[Build] of_root defined since Kernel 3.19	2025-04-02 14:54:47 +02:00
CyrIng	17886cba2b	[Build] Replaced inline C functions with static or macro ... * Kernel 6.14 `node_to_amd_nb()` workaround	2025-03-31 16:49:47 +02:00
CyrIng	f97a8b41e9	[riscv64] Fill with the Machine Architecture ID Register marchid ... [ppc64] Added source comment	2025-03-29 12:46:48 +01:00
CyrIng	c0942e22c6	[riscv64][ppc64] Improving Hybrid processor detection	2025-03-28 19:58:14 +01:00
CyrIng	9a9a9651e8	[Build] Added CONFIG_ACPI_CPPC_LIB to conditionnaly build EPP	2025-03-26 14:10:27 +01:00
CyrIng	73d1856d4a	uBench: Code clean-up	2025-03-22 09:18:09 +01:00
CyrIng	f16fdf303c	[ppc64][riscv64] ASM instructions for uBench macros	2025-03-21 21:18:15 +01:00
CyrIng	5dba49ee90	[aarch64][riscv64][ppc64] Improving DT integration to detect VM	2025-03-16 12:55:00 +01:00
CyrIng	0b58936203	[ppc64][riscv64] Device Tree fetching based on kernel version	2025-03-15 00:06:53 +01:00
CyrIng	57c331e6c9	[riscv64] Adding vendor Microchip	2025-03-10 14:41:58 +01:00
CyrIng	56b2858c53	[riscv64] Attempt to read the Hart ID from device tree	2025-03-09 11:15:25 +01:00
CyrIng	b55ef76742	[riscv64] Restore PMU counter delta calculation	2025-03-09 09:57:46 +01:00
CyrIng	450189f5a4	[riscv64] mvendorid & marchid based architecture qualification	2025-03-08 17:01:47 +01:00
CyrIng	262287165f	[riscv64] Specification of SSTATUS and SCOUNTEREN registers	2025-03-05 16:59:05 +01:00
CyrIng	e69f388f0e	[riscv64] Normalize counters to work with unaccurate QEMU cycles	2025-03-04 21:35:19 +01:00
CyrIng	7704ea4ee2	[riscv64] Attempt to enable the Cycle and Instruction counters	2025-03-04 20:21:03 +01:00
CyrIng	592f85564d	[riscv64] Read the performance cycles using rdcycle	2025-03-02 15:37:17 +01:00
CyrIng	774d061f8c	[riscv64] Read the retired instructions counter using rdinstret	2025-03-01 17:17:39 +01:00
CyrIng	5c3bc58c56	[riscv64] Get the TSC from rdtime instruction	2025-02-26 19:30:51 +01:00
CyrIng	04364b8282	[riscv64] Comment out any reading of cycles	2025-02-24 02:57:13 +01:00
CyrIng	92c5e0f05f	[RISC-V] Code clean-up to debug start-up	2025-02-23 16:23:53 +01:00
CyrIng	d28166050a	[RISC-V] Preliminary port of the riscv64 architecture	2025-02-22 11:12:48 +01:00