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Author	SHA1	Message	Date
CyrIng	3a7c7033f2	[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16 2.0.7	2025-06-05 20:46:55 +02:00
CyrIng	b6223385b9	[AMD] Decodes voltages of Phoenix families using Rembrandt SVI 2.0.6	2025-06-04 12:59:45 +02:00
CyrIng	c2e28ed3ee	[AMD][Raphael] Attempt to read the SoC voltage	2025-05-31 11:46:19 +02:00
CyrIng	90d4825ad0	[Kernel][6.15] Fix missing cpufreq_get_policy and asm/amd/nb.h	2025-05-31 10:05:27 +02:00
CyrIng	2c03ceab46	[AMD][Raphael] Don't probe the HSMP on Desktop/Mobile/Embedded	2025-05-30 08:31:18 +02:00
CyrIng	dfac22ae8a	[Doc] Obfuscate support email format in README and CLI usage	2025-05-29 09:12:38 +02:00
CyrIng	0974aceba3	[Doc] Added command line usage instructions to the README	2025-05-29 08:53:41 +02:00
CyrIng	6b7ea15142	[aarch64][riscv64][ppc64] Use exclusive load/store for selected shared variables	2025-05-28 15:17:58 +02:00
CyrIng	6b176cd026	[Kernel] Use VM_DONTEXPAND in mmap() for stability and isolation	2025-05-28 07:01:03 +02:00
CyrIng	989036f384	[Intel] Added the Bartlett Lake/S entry ... * `Clearwater Forest` architecture name fix	2025-05-26 13:44:53 +02:00
CyrIng	5ec7b7c743	[AMD][Genoa] Attempt to read SOC voltage ... * Apply monitoring interval in RAM consumption calculation 2.0.5	2025-05-24 11:55:12 +02:00
CyrIng	094c2f3c27	[Kernel] If version is >= 6.0 then call SMU via CONFIG_AMD_NB ... Ryzen 9950X issue #548	2025-05-22 20:22:39 +02:00
CyrIng	a3b978a2d3	[Code Review] Make module parameters load-time only (#547)	2025-05-22 19:19:09 +02:00
CyrIng	6a99cfb4b4	[x86_64] Add lock prefix to bit ops for cross-package atomicity	2025-05-20 21:54:11 +02:00
CyrIng	2569ef0518	[aarch64][riscv64][ppc64] Improving the CPU topology to detect BSP	2025-05-19 20:50:18 +02:00
CyrIng	e7deead548	[Code Review] Intel Core Ultra: Registers name and address updated	2025-05-18 12:30:34 +02:00
CyrIng	c3704a245a	[Intel][ADL/N] Adding "Twin Lake" and "Amston Lake" codenames	2025-05-16 23:04:51 +02:00
CyrIng	398dc12544	[AMD][Zen] Count DIMM ranks from the enabled chip select 2.0.3	2025-05-14 14:33:59 +02:00
CyrIng	fcc0e0f70e	[AMD][Zen][UMC] Computes DIMM ranks based on DDR type	2025-05-12 17:13:28 +02:00
CyrIng	347045ed17	Revert "[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98" ... This reverts commit e5a5d0c1d6.	2025-05-12 15:37:08 +02:00
CyrIng	e684e642d0	[UI] Increased length of L3 cache digits in header	2025-05-12 12:12:29 +02:00
CyrIng	c2b396a215	[AMD][Zen] Now conducts Datafabric calls through Kernel PCI ... [HSMP] Provides its own lock rather than SMN' lock	2025-05-12 11:55:34 +02:00
CyrIng	22f9c460a9	[AMD][Zen] HSMP arguments index fix in CONFIG_AMD_NB build mode	2025-05-11 13:03:04 +02:00
CyrIng	acbe192ad5	[AMD][Zen] Replaced package thermal with a pointer function	2025-05-10 18:11:05 +02:00
CyrIng	43fd828bdc	[AMD][Genoa] Probe up to four memory controllers	2025-05-10 15:11:21 +02:00
CyrIng	0729f349e4	[AMD] Improved EPYC Genoa support ... * CCD and CCX topology fixed to compute the right thermal SMU address * Increase `BIT_IO_RETRIES_COUNT` to parallelize `HSMP_RD_DIMM_PWR` calls * Added specifics for an "Eng Sample" of Genoa architecture	2025-05-09 19:44:16 +02:00
CyrIng	93c7096e2b	[Code Review] Refactored variable names for inclusivity	2025-05-08 11:17:40 +02:00
CyrIng	511fa2fe4d	[AMD][Genoa] Accumulate the power consumed by RAM	2025-05-04 18:22:35 +02:00
CyrIng	e5a5d0c1d6	[AMD] In AMD_DataFabric_Genoa() offset the UMC_DIMM_CFG to 0x98	2025-05-04 07:18:23 +02:00
CyrIng	e3bb96bf85	[x86_64] Order SMBIOS DIMM list by channel	2025-05-04 06:56:49 +02:00
CyrIng	d94626d276	[IMC] Can display Twelve Channel memory controller ... * Renamed `Disabled` to `Undefined` channels	2025-05-03 17:48:32 +02:00
CyrIng	e9eed278f0	[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots	2025-05-03 16:42:40 +02:00
CyrIng	638883766b	[Kernel] VT-d: request memory region before use	2025-05-01 09:39:10 +02:00
CyrIng	adf8cbadc5	[AMD][Hawk Point] Set AddrCfg & DimmCfg addresses for Phoenix UMC	2025-04-27 11:28:24 +02:00
CyrIng	de901592a2	[AMD][Genoa] Attempt to monitor DIMM power consumption from HSMP ... * Specifications of some Zen registers	2025-04-27 10:58:53 +02:00
CyrIng	b4903129ac	[AMD][Family 1Ah] Added the HSMP for EPYC Turin ... * Check mailbox protocol is correctly functioning * using the arithmetic addition `2 + 1 = 3`	2025-04-19 13:46:46 +02:00
CyrIng	c508b7d3f1	[CLI][aarch64][riscv64][ppc64] Compute the SMBIOS DIMM part number	2025-04-18 14:48:51 +02:00
CyrIng	063fb88127	[CLI][x86_64] Compute the SMBIOS DIMM part number (rev 2)	2025-04-18 14:06:13 +02:00
CyrIng	916546f4cb	[x86_64] Check HCF capability for MPERF/APERF MSR access in VM	2025-04-16 14:21:47 +02:00
CyrIng	7064970173	[AMD][EPYC][Genoa] Use generic voltage & power	2025-04-13 10:50:04 +02:00
CyrIng	2171321cf6	[Doc] README for Rocky Linux and Clear Linux	2025-04-12 11:21:35 +02:00
CyrIng	2cce3ed28d	[Build] Prevent module loading if detected CPU count > CORE_COUNT	2025-04-12 09:37:20 +02:00
CyrIng	6509cc4ba8	[Build] Make static the PCI list to comply with kernel frame size	2025-04-10 20:14:46 +02:00
CyrIng	f055e6acad	[Intel][MTL][ARL] Improving MC Bus and DDR speed to follow OC SOC	2025-04-09 21:55:45 +02:00
CyrIng	812f297a22	[Build] Kernel 6.15 is switching to use hrtimer_setup()	2025-04-09 09:54:20 +02:00
CyrIng	4600e91f5b	[CI] Bump to uraimo version 3	2025-04-07 13:53:25 +02:00
CyrIng	b838bf059d	[Intel][MTL][ARL] Refactored IMC decoder to query DDR clock	2025-04-07 12:57:52 +02:00
CyrIng	ef11110bb7	[UI] Display N/A when Intel processor is not HDC capable	2025-04-06 13:25:42 +02:00
CyrIng	0933a336be	[Intel] Merge branch 'Arrow_Lake'	2025-04-05 11:44:22 +02:00
CyrIng	a8489b5858	[Intel][ARL] Merged the P-core and E-core monitoring loops	2025-04-05 00:42:39 +02:00