CyrIng
d0775f73c2
[Build] Enforce targets are not built more than necessary
2025-07-09 18:52:27 +02:00
CyrIng
a5ca660a50
[Build] Clarify Makefile help, info, and version targets
2025-07-09 12:43:31 +02:00
CyrIng
a9bd15efe3
[aarch64] Getting temperature from the Generic Thermal Management
2025-07-07 16:39:47 +02:00
CyrIng
78b27bb575
[Build] Support building CoreFreq binaries individually or together
2025-06-22 13:03:15 +02:00
CyrIng
3a7c7033f2
[Kernel] Defer cpufreq get_policy and asm/amd/nb.h to v6.16
2025-06-05 20:46:55 +02:00
CyrIng
989036f384
[Intel] Added the Bartlett Lake/S entry
...
* `Clearwater Forest` architecture name fix
2025-05-26 13:44:53 +02:00
CyrIng
6a99cfb4b4
[x86_64] Add lock prefix to bit ops for cross-package atomicity
2025-05-20 21:54:11 +02:00
CyrIng
c3704a245a
[Intel][ADL/N] Adding "Twin Lake" and "Amston Lake" codenames
2025-05-16 23:04:51 +02:00
CyrIng
e9eed278f0
[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots
2025-05-03 16:42:40 +02:00
CyrIng
a44d56c315
Merge branch 'hotfix_optimizations'
2025-03-31 12:16:27 +02:00
CyrIng
5dba49ee90
[aarch64][riscv64][ppc64] Improving DT integration to detect VM
2025-03-16 12:55:00 +01:00
CyrIng
f314201943
[Build] Changed some inline function prototypes
2025-02-23 08:05:03 +01:00
Slawomir Stepien
6b93c1d7ed
[Build] Allow changing WARNING variable from command line
...
User should be able to change the WARNING build variable during make
invocation.
This change also specifies what is the true default value for that
variable.
2025-01-20 10:38:41 +01:00
CyrIng
17a08f536a
Copyright (C) 2015-2025 CYRIL COURTIAT
2025-01-19 13:15:05 +01:00
CyrIng
ad6730c83d
Version 2 ; Experience version
2024-12-24 07:53:04 +01:00
CyrIng
6436a4851d
[AArch64] Access HCR_EL2 based on CurrentEL bits
2024-11-22 19:02:52 +01:00
CyrIng
7ee38f9284
[AMD][Family 1Ah] Merge PCI identifier lists
2024-11-17 10:44:28 +01:00
CyrIng
6b28cc2007
[AMD][Family 1Ah] Refactoring topology for CCD cluster
2024-11-13 12:12:24 +01:00
CyrIng
976cd051f4
[Build] Print other variables from Makefile recipe info
...
CORE_COUNT
TASK_ORDER
MAX_FREQ_HZ
HWM_CHIPSET
2024-11-09 08:49:44 +01:00
CyrIng
d484bd999a
[AMD][Zen5][Zen5c] Introducing the TURIN architecture
2024-10-12 16:09:09 +02:00
CyrIng
3b9eb7d26f
[Build] Makefile compliant with the -s silent option
2024-09-29 12:22:33 +02:00
CyrIng
92ff25bf9f
[x86_64][Virtualization] Switch to HCF or VP_RUNTIME counters
2024-08-30 12:49:11 +02:00
CyrIng
85b1e62618
[AMD][VMR/RPL/GNR] Voltage Curve Optimizer HWM CHIPSET=AMD VCO
2024-08-25 13:09:07 +02:00
CyrIng
0e37a13498
[Zen5/Granite Ridge] Changed the Voltage formula identifier
2024-08-19 08:59:43 +02:00
CyrIng
5a3c3963ba
[Intel] Deny MSR_FLEX_RATIO access to Nehalem/Bloomfield(06_1A)
2024-08-08 12:12:29 +02:00
CyrIng
e8fe368fd3
[Doc] Refreshed README and Makefile
2024-08-06 19:01:28 +02:00
CyrIng
70a527c5cd
[Build] Now leave version number in Makefile
...
[Build] Pretty print the build and the clean of outputs
* Allow the `V=n` option increase the verbose level (incl. kernel)
2024-08-04 15:10:21 +02:00
CyrIng
9b644fd509
[CLI] UI_RULER_MINIMUM & UI_RULER_MAXIMUM building constraints
2024-06-09 11:30:31 +02:00
CyrIng
5c345101f6
[Build] Build time optimizations
2024-01-24 08:07:59 +01:00
CyrIng
73774ee734
Copyright (C) 2015-2024 CYRIL COURTIAT
2023-12-31 22:55:39 +01:00
CyrIng
439885fe81
[AArch64] Swap PMU counters for C0:UCC and C0:URC
...
* Save/Restore more PMU registers
* Force using Kernel delay to estimate BCLK
2023-12-30 12:00:24 +01:00
CyrIng
d855bb0bed
[Build] Improving the parallel execution
2023-12-17 19:09:31 +01:00
CyrIng
3512685664
[Build] Creating a new recipe to uninstall binaries
...
* DKMS, CKMS are now using default extra modules directories
2023-11-18 21:39:35 +01:00
CyrIng
55c27a5e30
[x86_64] Fix SymLinks creation for Alpine Linux compatibility: #461
2023-09-24 11:28:25 +02:00
CyrIng
06e647dd46
[AArch64] Use of Q constraint in inline asm
...
A memory address which uses a single base register with no offset
2023-07-22 14:19:00 +02:00
CyrIng
79e5d271a1
[Build] Make use of variables for system commands
2023-07-21 06:54:45 +02:00
CyrIng
1361739c14
Refactoring for other hardware architectures
2023-07-16 03:33:25 +02:00
CyrIng
ddbe97be73
[Doc] Miscellaneous Packages
2023-06-03 12:35:12 +02:00
CyrIng
46d554746e
[Intel] MSR registers which increment at the same rate as the TSC.
...
MSR registers related to Hardware Duty Cycling (HDC)
2023-01-28 19:05:41 +00:00
CyrIng
5461e356a6
Based on Raptor Lake, raise MAX_FREQ_HZ up to 7125000000 Hertz
2023-01-19 12:10:38 +00:00
CyrIng
45fab8fc7b
(C)2015-2023 CYRIL COURTIAT
2023-01-03 07:10:54 +00:00
CyrIng
75e57ebcae
(C)2015-2022 CYRIL COURTIAT
2022-12-07 08:50:07 +00:00
CyrIng
5dc3b62b58
ClockSource: TSC udelay() asm implementation builtin as a default
2022-08-30 10:08:06 +00:00
CyrIng
5bfcfce7da
Intel/ADL/IMC: Fixing the Memory Channels count (issue #351 )
...
SMBIOS: Various enhancements
2022-08-06 10:22:56 +00:00
CyrIng
f2aff9895c
Resolving symbols and latency issues
2022-05-10 19:13:15 +00:00
CyrIng
9bd2fffe82
Compile Architectural Counters using the build definition ARCH_PMC:
...
* Intel/SKL = {PCU}
* AMD/Zen = {L3, PERF, UMC}
2022-03-25 12:32:21 +01:00
CyrIng
39dbf3121a
[UI] Auto make RSC_LAYOUT_PACKAGE_FABRIC_CODE based on AMD_ZEN_PMC
2022-03-13 19:56:40 +01:00
CyrIng
90e711efc5
[AMD/Zen] Monitoring the UMC channel frequencies via SMU/PMC
2022-03-12 00:32:45 +01:00
CyrIng
51b6db13d3
[AMD/Zen] PMC enhancements.
2022-03-11 12:07:41 +01:00
CyrIng
09a50aee51
[AMD/Zen] Programming MSR PERF_CTL for "Micro-ops Retired" event
...
* One needs to build with 'make AMD_ZEN_PMU=PERF'
Default is 'AMD_ZEN_PMU=L3'
* Fix the General Core Performance Counters as 48 bits
2022-03-11 04:00:45 +01:00
