[AArch64] Use of Q constraint in inline asm

A memory address which uses a single base register with no offset
2025-07-23 20:20:40 +02:00 · 2023-07-22 14:19:00 +02:00
parent 73a2cfa0e3
commit 06e647dd46
3 changed files with 48 additions and 46 deletions
--- a/2
+++ b/2
@@ -4,7 +4,7 @@

 HW = $(shell uname -m)
 CC ?= cc
-WARNING = -Wall -Wfatal-errors
+WARNING = -Wall -Wfatal-errors -Wno-unused-variable
 SYMLINK ?= ln -rs
 INSTALL ?= install
 MKDIR ?= mkdir
--- a/aarch64/bitasm.h
+++ b/aarch64/bitasm.h
@@ -181,7 +181,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 		"orr	x1, x1, x3"		"\n\t"			\
 		"str	x1, %[base]"					\
 		: [ret] "+m" (_ret),					\
-		  [base] "=m" (_base)					\
+		  [base] "=Q" (_base)					\
 		: [offset] "r" (_offset)				\
 		: "cc", "memory", "%x0", "%x1", "%x2", "%x3"		\
 	);								\
@@ -203,7 +203,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 		"orr	x1, x1, x2"		"\n\t"			\
 		"str	x1, %[base]"					\
 		: [ret] "+m" (_ret),					\
-		  [base] "=m" (_base)					\
+		  [base] "=Q" (_base)					\
 		: [imm8] "i" (_imm8)					\
 		: "cc", "memory", "%x0", "%x1", "%x2"			\
 	);								\
@@ -226,7 +226,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 		"bic	x1, x1, x3"		"\n\t"			\
 		"str	x1, %[base]"					\
 		: [ret] "+m" (_ret),					\
-		  [base] "=m" (_base)					\
+		  [base] "=Q" (_base)					\
 		: [offset] "r" (_offset)				\
 		: "cc", "memory", "%x0", "%x1", "%x2", "%x3"		\
 	);								\
@@ -248,7 +248,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 		"bic	x1, x1, x2"		"\n\t"			\
 		"str	x1, %[base]"					\
 		: [ret] "+m" (_ret),					\
-		  [base] "=m" (_base)					\
+		  [base] "=Q" (_base)					\
 		: [imm8] "i" (_imm8)					\
 		: "cc", "memory", "%x0", "%x1", "%x2"			\
 	);								\
@@ -284,7 +284,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 	__asm__ volatile						\
 	(								\
 		"tst	%x[base], %x[offset]"	"\n\t"			\
-		"cset	%w[ret], eq"					\
+		"cset	%x[ret], eq"					\
 		: [ret] "+r" (_ret)					\
 		: [base] "r" (_base),					\
 		  [offset] "r" (_offset)				\
@@ -299,12 +299,14 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 									\
 	__asm__ volatile						\
 	(								\
-		"tst	%x[base], %[imm8]"	"\n\t"			\
-		"cset	%w[ret], eq"					\
+		"mov	x2, #1" 		"\n\t"			\
+		"lsl	x2, x2, %[imm8]"	"\n\t"			\
+		"tst	%x[base], x2"		"\n\t"			\
+		"cset	%x[ret], eq"					\
 		: [ret] "+r" (_ret)					\
 		: [base] "r" (_base),					\
 		  [imm8] "i" (_imm8)					\
-		: "cc", "memory"					\
+		: "cc", "memory", "%x2" 				\
 	);								\
 	_ret;								\
 })
@@ -315,12 +317,15 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 									\
 	__asm__ volatile						\
 	(								\
-		"tst	%x[base], %x[offset]"	"\n\t"			\
-		"cset	%w[ret], eq"					\
+		"mov	x2, %x[offset]" 	"\n\t"			\
+		"mov	x3, #1" 		"\n\t"			\
+		"lsl	x3, x3, x2"		"\n\t"			\
+		"tst	%x[base], x3"		"\n\t"			\
+		"cset	%x[ret], ne"					\
 		: [ret] "+r" (_ret)					\
 		: [base] "r" (_base),					\
 		  [offset] "r" (_offset)				\
-		: "cc", "memory"					\
+		: "cc", "memory", "%x2", "%x3"				\
 	);								\
 	_ret;								\
 })
@@ -334,7 +339,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 		"mov	x2, #1" 		"\n\t"			\
 		"lsl	x2, x2, %[imm8]"	"\n\t"			\
 		"tst	%x[base], x2"		"\n\t"			\
-		"cset	%w[ret], eq"					\
+		"cset	%x[ret], ne"					\
 		: [ret] "+r" (_ret)					\
 		: [base] "r" (_base),					\
 		  [imm8] "i" (_imm8)					\
@@ -431,15 +436,14 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 #define BITCPL(_src)							\
 ({									\
 	unsigned long long _dest;					\
-/*TODO									\
+									\
 	__asm__ volatile						\
 	(								\
-		"movq	%[src], %[dest]"	"\n\t"			\
-		"negq	%[dest]"					\
-		: [dest] "=m" (_dest)					\
+		"neg	%x[dest], %x[src]"				\
+		: [dest] "=rQ" (_dest)					\
 		: [src] "ir" (_src)					\
 		: "cc", "memory"					\
-	);							*/	\
+	);								\
 	_dest;								\
 })

@@ -481,23 +485,23 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 	__asm__ volatile						\
 	(								\
 		"str	%[src], %[dest]"				\
-		: [dest] "=m" (_dest)					\
-		: [src] "Jmr" (_src)					\
+		: [dest] "=Q" (_dest)					\
+		: [src] "r" (_src)					\
 		: "cc", "memory"					\
 	);								\
 })

 #define BITZERO(_lock, _src)						\
 ({									\
-	Bit64 _tmp __attribute__ ((aligned (8))) = _src;		\
 	volatile unsigned char _ret = 0;				\
 									\
 	__asm__ volatile						\
 	(								\
-	_lock	"orr	%[tmp], %[tmp], xzr"		"\n\t"		\
-		"cset	%[ret], ne" 					\
+		"clz	%x[ret], %x[src]"		"\n\t"		\
+		"cmp	%x[ret], #64"			"\n\t"		\
+		"cset	%x[ret], eq" 					\
 		: [ret] "+r" (_ret)					\
-		: [tmp] "r" (_tmp)					\
+		: [src] "r" (_src)					\
 		: "cc", "memory"					\
 	);								\
 	_ret;								\
@@ -645,7 +649,7 @@ ASM_RDTSC_PMCx1(x4, x5, ASM_RDTSCP, mem_tsc, __VA_ARGS__)
 ({									\
 	__asm__ volatile						\
 	(								\
-	_lock	"mov	%[dest], xzr"					\
+		"mov	%[dest], xzr"					\
 		: [dest] "=r" (_dest)					\
 		:							\
 		: "cc", "memory"					\
@@ -754,8 +758,8 @@ FEAT_MSG("LEGACY Level 1: BITCMP_CC() built without asm cmpxchg16b")
 			"cset	x2	,	eq"		"\n\t"	\
 			"str	x2	,	%[ret]" 		\
 			: [ret]	"+m"	(_ret)				\
-			: [opl] "m"	(_opl[cw]),			\
-			  [opr] "m"	(_opr[cw])			\
+			: [opl] "Q"	(_opl[cw]),			\
+			  [opr] "Q"	(_opr[cw])			\
 			: "cc", "memory", "%x2", "%x6", "%x7"		\
 		);							\
 		ret &= _ret;						\
--- a/aarch64/corefreqk.c
+++ b/aarch64/corefreqk.c
@@ -39,16 +39,18 @@
 #include <linux/sched/signal.h>
 #endif /* KERNEL_VERSION(4, 11, 0) */
 #include <linux/clocksource.h>
-/*TODO(CleanUp)
+#ifdef CONFIG_X86_64
 #include <asm/msr.h>
+#endif
+#if defined(CONFIG_HAVE_NMI) && defined(CONFIG_X86_64)
 #include <asm/nmi.h>
-*/
+#endif
 #ifdef CONFIG_XEN
 #include <xen/xen.h>
 #endif /* CONFIG_XEN */
-/*TODO(CleanUp)
+#ifdef CONFIG_X86_64
 #include <asm/mwait.h>
-*/
+#endif
 #ifdef CONFIG_AMD_NB
 #include <asm/amd_nb.h>
 #endif
@@ -21082,11 +21084,12 @@ void MatchPeerForDownService(SERVICE_PROC *pService, unsigned int cpu)
 }

 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
+#if defined(CONFIG_HAVE_NMI) && defined(CONFIG_X86_64)
 static int CoreFreqK_NMI_Handler(unsigned int type, struct pt_regs *pRegs)
 {
 	unsigned int cpu = smp_processor_id();
 	UNUSED(pRegs);
-/*TODO(CleanUp)
+
 	switch (type) {
 	case NMI_LOCAL:
 		PUBLIC(RO(Core, AT(cpu)))->Interrupt.NMI.LOCAL++;
@@ -21102,9 +21105,8 @@ static int CoreFreqK_NMI_Handler(unsigned int type, struct pt_regs *pRegs)
 		break;
 	}
 	return NMI_DONE;
-*/
-	return 0;
 }
+#endif /* CONFIG_HAVE_NMI */

 static long CoreFreqK_UnRegister_CPU_Idle(void)
 {
@@ -21233,9 +21235,9 @@ static long CoreFreqK_Register_Governor(void)

 static void CoreFreqK_Register_NMI(void)
 {
+#if defined(CONFIG_HAVE_NMI) && defined(CONFIG_X86_64)
  if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 0)
  {
-/*TODO(CleanUp)
    if(register_nmi_handler(NMI_LOCAL,
 			CoreFreqK_NMI_Handler,
 			0,
@@ -21245,11 +21247,9 @@ static void CoreFreqK_Register_NMI(void)
    } else {
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL);
    }
-*/
  }
  if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN) == 0)
  {
-/*TODO(CleanUp)
    if(register_nmi_handler(NMI_UNKNOWN,
 			CoreFreqK_NMI_Handler,
 			0,
@@ -21259,11 +21259,9 @@ static void CoreFreqK_Register_NMI(void)
    } else {
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN);
    }
-*/
  }
  if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR) == 0)
  {
-/*TODO(CleanUp)
    if(register_nmi_handler(NMI_SERR,
 			CoreFreqK_NMI_Handler,
 			0,
@@ -21273,11 +21271,9 @@ static void CoreFreqK_Register_NMI(void)
    } else {
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR);
    }
-*/
  }
  if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK) == 0)
  {
-/*TODO(CleanUp)
    if(register_nmi_handler(NMI_IO_CHECK,
 			CoreFreqK_NMI_Handler,
 			0,
@@ -21287,32 +21283,34 @@ static void CoreFreqK_Register_NMI(void)
    } else {
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK);
    }
-*/
  }
+#endif /* CONFIG_HAVE_NMI */
 }

 static void CoreFreqK_UnRegister_NMI(void)
 {
+#if defined(CONFIG_HAVE_NMI) && defined(CONFIG_X86_64)
    if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL) == 1)
    {
-/*TODO	unregister_nmi_handler(NMI_LOCAL, "corefreqk");		*/
+	unregister_nmi_handler(NMI_LOCAL, "corefreqk");
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_LOCAL);
    }
    if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN) == 1)
    {
-/*TODO	unregister_nmi_handler(NMI_UNKNOWN, "corefreqk");	*/
+	unregister_nmi_handler(NMI_UNKNOWN, "corefreqk");
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_UNKNOWN);
    }
    if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR) == 1)
    {
-/*TODO	unregister_nmi_handler(NMI_SERR, "corefreqk");		*/
+	unregister_nmi_handler(NMI_SERR, "corefreqk");
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_SERR);
    }
    if (BITVAL(PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK) == 1)
    {
-/*TODO	unregister_nmi_handler(NMI_IO_CHECK, "corefreqk");	*/
+	unregister_nmi_handler(NMI_IO_CHECK, "corefreqk");
 	BITCLR(LOCKLESS, PUBLIC(RO(Proc))->Registration.NMI, BIT_NMI_IO_CHECK);
    }
+#endif /* CONFIG_HAVE_NMI */
 }
 #else
 static void CoreFreqK_Register_NMI(void) {}