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[AMD/Zen] PMC enhancements.

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This commit is contained in:
CyrIng
2022-03-11 12:07:41 +01:00
parent 09a50aee51
commit 51b6db13d3
10 changed files with 217 additions and 40 deletions
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6
Makefile
View File

@@ -13,7 +13,7 @@ TASK_ORDER = 5
MAX_FREQ_HZ ?= 6575000000
MSR_CORE_PERF_UCC ?= MSR_IA32_APERF
MSR_CORE_PERF_URC ?= MSR_IA32_MPERF
AMD_ZEN_PMU ?= L3
AMD_ZEN_PMC ?= L3
obj-m := corefreqk.o
ccflags-y := -D CORE_COUNT=$(CORE_COUNT) \
@@ -47,7 +47,7 @@ endif
ccflags-y += -D MSR_CORE_PERF_UCC=$(MSR_CORE_PERF_UCC)
ccflags-y += -D MSR_CORE_PERF_URC=$(MSR_CORE_PERF_URC)
ccflags-y += -D AMD_ZEN_PMU=$(AMD_ZEN_PMU)
ccflags-y += -D AMD_ZEN_PMC=$(AMD_ZEN_PMC)
ifneq ($(HWM_CHIPSET),)
ccflags-y += -D HWM_CHIPSET=$(HWM_CHIPSET)
@@ -154,7 +154,7 @@ info:
$(info OPTIM_LVL [$(OPTIM_LVL)])
$(info MSR_CORE_PERF_UCC [$(MSR_CORE_PERF_UCC)])
$(info MSR_CORE_PERF_URC [$(MSR_CORE_PERF_URC)])
$(info AMD_ZEN_PMU [$(AMD_ZEN_PMU)])
$(info AMD_ZEN_PMC [$(AMD_ZEN_PMC)])
$(info NO_HEADER [$(NO_HEADER)])
$(info NO_FOOTER [$(NO_FOOTER)])
$(info NO_UPPER [$(NO_UPPER)])

33
corefreq-cli-rsc-en.h
View File

@@ -383,6 +383,15 @@
#define RSC_LAYOUT_PACKAGE_PC10_CODE_EN {'P', 'C', '1', '0'}
#define RSC_LAYOUT_PACKAGE_MC06_CODE_EN {'M', 'C', '0', '6'}
#define RSC_LAYOUT_PACKAGE_CTR0_CODE_EN {'C', 'T', 'R', '0'}
#define RSC_LAYOUT_PACKAGE_CTR1_CODE_EN {'C', 'T', 'R', '1'}
#define RSC_LAYOUT_PACKAGE_CTR2_CODE_EN {'C', 'T', 'R', '2'}
#define RSC_LAYOUT_PACKAGE_CTR3_CODE_EN {'C', 'T', 'R', '3'}
#define RSC_LAYOUT_PACKAGE_CTR4_CODE_EN {'C', 'T', 'R', '4'}
#define RSC_LAYOUT_PACKAGE_CTR5_CODE_EN {'C', 'T', 'R', '5'}
#define RSC_LAYOUT_PACKAGE_CTR6_CODE_EN {'C', 'T', 'R', '6'}
#define RSC_LAYOUT_PACKAGE_CTR7_CODE_EN {'C', 'T', 'R', '7'}
#define RSC_LAYOUT_PACKAGE_UNCORE_CODE_EN \
{ \
' ','T','S','C',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
@@ -407,6 +416,30 @@
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \
}
#define RSC_LAYOUT_PACKAGE_FABRIC_CODE_EN \
{ \
' ','T','S','C',':',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ','F','A','B','R','I','C',':',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',\
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ',' ' \
}
#define RSC_LAYOUT_TASKS_STATE_SORTED_CODE_EN \
{ \
'(','s','o','r','t','e','d',' ', 'b','y', \

10
corefreq-cli-rsc-fr.h
View File

@@ -150,7 +150,17 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_LAYOUT_PACKAGE_PC10_CODE_FR RSC_LAYOUT_PACKAGE_PC10_CODE_EN
#define RSC_LAYOUT_PACKAGE_MC06_CODE_FR RSC_LAYOUT_PACKAGE_MC06_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR0_CODE_FR RSC_LAYOUT_PACKAGE_CTR0_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR1_CODE_FR RSC_LAYOUT_PACKAGE_CTR1_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR2_CODE_FR RSC_LAYOUT_PACKAGE_CTR2_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR3_CODE_FR RSC_LAYOUT_PACKAGE_CTR3_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR4_CODE_FR RSC_LAYOUT_PACKAGE_CTR4_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR5_CODE_FR RSC_LAYOUT_PACKAGE_CTR5_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR6_CODE_FR RSC_LAYOUT_PACKAGE_CTR6_CODE_EN
#define RSC_LAYOUT_PACKAGE_CTR7_CODE_FR RSC_LAYOUT_PACKAGE_CTR7_CODE_EN
#define RSC_LAYOUT_PACKAGE_UNCORE_CODE_FR RSC_LAYOUT_PACKAGE_UNCORE_CODE_EN
#define RSC_LAYOUT_PACKAGE_FABRIC_CODE_FR RSC_LAYOUT_PACKAGE_FABRIC_CODE_EN
#define RSC_LAYOUT_TASKS_STATE_SORTED_CODE_FR \
{ \

29
corefreq-cli-rsc-theme-dflt.h
View File

@@ -5,7 +5,7 @@
*/
#define RSC_THEME_DFLT_CODE /* 72 chars */ \
" Default theme by CyrIng. Since 2015; updated Feb. 2022 "
" Default theme by CyrIng. Since 2015; updated Mar. 2022 "
#define RSC_UI_THM_DFLT_ATTR \
{ \
@@ -858,6 +858,30 @@
#define RSC_LAYOUT_PACKAGE_MC06_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR0_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR1_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR2_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR3_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR4_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR5_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR6_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_CTR7_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_DFLT_ATTR
#define RSC_LAYOUT_PACKAGE_UNCORE_THM_DFLT_ATTR \
{ \
LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\
@@ -882,6 +906,9 @@
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
}
#define RSC_LAYOUT_PACKAGE_FABRIC_THM_DFLT_ATTR \
RSC_LAYOUT_PACKAGE_UNCORE_THM_DFLT_ATTR
#define RSC_LAYOUT_RULER_TASKS_THM_DFLT_ATTR \
{ \
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\

29
corefreq-cli-rsc-theme-usr1.h
View File

@@ -5,7 +5,7 @@
*/
#define RSC_THEME_USR1_CODE /* 72 chars */ \
" Strawberry theme by CyrIng. Updated by CyrIng - Feb. 2022 "
" Strawberry theme by CyrIng. Updated by CyrIng - Mar. 2022 "
#define RSC_UI_THM_USR1_ATTR \
{ \
@@ -858,6 +858,30 @@
#define RSC_LAYOUT_PACKAGE_MC06_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR0_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR1_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR2_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR3_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR4_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR5_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR6_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_CTR7_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR1_ATTR
#define RSC_LAYOUT_PACKAGE_UNCORE_THM_USR1_ATTR \
{ \
LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,\
@@ -882,6 +906,9 @@
LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW \
}
#define RSC_LAYOUT_PACKAGE_FABRIC_THM_USR1_ATTR \
RSC_LAYOUT_PACKAGE_UNCORE_THM_USR1_ATTR
#define RSC_LAYOUT_RULER_TASKS_THM_USR1_ATTR \
{ \
LKW,LKW,LKW,LKW,LKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,HKW,LKW,LKW,LKW,\

29
corefreq-cli-rsc-theme-usr2.h
View File

@@ -5,7 +5,7 @@
*/
#define RSC_THEME_USR2_CODE /* 72 chars */ \
" Transparent theme by leaty. Updated by CyrIng - Feb. 2022 "
" Transparent theme by leaty. Updated by CyrIng - Mar. 2022 "
#define RSC_UI_THM_USR2_ATTR \
{ \
@@ -858,6 +858,30 @@
#define RSC_LAYOUT_PACKAGE_MC06_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR0_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR1_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR2_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR3_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR4_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR5_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR6_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_CTR7_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_PC_THM_USR2_ATTR
#define RSC_LAYOUT_PACKAGE_UNCORE_THM_USR2_ATTR \
{ \
LWK,LWK,LWK,LWK,HDK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,HWK,\
@@ -882,6 +906,9 @@
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK \
}
#define RSC_LAYOUT_PACKAGE_FABRIC_THM_USR2_ATTR \
RSC_LAYOUT_PACKAGE_UNCORE_THM_USR2_ATTR
#define RSC_LAYOUT_RULER_TASKS_THM_USR2_ATTR \
{ \
LWK,LWK,LWK,LWK,LWK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,HDK,LWK,LWK,LWK,\

18
corefreq-cli-rsc.c
View File

@@ -151,7 +151,16 @@ DEF_LDA(RSC_LAYOUT_PACKAGE_PC08);
DEF_LDA(RSC_LAYOUT_PACKAGE_PC09);
DEF_LDA(RSC_LAYOUT_PACKAGE_PC10);
DEF_LDA(RSC_LAYOUT_PACKAGE_MC06);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR0);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR1);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR2);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR3);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR4);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR5);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR6);
DEF_LDA(RSC_LAYOUT_PACKAGE_CTR7);
DEF_LDA(RSC_LAYOUT_PACKAGE_UNCORE);
DEF_LDA(RSC_LAYOUT_PACKAGE_FABRIC);
DEF_LDA(RSC_LAYOUT_RULER_TASKS);
DEF_LDA(RSC_LAYOUT_TASKS_TRACKING);
DEF_LDA(RSC_LAYOUT_TASKS_STATE_SORTED);
@@ -362,7 +371,16 @@ RESOURCE_ST Resource[] = {
LDA(RSC_LAYOUT_PACKAGE_PC09),
LDA(RSC_LAYOUT_PACKAGE_PC10),
LDA(RSC_LAYOUT_PACKAGE_MC06),
LDA(RSC_LAYOUT_PACKAGE_CTR0),
LDA(RSC_LAYOUT_PACKAGE_CTR1),
LDA(RSC_LAYOUT_PACKAGE_CTR2),
LDA(RSC_LAYOUT_PACKAGE_CTR3),
LDA(RSC_LAYOUT_PACKAGE_CTR4),
LDA(RSC_LAYOUT_PACKAGE_CTR5),
LDA(RSC_LAYOUT_PACKAGE_CTR6),
LDA(RSC_LAYOUT_PACKAGE_CTR7),
LDA(RSC_LAYOUT_PACKAGE_UNCORE),
LDA(RSC_LAYOUT_PACKAGE_FABRIC),
LDA(RSC_LAYOUT_RULER_TASKS),
LDA(RSC_LAYOUT_TASKS_TRACKING),
LDA(RSC_LAYOUT_TASKS_STATE_SORTED),

9
corefreq-cli-rsc.h
View File

@@ -176,7 +176,16 @@ enum {
RSC_LAYOUT_PACKAGE_PC09,
RSC_LAYOUT_PACKAGE_PC10,
RSC_LAYOUT_PACKAGE_MC06,
RSC_LAYOUT_PACKAGE_CTR0,
RSC_LAYOUT_PACKAGE_CTR1,
RSC_LAYOUT_PACKAGE_CTR2,
RSC_LAYOUT_PACKAGE_CTR3,
RSC_LAYOUT_PACKAGE_CTR4,
RSC_LAYOUT_PACKAGE_CTR5,
RSC_LAYOUT_PACKAGE_CTR6,
RSC_LAYOUT_PACKAGE_CTR7,
RSC_LAYOUT_PACKAGE_UNCORE,
RSC_LAYOUT_PACKAGE_FABRIC,
RSC_LAYOUT_RULER_TASKS,
RSC_LAYOUT_TASKS_TRACKING,
RSC_LAYOUT_TASKS_STATE_SORTED,

38
corefreq-cli.c
View File

@@ -14649,7 +14649,7 @@ CUINT Layout_Ruler_Interrupts(Layer *layer, const unsigned int cpu, CUINT row)
CUINT Layout_Ruler_Package(Layer *layer, const unsigned int cpu, CUINT row)
{
ASCII *hCState[9] = {
const ASCII *Intel_CState[9] = {
RSC(LAYOUT_PACKAGE_PC02).CODE(),
RSC(LAYOUT_PACKAGE_PC03).CODE(),
RSC(LAYOUT_PACKAGE_PC04).CODE(),
@@ -14659,7 +14659,18 @@ CUINT Layout_Ruler_Package(Layer *layer, const unsigned int cpu, CUINT row)
RSC(LAYOUT_PACKAGE_PC09).CODE(),
RSC(LAYOUT_PACKAGE_PC10).CODE(),
RSC(LAYOUT_PACKAGE_MC06).CODE()
};
}, *AMD_CState[9] = {
RSC(LAYOUT_PACKAGE_CTR0).CODE(),
RSC(LAYOUT_PACKAGE_CTR1).CODE(),
RSC(LAYOUT_PACKAGE_CTR2).CODE(),
RSC(LAYOUT_PACKAGE_CTR3).CODE(),
RSC(LAYOUT_PACKAGE_CTR4).CODE(),
RSC(LAYOUT_PACKAGE_CTR5).CODE(),
RSC(LAYOUT_PACKAGE_CTR6).CODE(),
RSC(LAYOUT_PACKAGE_CTR7).CODE(),
RSC(LAYOUT_PACKAGE_MC06).CODE()
}, **hCState = RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_INTEL ?
Intel_CState : AMD_CState;
LayerFillAt( layer, 0, row, Draw.Size.width,
RSC(LAYOUT_RULER_PACKAGE).CODE(),
@@ -14682,10 +14693,17 @@ CUINT Layout_Ruler_Package(Layer *layer, const unsigned int cpu, CUINT row)
}
LayerDeclare( LAYOUT_PACKAGE_UNCORE, Draw.Size.width,
0, (row + 10), hUncore);
0, (row + 10), Intel_Uncore);
LayerCopyAt( layer, hUncore.origin.col, hUncore.origin.row,
hUncore.length, hUncore.attr, hUncore.code);
LayerDeclare( LAYOUT_PACKAGE_FABRIC, Draw.Size.width,
0, (row + 10), AMD_Fabric);
const LAYER_DECL_ST *hUncore = \
RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_INTEL ?
&Intel_Uncore : &AMD_Fabric;
LayerCopyAt( layer, hUncore->origin.col, hUncore->origin.row,
hUncore->length, hUncore->attr, hUncore->code);
LayerFillAt( layer, 0, (row + 11),
Draw.Size.width, hLine,
@@ -17084,12 +17102,16 @@ CUINT Draw_AltMonitor_Package(Layer *layer, const unsigned int cpu, CUINT row)
bar0, hBar, bar1, hSpace);
memcpy(&LayerAt(layer, code, 5, (row + 8)), Buffer, len);
/* TSC & UNCORE */
/* TSC */
StrLenFormat(len, Buffer, Draw.Area.LoadWidth,
"%18llu" "%.*s" "UNCORE:%18llu",
PFlop->Delta.PTSC, 7+2+18, hSpace, PFlop->Uncore.FC0);
"%18llu", PFlop->Delta.PTSC);
memcpy(&LayerAt(layer, code, 5, (row + 9)), Buffer, len);
/* UNCORE */
StrLenFormat(len, Buffer, Draw.Area.LoadWidth,
"%18llu", PFlop->Uncore.FC0);
memcpy(&LayerAt(layer, code, 5+18+7+2+18+7, (row + 9)), Buffer, len);
row += 1 + 10;
return row;

56
corefreqk.c
View File

@@ -10758,7 +10758,7 @@ void Intel_Core_Counters_Set(CORE_RO *Core)
}
}
#define AMD_Core_Counters_Set(Core, PMU) \
#define AMD_Core_Counters_Set(Core, PMC) \
({ \
if (PUBLIC(RO(Proc))->Features.PerfMon.EBX.InstrRetired == 0) \
{ \
@@ -10766,7 +10766,7 @@ void Intel_Core_Counters_Set(CORE_RO *Core)
\
RDMSR(HwCfgRegister, MSR_K7_HWCR); \
Core->SaveArea.Core_HardwareConfiguration = HwCfgRegister; \
HwCfgRegister.PMU.IRPerfEn = 1 ; \
HwCfgRegister.PMC.IRPerfEn = 1 ; \
WRMSR(HwCfgRegister, MSR_K7_HWCR); \
} \
})
@@ -10807,12 +10807,12 @@ void Intel_Core_Counters_Set(CORE_RO *Core)
WRMSR(Zen_PerformanceControl, MSR_AMD_F17H_PERF_CTL); \
})
#define _AMD_Zen_Counters_Set_(Core, PMU) \
#define _AMD_Zen_Counters_Set_(Core, PMC) \
({ \
AMD_Zen_##PMU##_Counters_Set(Core); \
AMD_Zen_##PMC##_Counters_Set(Core); \
})
#define AMD_Zen_Counters_Set(Core, PMU) \
_AMD_Zen_Counters_Set_(Core, PMU)
#define AMD_Zen_Counters_Set(Core, PMC) \
_AMD_Zen_Counters_Set_(Core, PMC)
#define Uncore_Counters_Set(PMU) \
({ \
@@ -10887,12 +10887,12 @@ void AMD_Core_Counters_Clear(CORE_RO *Core)
WRMSR(Core->SaveArea.Zen_PerformanceControl,MSR_AMD_F17H_PERF_CTL);\
})
#define _AMD_Zen_Counters_Clear_(Core, PMU) \
#define _AMD_Zen_Counters_Clear_(Core, PMC) \
({ \
AMD_Zen_##PMU##_Counters_Clear(Core); \
AMD_Zen_##PMC##_Counters_Clear(Core); \
})
#define AMD_Zen_Counters_Clear(Core, PMU) \
_AMD_Zen_Counters_Clear_(Core, PMU)
#define AMD_Zen_Counters_Clear(Core, PMC) \
_AMD_Zen_Counters_Clear_(Core, PMC)
#define Uncore_Counters_Clear(PMU) \
({ \
@@ -11323,12 +11323,12 @@ static void PKG_Counters_IvyBridge_EP(CORE_RO *Core, unsigned int T)
Pkg->Counter[T].CTR[complex] &= 0xffffffffffff ; \
})
#define _AMD_Zen_CCX_Counters_(Pkg, T, complex, PMU) \
#define _AMD_Zen_CCX_Counters_(Pkg, T, complex, PMC) \
({ \
AMD_Zen_CCX_##PMU##_Counters(Pkg, T, complex); \
AMD_Zen_CCX_##PMC##_Counters(Pkg, T, complex); \
})
#define AMD_Zen_CCX_Counters(Pkg, T, complex, PMU) \
_AMD_Zen_CCX_Counters_(Pkg, T, complex, PMU)
#define AMD_Zen_CCX_Counters(Pkg, T, complex, PMC) \
_AMD_Zen_CCX_Counters_(Pkg, T, complex, PMC)
#define Pkg_OVH(Pkg, Core) \
({ \
@@ -15413,12 +15413,13 @@ void Cycle_AMD_Family_17h(CORE_RO *Core,
}
/* Read the Cache L3 performance counter per Complex */
if ((Core->T.PackageID == 0) &&
!(Core->T.ApicID & PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
if ((Core->T.PackageID == 0)
&& !(Core->T.ApicID
& PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
{
const unsigned short CCX = Core->T.Cluster.CCX & 0b111;
AMD_Zen_CCX_Counters(PUBLIC(RO(Proc)), 1, CCX, AMD_ZEN_PMU);
AMD_Zen_CCX_Counters(PUBLIC(RO(Proc)), 1, CCX, AMD_ZEN_PMC);
Delta_L3(PUBLIC(RO(Proc)), CCX);
@@ -15606,10 +15607,11 @@ static void Start_AMD_Family_17h(void *arg)
AMD_Core_Counters_Set(Core, Family_17h);
if ((Core->T.ThreadID == 0) &&
!(Core->T.ApicID & PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
if ((Core->T.ThreadID == 0)
&& !(Core->T.ApicID
& PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
{
AMD_Zen_Counters_Set(Core, AMD_ZEN_PMU);
AMD_Zen_Counters_Set(Core, AMD_ZEN_PMC);
}
SMT_Counters_AMD_Family_17h(Core, 0);
@@ -15628,12 +15630,13 @@ static void Start_AMD_Family_17h(void *arg)
RDCOUNTER(Core->Counter[0].Power.ACCU,MSR_AMD_PP0_ENERGY_STATUS);
Core->Counter[0].Power.ACCU &= 0xffffffff;
}
if ((Core->T.PackageID == 0) &&
!(Core->T.ApicID & PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
if ((Core->T.PackageID == 0)
&& !(Core->T.ApicID
& PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
{
const unsigned short CCX = Core->T.Cluster.CCX & 0b111;
AMD_Zen_CCX_Counters(PUBLIC(RO(Proc)), 0, CCX, AMD_ZEN_PMU);
AMD_Zen_CCX_Counters(PUBLIC(RO(Proc)), 0, CCX, AMD_ZEN_PMC);
}
BITSET(LOCKLESS, PRIVATE(OF(Join, AT(cpu)))->TSM, MUSTFWD);
@@ -15656,10 +15659,11 @@ static void Stop_AMD_Family_17h(void *arg)
AMD_Core_Counters_Clear(Core);
if ((Core->T.ThreadID == 0) &&
!(Core->T.ApicID & PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
if ((Core->T.ThreadID == 0)
&& !(Core->T.ApicID
& PUBLIC(RO(Proc))->Features.leaf80000008.ECX.ApicIdCoreIdSize))
{
AMD_Zen_Counters_Clear(Core, AMD_ZEN_PMU);
AMD_Zen_Counters_Clear(Core, AMD_ZEN_PMC);
}
if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) {
if (Arch[PUBLIC(RO(Proc))->ArchID].Uncore.Stop != NULL) {