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81 Commits

Author SHA1 Message Date
CyrIng
17a08f536a Copyright (C) 2015-2025 CYRIL COURTIAT 2025-01-19 13:15:05 +01:00
CyrIng
ad6730c83d Version 2 ; Experience version 2024-12-24 07:53:04 +01:00
CyrIng
5aefb1b6c9 [Build] Change dkms configuration to install into /usr/bin/ 2024-07-24 02:48:28 +02:00
CyrIng
4705b32740 dkms and ckms configuration files upgraded to version 1.98 2024-05-27 16:57:43 +02:00
CyrIng
73774ee734 Copyright (C) 2015-2024 CYRIL COURTIAT 2023-12-31 22:55:39 +01:00
CyrIng
3512685664 [Build] Creating a new recipe to uninstall binaries 
* DKMS, CKMS are now using default extra modules directories
 2023-11-18 21:39:35 +01:00
CyrIng
9f71f4af76 [Intel][10 to 14th Gen] Allow toggling the L1 Scrubbing 2023-07-01 13:36:22 +02:00
CyrIng
36c32558d8 Version 1.96 2023-03-09 11:11:05 +00:00
CyrIng
12f78174a9 Version 1.95 
[AMD][CPUID] Secure Memory Encryption SME support.
 2023-01-10 18:43:06 +00:00
CyrIng
45fab8fc7b (C)2015-2023 CYRIL COURTIAT 2023-01-03 07:10:54 +00:00
CyrIng
870899ff42 CoreFreq version 1.93.1 2022-12-12 19:43:26 +00:00
CyrIng
75e57ebcae (C)2015-2022 CYRIL COURTIAT 2022-12-07 08:50:07 +00:00
CyrIng
5e805c1ab9 [Kernel/ACPI] Attempt to write CPPC registers: 
* Can Enable CPPC via existing HWP call flow.
* Target ratio is somehow functional.
* Min and Max ratios are unimplemented.
 2022-08-16 19:48:15 +00:00
CyrIng
56c99ae03f Version 1.91.2 2022-06-18 18:14:27 +00:00
CyrIng
3899217c5e [UI] Display the AMD/Zen/UMC relative frequencies: 
* when `ARCH_PMC=UMC` built
* in Frequency view, alternate footer area (from `%` shortcut)
* in Custom view, footer area
 2022-06-15 19:20:14 +00:00
CyrIng
44d678a65a [AMD/Zen] Programming L3 PMC for L3 Cache Miss Latency (cycles) 2022-03-09 23:55:24 +01:00
CyrIng
72ce5bc7df [IMC] New DRAM timings: tXS, tXP 2022-01-15 14:23:33 +01:00
CyrIng
7a3175d061 Copyright (C) 2015-2022 CYRIL INGENIERIE 2022-01-06 09:19:08 +01:00
CyrIng
0b005d8767 [AMD/EPYC] Refactoring for multiple UMC 2021-11-17 00:28:29 +01:00
CyrIng
bec0e0d274 Version 1.88 
[Daemon] Improving the source code.
 2021-10-05 01:12:14 +02:00
CyrIng
a36be2d24f [Intel][11th Gen] Initial implementation of the Rocket Lake IMC 2021-06-17 17:25:55 +02:00
CyrIng
388effac93 [Intel/Nehalem] Altering the TDC limit: 
* "Custom_TDC_Offset" "Activate_TDC_Limit" new parameters
* API changed for selection through UI
 2021-05-16 16:22:52 +02:00
CyrIng
187bf2c7c5 [AMD/Zen/UMC] BankGroupSwap 2021-04-23 09:57:57 +02:00
CyrIng
5c820bf0cf [Code review] 
* Improving interoperability with Rust.
* Adding the Relative and Absolute frequency limits.
 2021-01-24 15:26:49 +00:00
CyrIng
4a71047b7a CoreFreq (C) 2015-2021 CYRIL INGENIERIE 2021-01-01 17:01:49 +00:00
CyrIng
2c86371f49 [UI] Dropdown window with multi-columns support. 2020-12-31 06:09:59 +00:00
CyrIng
6ba6cdf1f0 [AMD/Zen2/Ryzen][UMC] Guessing the DIMM Single/Dual Ranks (issue #212) 
Rank is guessed from from Bit-9 of the Chip Mask register.
Total size is the sum of all Chips at the end of the loop.
No specs found for Columns and Rows, thus hard coded DDR4 common values.
Banks are computed from the equation:
(Banks x Ranks x Columns x Rows) x 8 = Size (Bytes)

[RAPL] Only compute the Power-Window unit if registers are provided
and the Settings-Power-Scope is set to non <None>.
 2020-11-12 09:40:29 +01:00
CyrIng
96cb71bfaf Version 1.81 : 
* Fixed the CPUID x2APIC aggregation
* Scroll the DDR timings in its Dashboard card
* Misc code size optimizations
* Introducing new UI compilation directives
 ( NO_HEADER , NO_UPPER , NO_LOWER , NO_FOOTER )
 2020-09-16 01:48:37 +00:00
CyrIng
9701f8a09d Misc CPUID bits of the AMD/Zen architecture. 2020-07-09 08:12:49 +00:00
CyrIng
99a8f6e468 [AMD][EPYC/Threadripper] try to read thermal sensor per node in SMT|Core scope 2020-06-21 14:11:46 +00:00
Adam Zegelin
136f28f1a4 Bump DKMS version to 1.78. 2020-06-15 14:03:30 -07:00
CyrIng
74a8869990 Refactoring the UI scaling. 2020-04-26 14:23:28 +02:00
CyrIng
72377fb795 CPUID additional bits. 
[Experimental][Intel] "Icelake/SP", "Sunny Cove", "Tigerlake",
"Atom/C3000", "Atom/Tremont", "Atom/Tremont/EHL"
 2020-04-06 17:25:16 +02:00
CyrIng
021e0249a0 [GUI] Handling the X-Window & Terminal events. 2020-03-20 09:53:47 +01:00
CyrIng
b2c04fdc6d Current developments. 2020-02-21 04:04:27 +01:00
CyrIng
e5b6d7f5b9 [IMC][Intel][Haswell][Broadwell] Mobile M/H , U/Y & Desktop processors. 2020-01-18 13:44:31 +01:00
CyrIng
0e03ea8446 Fixed the version in the DKMS package. 2020-01-10 06:09:21 +01:00
CyrIng
f4b523c074 Version 1.71 - Copyright (C) 2015-2020 CYRIL INGENIERIE 2020-01-01 06:21:37 +01:00
Alexey Ivanov
9f48cb3880 Use kernel dir passed by DKMS 2019-12-22 22:48:02 -08:00
CyrIng
6c24c3b8d7 [AMD][Zen] Conditional build with amd_smn_read() for Kernel version 4.20 and superiors (issue #145) 2019-12-05 19:45:16 +01:00
CyrIng
bf9a8ee859 Intel Mitigation Mechanisms: TSX Asynchronous Abort (TAA_NO) & Page Size Change MCE (PSCHANGE_MC_NO) capabilities. 2019-11-16 11:15:19 +01:00
CyrIng
0ac783c9c6 Version 1.68 2019-11-01 12:55:29 +01:00
CyrIng
b91cc8471d [RAPL] Energy and Power measurement per Core. 2019-10-12 20:00:09 +02:00
CyrIng
131560030f Signals handling. 2019-09-19 14:30:38 +02:00
CyrIng
9088d50546 Version 1.65 2019-09-03 23:03:14 +02:00
CyrIng
4e6d4c6c9d [ODCM & Policy] Haswell-DT in white-list (#143) // HWP MSR fixup (#109) 2019-08-29 20:54:13 +02:00
CyrIng
ca3b0a13c3 256 SMT-Cores Scaling. 2019-08-24 18:03:50 +02:00
CyrIng
edd57c1e93 Version 1.62 2019-08-15 12:03:33 +02:00
CyrIng
6cdc69cdfb Embed & check the CoreFreq version footprint into the shared memories. 2019-07-30 07:13:44 +02:00
CyrIng
8deb045098 [AMD] Introducing the Core Complex ID. 2019-07-28 12:06:41 +02:00