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Version 1.71 - Copyright (C) 2015-2020 CYRIL INGENIERIE

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CyrIng
2020-01-01 06:21:37 +01:00
parent 4e6300e6cf
commit f4b523c074
29 changed files with 85 additions and 41 deletions
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2
CoreFreq.svg
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@@ -266,7 +266,7 @@
id="tspan3603"
x="118.95782"
y="1111.7253"
style="font-size:12.5px">CoreFreq 2015-2019</tspan><tspan
style="font-size:12.5px">CoreFreq 2015-2020</tspan><tspan
sodipodi:role="line"
id="tspan3605"
x="118.95782"
Side by Side Swipe Overlay

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Width:  |  Height:  |  Size: 73 KiB

After

Width:  |  Height:  |  Size: 73 KiB

10
Makefile
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@@ -1,5 +1,5 @@
# CoreFreq
# Copyright (C) 2015-2019 CYRIL INGENIERIE
# Copyright (C) 2015-2020 CYRIL INGENIERIE
# Licenses: GPL2
CC ?= cc
@@ -24,6 +24,10 @@ endif
ccflags-y += -D MSR_CORE_PERF_UCC=$(MSR_CORE_PERF_UCC)
ccflags-y += -D MSR_CORE_PERF_URC=$(MSR_CORE_PERF_URC)
ifneq ($(HWM_CHIPSET),)
ccflags-y += -D HWM_CHIPSET=$(HWM_CHIPSET)
endif
.PHONY: all
all: corefreqd corefreq-cli
$(MAKE) -j1 -C $(KERNELDIR) M=$(PWD) modules
@@ -122,6 +126,9 @@ help:
"| UBENCH=<N> |\n"\
"| where <N> is 0 to disable or 1 to enable micro-benchmark |\n"\
"| |\n"\
"| HWM_CHIPSET=<chipset> |\n"\
"| where <chipset> is W83627 |\n"\
"| |\n"\
"| FEAT_DBG=<N> |\n"\
"| where <N> is 0 or 1 for FEATURE DEBUG level |\n"\
"| |\n"\
@@ -141,6 +148,7 @@ help:
"| make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 \\ |\n"\
"| MSR_CORE_PERF_UCC=MSR_CORE_PERF_FIXED_CTR1 \\ |\n"\
"| MSR_CORE_PERF_URC=MSR_CORE_PERF_FIXED_CTR2 \\ |\n"\
"| HWM_CHIPSET=W83627 \\ |\n"\
"| clean all |\n"\
"o---------------------------------------------------------------o"

4
README.md
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@@ -129,7 +129,7 @@ CoreFreq: Processor [06_1A] Architecture [Nehalem/Bloomfield] CPU [8/8]
### Daemon
```
CoreFreq Daemon. Copyright (C) 2015-2019 CYRIL INGENIERIE
CoreFreq Daemon. Copyright (C) 2015-2020 CYRIL INGENIERIE
Processor [Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz]
Architecture [Nehalem/Bloomfield] 8/8 CPU Online.
@@ -311,5 +311,5 @@ parm: Mech_L1D_FLUSH:Mitigation Mechanism Cache L1D Flush (short)
# About
[CyrIng](https://github.com/cyring)
Copyright (C) 2015-2019 CYRIL INGENIERIE
Copyright (C) 2015-2020 CYRIL INGENIERIE
-------

2
amdmsr.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
bitasm.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq-api.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq-cli-extra.c
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@@ -1,5 +1,5 @@
/*
* CoreFreq (C) 2015-2019 CYRIL INGENIERIE
* CoreFreq (C) 2015-2020 CYRIL INGENIERIE
* Contributors: Andrew Gurinovich ; CyrIng
* Licenses: GPL2
*

2
corefreq-cli-extra.h
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@@ -1,5 +1,5 @@
/*
* CoreFreq (C) 2015-2019 CYRIL INGENIERIE
* CoreFreq (C) 2015-2020 CYRIL INGENIERIE
* Contributors: Andrew Gurinovich ; CyrIng
* Licenses: GPL2
*

2
corefreq-cli-json.c
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@@ -1,5 +1,5 @@
/*
* CoreFreq (C) 2015-2019 CYRIL INGENIERIE
* CoreFreq (C) 2015-2020 CYRIL INGENIERIE
* Contributors: Andrew Gurinovich ; CyrIng
* Licenses: GPL2
*/

2
corefreq-cli-json.h
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@@ -1,5 +1,5 @@
/*
* CoreFreq (C) 2015-2019 CYRIL INGENIERIE
* CoreFreq (C) 2015-2020 CYRIL INGENIERIE
* Contributors: Andrew Gurinovich ; CyrIng
* Licenses: GPL2
*/

4
corefreq-cli-rsc-en.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -598,7 +598,7 @@
#define RSC_ERROR_CMD_SYNTAX_CODE_EN \
"CoreFreq." \
" Copyright (C) 2015-2019 CYRIL INGENIERIE\n\n"\
" Copyright (C) 2015-2020 CYRIL INGENIERIE\n\n"\
"Usage:\t%s [-option <arguments>]\n" \
"\t-0,1,2\tMemory unit in K,M,G Byte\n" \
"\t-F\tTemperature in Fahrenheit\n" \

4
corefreq-cli-rsc-fr.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -598,7 +598,7 @@
#define RSC_ERROR_CMD_SYNTAX_CODE_FR \
"CoreFreq." \
" Copyright (C) 2015-2019 CYRIL INGENIERIE\n\n" \
" Copyright (C) 2015-2020 CYRIL INGENIERIE\n\n" \
"Usage:\t%s [-option <arguments>]\n" \
"\t-0,1,2\tUnité mémoire en K,M,G octet\n" \
"\t-F\tTemperature en Fahrenheit\n" \

2
corefreq-cli-rsc.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

4
corefreq-cli-rsc.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -2110,5 +2110,5 @@ extern RESOURCE_ST Resource[];
#define RSC_LOGO_R5 " /_/ "
#define RSC_COPY_R0 " by CyrIng "
#define RSC_COPY_R1 " "
#define RSC_COPY_R2 " (C)2015-2019 CYRIL INGENIERIE "
#define RSC_COPY_R2 " (C)2015-2020 CYRIL INGENIERIE "

2
corefreq-cli.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq-cli.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq-ui.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq-ui.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreq.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

4
corefreqd.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -4634,7 +4634,7 @@ REASON_CODE Shm_Manager(FD *fd, PROC *Proc, uid_t uid, uid_t gid, mode_t cmask)
/* Welcomes with brand and per CPU base clock. */
if (Quiet & 0x001)
printf("CoreFreq Daemon %s" \
" Copyright (C) 2015-2019 CYRIL INGENIERIE\n",
" Copyright (C) 2015-2020 CYRIL INGENIERIE\n",
COREFREQ_VERSION);
if (Quiet & 0x010)
printf("\n" \

2
corefreqd.service
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@@ -1,5 +1,5 @@
# CoreFreq
# Copyright (C) 2015-2019 CYRIL INGENIERIE
# Copyright (C) 2015-2020 CYRIL INGENIERIE
# Licenses: GPL2
[Unit]

10
corefreqk.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -6883,10 +6883,10 @@ static enum hrtimer_restart Cycle_Nehalem(struct hrtimer *pTimer)
if (Core->Bind == Proc->Service.Core) {
PKG_Counters_Nehalem(Core, 1);
#if FEAT_DBG > 1
FEAT_MSG("Including:Winbond(CPUVCORE)")
outb_p(0x20, 0x295);
Core->PowerThermal.VID = inb_p(0x295 + 1);
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
outb_p(HWM_W83627_CPUVCORE, HWM_W83627_INDEX_PORT);
Core->PowerThermal.VID = inb_p(HWM_W83627_DATA_PORT);
#endif
Delta_PC03(Proc);

30
corefreqk.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
@@ -3853,7 +3853,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {
@@ -3877,7 +3881,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
@@ -3901,7 +3909,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
@@ -3925,7 +3937,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {
@@ -3950,7 +3966,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_DMI_ids,
.Uncore = {
@@ -3974,7 +3994,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = Intel_Turbo_Config8C,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Westmere_EP_ids,
.Uncore = {
@@ -3998,7 +4022,11 @@ static ARCH Arch[ARCHITECTURES] = {
.ClockMod = ClockMod_Nehalem_PPC,
.TurboClock = NULL,
.thermalFormula = THERMAL_FORMULA_INTEL,
#if defined(HWM_CHIPSET) && (HWM_CHIPSET == W83627)
.voltageFormula = VOLTAGE_FORMULA_WINBOND_IO,
#else
.voltageFormula = VOLTAGE_FORMULA_NONE,
#endif
.powerFormula = POWER_FORMULA_NONE,
.PCI_ids = PCI_Nehalem_QPI_ids,
.Uncore = {

2
corefreqm.c
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
corefreqm.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

14
coretypes.h
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@@ -1,12 +1,12 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/
#define COREFREQ_MAJOR 1
#define COREFREQ_MINOR 70
#define COREFREQ_REV 7
#define COREFREQ_MINOR 71
#define COREFREQ_REV 0
#define FEAT_MESSAGE(_msg) _Pragma(#_msg)
#define FEAT_MSG(_msg) FEAT_MESSAGE(message(#_msg))
@@ -1518,6 +1518,14 @@ typedef struct /* BSP CPUID features. */
#define PCI_DEVICE_ID_AMD_17H_ARDEN_DF_F3 0x160b /* Arden */
#endif
/* Hardware Monitoring: Super I/O chipsets */
#define W83627 0x5ca3
/* Source: Winbond W83627 datasheet */
#define HWM_W83627_INDEX_PORT 0x295
#define HWM_W83627_DATA_PORT 0x296
#define HWM_W83627_CPUVCORE 0x20
typedef struct
{
struct {

4
dkms.conf
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@@ -1,11 +1,11 @@
# CoreFreq
# Copyright (C) 2015-2019 CYRIL INGENIERIE
# Copyright (C) 2015-2020 CYRIL INGENIERIE
# Licenses: GPL2
#
AUTOINSTALL="yes"
REMAKE_INITRD="no"
DRV_PATH=/kernel/drivers/misc
DRV_VERSION=1.70
DRV_VERSION=1.71
PACKAGE_NAME="corefreqk"
PACKAGE_VERSION="$DRV_VERSION"
BUILT_MODULE_NAME[0]="corefreqk"

2
intelmsr.h
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@@ -1,6 +1,6 @@
/*
* CoreFreq
* Copyright (C) 2015-2019 CYRIL INGENIERIE
* Copyright (C) 2015-2020 CYRIL INGENIERIE
* Licenses: GPL2
*/

2
scripter.sh
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@@ -1,7 +1,7 @@
#!/bin/sh
#
# CoreFreq
# Copyright (C) 2015-2019 CYRIL INGENIERIE
# Copyright (C) 2015-2020 CYRIL INGENIERIE
# Licenses: GPL2
#
if (( $# > 2 )); then