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535.261.03

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This commit is contained in:
Bernhard Stoeckner
2025-07-17 17:13:07 +02:00
parent f468568958
commit 9c67f19366
37 changed files with 425 additions and 177 deletions
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8
README.md
View File

@@ -1,7 +1,7 @@
# NVIDIA Linux Open GPU Kernel Module Source
This is the source release of the NVIDIA Linux open GPU kernel modules,
version 535.247.01.
version 535.261.03.
## How to Build
@@ -17,7 +17,7 @@ as root:
Note that the kernel modules built here must be used with GSP
firmware and user-space NVIDIA GPU driver components from a corresponding
535.247.01 driver release. This can be achieved by installing
535.261.03 driver release. This can be achieved by installing
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
option. E.g.,
@@ -180,7 +180,7 @@ software applications.
## Compatible GPUs
The open-gpu-kernel-modules can be used on any Turing or later GPU
(see the table below). However, in the 535.247.01 release,
(see the table below). However, in the 535.261.03 release,
GeForce and Workstation support is still considered alpha-quality.
To enable use of the open kernel modules on GeForce and Workstation GPUs,
@@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
parameter to 1. For more details, see the NVIDIA GPU driver end user
README here:
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.247.01/README/kernel_open.html
https://us.download.nvidia.com/XFree86/Linux-x86_64/535.261.03/README/kernel_open.html
In the below table, if three IDs are listed, the first is the PCI Device
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI

57
kernel-open/Kbuild
View File

@@ -75,70 +75,63 @@ $(foreach _module, $(NV_KERNEL_MODULES), \
$(eval include $(src)/$(_module)/$(_module).Kbuild))
#
# Define CFLAGS that apply to all the NVIDIA kernel modules. EXTRA_CFLAGS
# is deprecated since 2.6.24 in favor of ccflags-y, but we need to support
# older kernels which do not have ccflags-y. Newer kernels append
# $(EXTRA_CFLAGS) to ccflags-y for compatibility.
#
EXTRA_CFLAGS += -I$(src)/common/inc
EXTRA_CFLAGS += -I$(src)
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.247.01\"
ccflags-y += -I$(src)/common/inc
ccflags-y += -I$(src)
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
ccflags-y += -DNV_VERSION_STRING=\"535.261.03\"
ifneq ($(SYSSRCHOST1X),)
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
ccflags-y += -I$(SYSSRCHOST1X)
endif
EXTRA_CFLAGS += -Wno-unused-function
ccflags-y += -Wno-unused-function
ifneq ($(NV_BUILD_TYPE),debug)
EXTRA_CFLAGS += -Wuninitialized
ccflags-y += -Wuninitialized
endif
EXTRA_CFLAGS += -fno-strict-aliasing
ccflags-y += -fno-strict-aliasing
ifeq ($(ARCH),arm64)
EXTRA_CFLAGS += -mstrict-align
ccflags-y += -mstrict-align
endif
ifeq ($(NV_BUILD_TYPE),debug)
EXTRA_CFLAGS += -g
EXTRA_CFLAGS += $(call cc-option,-gsplit-dwarf,)
ccflags-y += -g
ccflags-y += $(call cc-option,-gsplit-dwarf,)
endif
EXTRA_CFLAGS += -ffreestanding
ccflags-y += -ffreestanding
ifeq ($(ARCH),arm64)
EXTRA_CFLAGS += -mgeneral-regs-only -march=armv8-a
EXTRA_CFLAGS += $(call cc-option,-mno-outline-atomics,)
ccflags-y += -mgeneral-regs-only -march=armv8-a
ccflags-y += $(call cc-option,-mno-outline-atomics,)
endif
ifeq ($(ARCH),x86_64)
EXTRA_CFLAGS += -mno-red-zone -mcmodel=kernel
ccflags-y += -mno-red-zone -mcmodel=kernel
endif
ifeq ($(ARCH),powerpc)
EXTRA_CFLAGS += -mlittle-endian -mno-strict-align -mno-altivec
ccflags-y += -mlittle-endian -mno-strict-align -mno-altivec
endif
EXTRA_CFLAGS += -DNV_UVM_ENABLE
EXTRA_CFLAGS += $(call cc-option,-Werror=undef,)
EXTRA_CFLAGS += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
EXTRA_CFLAGS += -DNV_KERNEL_INTERFACE_LAYER
ccflags-y += -DNV_UVM_ENABLE
ccflags-y += $(call cc-option,-Werror=undef,)
ccflags-y += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
ccflags-y += -DNV_KERNEL_INTERFACE_LAYER
#
# Detect SGI UV systems and apply system-specific optimizations.
#
ifneq ($(wildcard /proc/sgi_uv),)
EXTRA_CFLAGS += -DNV_CONFIG_X86_UV
ccflags-y += -DNV_CONFIG_X86_UV
endif
ifdef VGX_FORCE_VFIO_PCI_CORE
EXTRA_CFLAGS += -DNV_VGPU_FORCE_VFIO_PCI_CORE
ccflags-y += -DNV_VGPU_FORCE_VFIO_PCI_CORE
endif
#
@@ -165,9 +158,11 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \
NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags)
NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie
NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(ccflags-y) -fno-pie
NV_CONFTEST_CFLAGS += $(filter -std=%,$(KBUILD_CFLAGS))
NV_CONFTEST_CFLAGS += $(call cc-disable-warning,pointer-sign)
NV_CONFTEST_CFLAGS += $(call cc-option,-fshort-wchar,)
NV_CONFTEST_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types,)
NV_CONFTEST_COMPILE_TEST_HEADERS := $(obj)/conftest/macros.h
NV_CONFTEST_COMPILE_TEST_HEADERS += $(obj)/conftest/functions.h

21
kernel-open/common/inc/nv-mm.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -292,9 +292,21 @@ static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
#endif
}
#define NV_CAN_CALL_VMA_START_WRITE 1
#if !NV_CAN_CALL_VMA_START_WRITE
/*
* Commit 45ad9f5290dc updated vma_start_write() to call __vma_start_write().
*/
void nv_vma_start_write(struct vm_area_struct *);
#endif
static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
{
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
#if !NV_CAN_CALL_VMA_START_WRITE
nv_vma_start_write(vma);
ACCESS_PRIVATE(vma, __vm_flags) |= flags;
#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
vm_flags_set(vma, flags);
#else
vma->vm_flags |= flags;
@@ -303,7 +315,10 @@ static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
static inline void nv_vm_flags_clear(struct vm_area_struct *vma, vm_flags_t flags)
{
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
#if !NV_CAN_CALL_VMA_START_WRITE
nv_vma_start_write(vma);
ACCESS_PRIVATE(vma, __vm_flags) &= ~flags;
#elif defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
vm_flags_clear(vma, flags);
#else
vma->vm_flags &= ~flags;

11
kernel-open/common/inc/nv-timer.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -63,4 +63,13 @@ static inline void nv_timer_setup(struct nv_timer *nv_timer,
#endif
}
static inline void nv_timer_delete_sync(struct timer_list *timer)
{
#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
timer_delete_sync(timer);
#else
del_timer_sync(timer);
#endif
}
#endif // __NV_TIMER_H__

70
kernel-open/conftest.sh
View File

@@ -4013,33 +4013,6 @@ compile_test() {
fi
;;
dma_buf_has_dynamic_attachment)
#
# Determine if the function dma_buf_attachment_is_dynamic()
# is present.
#
# Added by commit: 15fd552d186c
# ("dma-buf: change DMA-buf locking convention v3") in v5.5 (2018-07-03)
#
echo "$CONFTEST_PREAMBLE
#include <linux/dma-buf.h>
bool conftest_dma_buf_attachment_is_dynamic(void) {
return dma_buf_attachment_is_dynamic(NULL);
}" > conftest$$.c
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
rm -f conftest$$.c
if [ -f conftest$$.o ]; then
echo "#define NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT" | append_conftest "functions"
rm -f conftest$$.o
return
else
echo "#undef NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT" | append_conftest "functions"
return
fi
;;
dma_buf_attachment_has_peer2peer)
#
# Determine if peer2peer is present in struct dma_buf_attachment.
@@ -6687,6 +6660,22 @@ compile_test() {
compile_check_conftest "$CODE" "NV_DRM_UNLOCKED_IOCTL_FLAG_PRESENT" "" "types"
;;
page_pgmap)
#
# Determine if the page_pgmap() function is present.
#
# Added by commit 82ba975e4c43 ("mm: allow compound zone device
# pages") in v6.14
#
CODE="
#include <linux/mmzone.h>
int conftest_page_pgmap(void) {
return page_pgmap();
}"
compile_check_conftest "$CODE" "NV_PAGE_PGMAP_PRESENT" "" "functions"
;;
folio_test_swapcache)
#
# Determine if the folio_test_swapcache() function is present.
@@ -6744,6 +6733,33 @@ compile_test() {
compile_check_conftest "$CODE" "NV_DRM_DRIVER_HAS_DATE" "" "types"
;;
drm_connector_helper_funcs_mode_valid_has_const_mode_arg)
#
# Determine if the 'mode' pointer argument is const in
# drm_connector_helper_funcs::mode_valid.
#
# The 'mode' pointer argument in
# drm_connector_helper_funcs::mode_valid was made const by commit
# 26d6fd81916e ("drm/connector: make mode_valid take a const struct
# drm_display_mode") in linux-next, expected in v6.15.
#
CODE="
#if defined(NV_DRM_DRM_ATOMIC_HELPER_H_PRESENT)
#include <drm/drm_atomic_helper.h>
#endif
static int conftest_drm_connector_mode_valid(struct drm_connector *connector,
const struct drm_display_mode *mode) {
return 0;
}
const struct drm_connector_helper_funcs conftest_drm_connector_helper_funcs = {
.mode_valid = conftest_drm_connector_mode_valid,
};"
compile_check_conftest "$CODE" "NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG" "" "types"
;;
# When adding a new conftest entry, please use the correct format for
# specifying the relevant upstream Linux kernel commit.
#

4
kernel-open/nvidia-drm/nvidia-drm-connector.c
View File

@@ -314,7 +314,11 @@ static int nv_drm_connector_get_modes(struct drm_connector *connector)
}
static int nv_drm_connector_mode_valid(struct drm_connector *connector,
#if defined(NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG)
const struct drm_display_mode *mode)
#else
struct drm_display_mode *mode)
#endif
{
struct drm_device *dev = connector->dev;
struct nv_drm_device *nv_dev = to_nv_device(dev);

2
kernel-open/nvidia-drm/nvidia-drm.Kbuild
View File

@@ -56,6 +56,7 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl_refcount_dec_and_test
NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_alpha_blending_available
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_fd_to_handle
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_present_drm_gem_prime_handle_to_fd
NV_CONFTEST_GENERIC_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_dev_unref
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_reinit_primary_mode_group
@@ -137,3 +138,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_output_poll_changed
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_driver_has_date
NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations_fop_unsigned_offset_present
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_connector_helper_funcs_mode_valid_has_const_mode_arg

10
kernel-open/nvidia-modeset/nvidia-modeset-linux.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-21 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -652,7 +652,11 @@ static void nvkms_kthread_q_callback(void *arg)
* pending timers and than waiting for workqueue callbacks.
*/
if (timer->kernel_timer_created) {
#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
timer_delete_sync(&timer->kernel_timer);
#else
del_timer_sync(&timer->kernel_timer);
#endif
}
/*
@@ -1743,7 +1747,11 @@ restart:
* completion, and we wait for queue completion with
* nv_kthread_q_stop below.
*/
#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
if (timer_delete_sync(&timer->kernel_timer) == 1) {
#else
if (del_timer_sync(&timer->kernel_timer) == 1) {
#endif
/* We've deactivated timer so we need to clean after it */
list_del(&timer->timers_list);

1
kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
View File

@@ -91,3 +91,4 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_real_ts64
NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64
NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native
NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_register_backlight
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync

3
kernel-open/nvidia-uvm/nvidia-uvm.Kbuild
View File

@@ -87,6 +87,7 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += mmgrab
NV_CONFTEST_FUNCTION_COMPILE_TESTS += iommu_sva_bind_device_has_drvdata_arg
NV_CONFTEST_FUNCTION_COMPILE_TESTS += vm_fault_to_errno
NV_CONFTEST_FUNCTION_COMPILE_TESTS += folio_test_swapcache
NV_CONFTEST_FUNCTION_COMPILE_TESTS += page_pgmap
NV_CONFTEST_TYPE_COMPILE_TESTS += backing_dev_info
NV_CONFTEST_TYPE_COMPILE_TESTS += mm_context_t
@@ -116,3 +117,5 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += mmu_interval_notifier
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_int_active_memcg
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_migrate_vma_setup
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present___iowrite64_lo_hi
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_make_device_exclusive

9
kernel-open/nvidia-uvm/uvm_ats_sva.c
View File

@@ -139,7 +139,11 @@ NvU32 smmu_vcmdq_read32(void __iomem *smmu_cmdqv_base, int reg)
static void smmu_vcmdq_write64(void __iomem *smmu_cmdqv_base, int reg, NvU64 val)
{
#if NV_IS_EXPORT_SYMBOL_PRESENT___iowrite64_lo_hi
__iowrite64_lo_hi(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg);
#else
iowrite64(val, SMMU_VCMDQ_BASE_ADDR(smmu_cmdqv_base, VCMDQ) + reg);
#endif
}
// Fix for Bug 4130089: [GH180][r535] WAR for kernel not issuing SMMU
@@ -304,12 +308,13 @@ void uvm_ats_smmu_invalidate_tlbs(uvm_gpu_va_space_t *gpu_va_space, NvU64 addr,
NV_STATUS uvm_ats_sva_add_gpu(uvm_parent_gpu_t *parent_gpu)
{
#if NV_IS_EXPORT_SYMBOL_GPL_iommu_dev_enable_feature
int ret;
ret = iommu_dev_enable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA);
if (ret)
return errno_to_nv_status(ret);
#endif
if (UVM_ATS_SMMU_WAR_REQUIRED())
return uvm_ats_smmu_war_init(parent_gpu);
else
@@ -321,7 +326,9 @@ void uvm_ats_sva_remove_gpu(uvm_parent_gpu_t *parent_gpu)
if (UVM_ATS_SMMU_WAR_REQUIRED())
uvm_ats_smmu_war_deinit(parent_gpu);
#if NV_IS_EXPORT_SYMBOL_GPL_iommu_dev_disable_feature
iommu_dev_disable_feature(&parent_gpu->pci_dev->dev, IOMMU_DEV_FEAT_SVA);
#endif
}
NV_STATUS uvm_ats_sva_bind_gpu(uvm_gpu_va_space_t *gpu_va_space)

40
kernel-open/nvidia-uvm/uvm_hmm.c
View File

@@ -1864,7 +1864,7 @@ static void fill_dst_pfn(uvm_va_block_t *va_block,
dpage = pfn_to_page(pfn);
UVM_ASSERT(is_device_private_page(dpage));
UVM_ASSERT(dpage->pgmap->owner == &g_uvm_global);
UVM_ASSERT(page_pgmap(dpage)->owner == &g_uvm_global);
hmm_mark_gpu_chunk_referenced(va_block, gpu, gpu_chunk);
UVM_ASSERT(!page_count(dpage));
@@ -2281,6 +2281,39 @@ static void hmm_release_atomic_pages(uvm_va_block_t *va_block,
}
}
static int hmm_make_device_exclusive_range(struct mm_struct *mm,
unsigned long start,
unsigned long end,
struct page **pages)
{
#if NV_IS_EXPORT_SYMBOL_PRESENT_make_device_exclusive
unsigned long addr;
int npages = 0;
for (addr = start; addr < end; addr += PAGE_SIZE) {
struct folio *folio;
struct page *page;
page = make_device_exclusive(mm, addr, &g_uvm_global, &folio);
if (IS_ERR(page)) {
while (npages) {
page = pages[--npages];
unlock_page(page);
put_page(page);
}
npages = PTR_ERR(page);
break;
}
pages[npages++] = page;
}
return npages;
#else
return make_device_exclusive_range(mm, start, end, pages, &g_uvm_global);
#endif
}
static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id,
uvm_va_block_t *va_block,
uvm_va_block_retry_t *va_block_retry,
@@ -2336,11 +2369,10 @@ static NV_STATUS hmm_block_atomic_fault_locked(uvm_processor_id_t processor_id,
uvm_mutex_unlock(&va_block->lock);
npages = make_device_exclusive_range(service_context->block_context.mm,
npages = hmm_make_device_exclusive_range(service_context->block_context.mm,
uvm_va_block_cpu_page_address(va_block, region.first),
uvm_va_block_cpu_page_address(va_block, region.outer - 1) + PAGE_SIZE,
pages + region.first,
&g_uvm_global);
pages + region.first);
uvm_mutex_lock(&va_block->lock);

5
kernel-open/nvidia-uvm/uvm_linux.h
View File

@@ -590,4 +590,9 @@ static inline pgprot_t uvm_pgprot_decrypted(pgprot_t prot)
#include <asm/page.h>
#define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x)))
#endif
#ifndef NV_PAGE_PGMAP_PRESENT
#define page_pgmap(page) (page)->pgmap
#endif
#endif // _UVM_LINUX_H

2
kernel-open/nvidia-uvm/uvm_pmm_gpu.c
View File

@@ -3314,7 +3314,7 @@ NvU32 uvm_pmm_gpu_phys_to_virt(uvm_pmm_gpu_t *pmm, NvU64 phys_addr, NvU64 region
static uvm_pmm_gpu_t *devmem_page_to_pmm(struct page *page)
{
return container_of(page->pgmap, uvm_pmm_gpu_t, devmem.pagemap);
return container_of(page_pgmap(page), uvm_pmm_gpu_t, devmem.pagemap);
}
static uvm_gpu_chunk_t *devmem_page_to_chunk_locked(struct page *page)

29
kernel-open/nvidia/nv-caps.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -562,6 +562,9 @@ err:
void NV_API_CALL nv_cap_close_fd(int fd)
{
struct file *file;
NvBool is_nv_cap_fd;
if (fd == -1)
{
return;
@@ -580,6 +583,30 @@ void NV_API_CALL nv_cap_close_fd(int fd)
return;
}
file = fget(fd);
if (file == NULL)
{
task_unlock(current);
return;
}
/* Make sure the fd belongs to the nv-cap-drv */
is_nv_cap_fd = (file->f_op == &g_nv_cap_drv_fops);
fput(file);
/*
* In some cases, we may be in shutdown path and execute
* in context of unrelated process. In that case we should
* not access any 'current' state, but instead let kernel
* clean up capability files on its own.
*/
if (!is_nv_cap_fd)
{
task_unlock(current);
return;
}
/*
* From v4.17-rc1 (to v5.10.8) kernels have stopped exporting sys_close(fd)
* and started exporting __close_fd, as of this commit:

5
kernel-open/nvidia/nv-dmabuf.c
View File

@@ -780,10 +780,9 @@ nv_dma_buf_map(
// On non-coherent platforms, importers must be able to handle peer
// MMIO resources not backed by struct page.
//
#if defined(NV_DMA_BUF_HAS_DYNAMIC_ATTACHMENT) && \
defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER)
#if defined(NV_DMA_BUF_ATTACHMENT_HAS_PEER2PEER)
if (!priv->nv->coherent &&
dma_buf_attachment_is_dynamic(attachment) &&
(attachment->importer_ops != NULL) &&
!attachment->peer2peer)
{
nv_printf(NV_DBG_ERRORS,

74
kernel-open/nvidia/nv-mmap.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -804,3 +804,75 @@ void NV_API_CALL nv_set_safe_to_mmap_locked(
nvl->safe_to_mmap = safe_to_mmap;
}
#if !NV_CAN_CALL_VMA_START_WRITE
static NvBool nv_vma_enter_locked(struct vm_area_struct *vma, NvBool detaching)
{
NvU32 tgt_refcnt = VMA_LOCK_OFFSET;
NvBool interrupted = NV_FALSE;
if (!detaching)
{
tgt_refcnt++;
}
if (!refcount_add_not_zero(VMA_LOCK_OFFSET, &vma->vm_refcnt))
{
return NV_FALSE;
}
rwsem_acquire(&vma->vmlock_dep_map, 0, 0, _RET_IP_);
prepare_to_rcuwait(&vma->vm_mm->vma_writer_wait);
for (;;)
{
set_current_state(TASK_UNINTERRUPTIBLE);
if (refcount_read(&vma->vm_refcnt) == tgt_refcnt)
break;
if (signal_pending_state(TASK_UNINTERRUPTIBLE, current))
{
interrupted = NV_TRUE;
break;
}
schedule();
}
// This is an open-coded version of finish_rcuwait().
rcu_assign_pointer(vma->vm_mm->vma_writer_wait.task, NULL);
__set_current_state(TASK_RUNNING);
if (interrupted)
{
// Clean up on error: release refcount and dep_map
refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
return NV_FALSE;
}
lock_acquired(&vma->vmlock_dep_map, _RET_IP_);
return NV_TRUE;
}
/*
* Helper function to handle VMA locking and refcount management.
*/
void nv_vma_start_write(struct vm_area_struct *vma)
{
NvU32 mm_lock_seq;
NvBool locked;
if (__is_vma_write_locked(vma, &mm_lock_seq))
return;
locked = nv_vma_enter_locked(vma, NV_FALSE);
WRITE_ONCE(vma->vm_lock_seq, mm_lock_seq);
if (locked)
{
NvBool detached;
detached = refcount_sub_and_test(VMA_LOCK_OFFSET, &vma->vm_refcnt);
rwsem_release(&vma->vmlock_dep_map, _RET_IP_);
WARN_ON_ONCE(detached);
}
}
EXPORT_SYMBOL(nv_vma_start_write);
#endif // !NV_CAN_CALL_VMA_START_WRITE

9
kernel-open/nvidia/nv-nano-timer.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -154,8 +154,13 @@ void NV_API_CALL nv_create_nano_timer(
nv_nstimer->nv_nano_timer_callback = nvidia_nano_timer_callback;
#if NV_NANO_TIMER_USE_HRTIMER
#if NV_IS_EXPORT_SYMBOL_PRESENT_hrtimer_setup
hrtimer_setup(&nv_nstimer->hr_timer, &nv_nano_timer_callback_typed_data,
CLOCK_MONOTONIC, HRTIMER_MODE_REL);
#else
hrtimer_init(&nv_nstimer->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
nv_nstimer->hr_timer.function = nv_nano_timer_callback_typed_data;
#endif // NV_IS_EXPORT_SYMBOL_PRESENT_hrtimer_setup
#else
#if defined(NV_TIMER_SETUP_PRESENT)
timer_setup(&nv_nstimer->jiffy_timer, nv_jiffy_timer_callback_typed_data, 0);
@@ -213,7 +218,7 @@ void NV_API_CALL nv_cancel_nano_timer(
#if NV_NANO_TIMER_USE_HRTIMER
hrtimer_cancel(&nv_nstimer->hr_timer);
#else
del_timer_sync(&nv_nstimer->jiffy_timer);
nv_timer_delete_sync(&nv_nstimer->jiffy_timer);
#endif
}

4
kernel-open/nvidia/nv.c
View File

@@ -3753,7 +3753,7 @@ int NV_API_CALL nv_stop_rc_timer(
nv_printf(NV_DBG_INFO, "NVRM: stopping rc timer\n");
nv->rc_timer_enabled = 0;
del_timer_sync(&nvl->rc_timer.kernel_timer);
nv_timer_delete_sync(&nvl->rc_timer.kernel_timer);
nv_printf(NV_DBG_INFO, "NVRM: rc timer stopped\n");
return 0;
@@ -3797,7 +3797,7 @@ void NV_API_CALL nv_stop_snapshot_timer(void)
NV_SPIN_UNLOCK_IRQRESTORE(&nvl->snapshot_timer_lock, flags);
if (timer_active)
del_timer_sync(&nvl->snapshot_timer.kernel_timer);
nv_timer_delete_sync(&nvl->snapshot_timer.kernel_timer);
}
void NV_API_CALL nv_flush_snapshot_timer(void)

6
kernel-open/nvidia/nvidia.Kbuild
View File

@@ -186,7 +186,6 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_kmap
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_kmap_atomic
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_ops_has_map_atomic
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_has_dynamic_attachment
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_buf_attachment_has_peer2peer
NV_CONFTEST_FUNCTION_COMPILE_TESTS += dma_set_mask_and_coherent
NV_CONFTEST_FUNCTION_COMPILE_TESTS += devm_clk_bulk_get_all
@@ -231,6 +230,11 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pte
NV_CONFTEST_SYMBOL_COMPILE_TESTS += follow_pte_arg_vma
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_follow_pfnmap_start
NV_CONFTEST_SYMBOL_COMPILE_TESTS += ecc_digits_from_bytes
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_hrtimer_setup
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl___vma_start_write
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_iommu_dev_enable_feature
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_iommu_dev_disable_feature
NV_CONFTEST_TYPE_COMPILE_TESTS += dma_ops
NV_CONFTEST_TYPE_COMPILE_TESTS += swiotlb_dma_ops

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r539_28
#define NV_BUILD_BRANCH r539_41
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r539_28
#define NV_PUBLIC_BRANCH r539_41
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r539_28-859"
#define NV_BUILD_CHANGELIST_NUM (35750789)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r539_41-927"
#define NV_BUILD_CHANGELIST_NUM (36124219)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r539_28-859"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35750789)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r539_41-927"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36124219)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r539_28-1"
#define NV_BUILD_CHANGELIST_NUM (35750715)
#define NV_BUILD_BRANCH_VERSION "r539_41-1"
#define NV_BUILD_CHANGELIST_NUM (36117060)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "539.29"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35750715)
#define NV_BUILD_NAME "539.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36117060)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.247.01"
#define NV_VERSION_STRING "535.261.03"
#else

1
src/common/nvswitch/kernel/ls10/minion_ls10.c
View File

@@ -934,7 +934,6 @@ cleanup:
if (tempStatus != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "Link %d Inband Buffer transfer for RX_BUFFER_CLEAR\n", linkId);
return;
}
if (device->link[linkId].inbandData.message != NULL)
{

5
src/nvidia/arch/nvalloc/common/inc/nvcst.h
View File

@@ -65,7 +65,6 @@ CHIPSET_SETUP_FUNC(Intel_0685_setupFunc)
CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
CHIPSET_SETUP_FUNC(Intel_1B81_setupFunc)
CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
@@ -187,8 +186,8 @@ CSINFO chipsetInfo[] =
{PCI_VENDOR_ID_INTEL, 0x4385, CS_INTEL_4381, "Intel-RocketLake", Intel_4381_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A82, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A84, CS_INTEL_7A82, "Intel-AlderLake", Intel_7A82_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", Intel_1B81_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x1B81, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A8A, CS_INTEL_1B81, "Intel-SapphireRapids", NULL},
{PCI_VENDOR_ID_INTEL, 0x18DC, CS_INTEL_18DC, "Intel-IceLake", NULL},
{PCI_VENDOR_ID_INTEL, 0x7A04, CS_INTEL_7A04, "Intel-RaptorLake", Intel_7A04_setupFunc},
{PCI_VENDOR_ID_INTEL, 0x5795, CS_INTEL_5795, "Intel-GraniteRapids", NULL},

14
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
View File

@@ -224,6 +224,20 @@
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0 0x000000D4
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1 0x000000D8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_VALUE 31:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE 0x00535442 //"BTS"
// Allocation of _VALUE bits
#define NV_PCI_VIRTUAL_CONFIG_BITS_PCI_EGRESS_POISON_ENABLE 0:0
// Chipset-specific definitions.
// Intel SantaRosa definitions
#define INTEL_2A00_CONFIG_SPACE_BASE 0x60

30
src/nvidia/arch/nvalloc/common/inc/oob/smbpbi_priv.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -47,33 +47,13 @@
#define NV_MSGBOX_CMD_ERR_MORE_PROCESSING_REQUIRED 0x000000F0
//
// Alternative encodings of the command word
// These are distinguished by a non-zero value in the 29:29 bit,
// previously known as _RSVD.
// Alternative encodings of the command word.
// These were distinguished by a non-zero value in the 29:29 bit.
// Bit 29 is now reserved and must be 0 i.e. only standard requests will be processed
// and debug requests would fail.
//
#define NV_MSGBOX_CMD_ENCODING 29:29
#define NV_MSGBOX_CMD_ENCODING_STANDARD 0x00000000
#define NV_MSGBOX_CMD_ENCODING_DEBUG 0x00000001
// Debug command structure
#define NV_MSGBOX_DEBUG_CMD_OPCODE 1:0
#define NV_MSGBOX_DEBUG_CMD_OPCODE_READ_PRIV 0x00000000
#define NV_MSGBOX_DEBUG_CMD_ARG 23:2
/* Utility command constructor macros */
#define NV_MSGBOX_DEBUG_CMD(opcode, arg) \
( \
DRF_DEF(_MSGBOX, _DEBUG_CMD, _OPCODE, opcode) | \
DRF_NUM(_MSGBOX, _DEBUG_CMD, _ARG, (arg)) | \
DRF_DEF(_MSGBOX, _CMD, _STATUS, _NULL) | \
DRF_DEF(_MSGBOX, _CMD, _ENCODING, _DEBUG) | \
DRF_DEF(_MSGBOX, _CMD, _INTR, _PENDING) \
)
#define NV_MSGBOX_DEBUG_CMD_READ_PRIV(offset) \
NV_MSGBOX_DEBUG_CMD(_READ_PRIV, (offset) >> 2)
#endif // _SMBPBI_PRIV_H_

8
src/nvidia/generated/g_gpu_access_nvoc.h
View File

@@ -216,6 +216,14 @@ void regCheckAndLogReadFailure(RegisterAccess *, NvU32 addr, NvU32 mask, NvU32 v
// Get the address of a register given the Aperture and offset.
#define REG_GET_ADDR(ap, offset) ioaprtGetRegAddr(ap, offset)
//
// These UNCHECKED macros are provided for extenuating circumstances to avoid the 0xbadf
// sanity checking done by the usual register read utilities and must not be used generally
//
//
#define GPU_REG_RD08_UNCHECKED(g,a) osDevReadReg008(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
#define GPU_REG_RD32_UNCHECKED(g,a) osDevReadReg032(g, gpuGetDeviceMapping(g, DEVICE_INDEX_GPU, 0), a)
// GPU macros defined in terms of DEV_ macros
#define GPU_REG_RD08(g,a) REG_INST_RD08(g,GPU,0,a)
#define GPU_REG_RD16(g,a) REG_INST_RD16(g,GPU,0,a)

3
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1016,6 +1016,7 @@ struct OBJGPU {
NvBool gpuLinkTerminationEnabled;
NvBool gspRmInitialized;
_GPU_PCIE_PEER_CLIQUE pciePeerClique;
NvU16 virtualConfigBits;
NvU32 i2cPortForExtdev;
GPUIDINFO idInfo;
_GPU_CHIP_INFO chipInfo;

1
src/nvidia/generated/rmconfig.h
View File

@@ -294,6 +294,7 @@
#define RMCFG_FEATURE_FEATURE_GH180 1 // RMconfig to encapsulate GH180 features
#define RMCFG_FEATURE_MULTICAST_FABRIC 1 // Support for MULTICAST_FABRIC
#define RMCFG_FEATURE_NVLINK_ERROR_THRESHOLD 1 // Support for NVLINK_ERROR_THRESHOLD
#define RMCFG_FEATURE_TPC_REPAIR 1 // Support for TPC swapping in-field
#define RMCFG_FEATURE_FABRIC_LINEAR_ADDRESSING 1 // Unicast fabric memory management

1
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -174,6 +174,7 @@ typedef struct GspSystemInfo
BUSINFO chipsetIDInfo;
ACPI_METHOD_DATA acpiMethodData;
NvU32 hypervisorType;
NvU16 virtualConfigBits;
NvBool bIsPassthru;
NvU64 sysTimerOffsetNs;
GSP_VF_INFO gspVFInfo;

7
src/nvidia/kernel/vgpu/nv/rpc.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1337,6 +1337,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid;
rpcInfo->hypervisorType = hypervisorGetHypervisorType(pHypervisor);
rpcInfo->virtualConfigBits = pGpu->virtualConfigBits;
rpcInfo->bIsPassthru = pGpu->bIsPassthru;
// Fill in VF related GPU flags
@@ -1457,6 +1458,8 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
if (IS_GSP_CLIENT(pGpu))
{
rpc_dump_protobuf_component_v18_12 *rpc_params = &rpc_message->dump_protobuf_component_v18_12;
const NvU32 fixed_param_size = sizeof(rpc_message_header_v) + sizeof(*rpc_params);
NV_ASSERT_OR_RETURN(fixed_param_size <= pRpc->maxRpcSize, NV_ERR_INVALID_STATE);
status = rpcWriteCommonHeader(pGpu, pRpc, NV_VGPU_MSG_FUNCTION_DUMP_PROTOBUF_COMPONENT,
sizeof(*rpc_params));
@@ -1468,7 +1471,7 @@ NV_STATUS rpcDumpProtobufComponent_v18_12
rpc_params->countOnly = ((pPrbEnc->flags & PRB_COUNT_ONLY) != 0);
rpc_params->bugCheckCode = pNvDumpState->bugCheckCode;
rpc_params->internalCode = pNvDumpState->internalCode;
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize, prbEncBufLeft(pPrbEnc));
rpc_params->bufferSize = NV_MIN(pRpc->maxRpcSize - fixed_param_size, prbEncBufLeft(pPrbEnc));
status = _issueRpcAndWait(pGpu, pRpc);

5
src/nvidia/src/kernel/gpu/arch/hopper/kern_gpu_gh100.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -22,6 +22,7 @@
*/
#include "gpu/gpu.h"
#include "gpu/gpu_access.h"
#include "gpu/gpu_child_class_defs.h"
#include "os/os.h"
#include "nverror.h"
@@ -95,7 +96,7 @@ gpuReadVgpuConfigReg_GH100
NvU32 *pData
)
{
*pData = GPU_REG_RD32(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
*pData = GPU_REG_RD32_UNCHECKED(pGpu, DEVICE_BASE(NV_EP_PCFGM) + index);
return NV_OK;
}

63
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,8 +229,30 @@ kfspIsQueueEmpty_IMPL
return (cmdqHead == cmdqTail);
}
/*
* @brief GpuWaitConditionFunc for MBOX receiver ready
*
* @param[in] pGpu GPU object pointer
* @param[in] pCondData KernelFsp object pointer
*
* @returns NvBool NV_TRUE if command and message fsp
* queues are empty
*/
static NvBool
_kfspWaitForQueuesEmpty
(
OBJGPU *pGpu,
void *pCondData
)
{
KernelFsp *pKernelFsp = (KernelFsp*) pCondData;
return kfspIsQueueEmpty(pGpu, pKernelFsp) &&
kfspIsMsgQueueEmpty(pGpu, pKernelFsp);
}
/*!
* @brief Wait for FSP RM command queue to be empty
* @brief Wait for FSP RM queues to be empty
*
* @param[in] pGpu OBJGPU pointer
* @param[in] pKernelFsp KernelFsp pointer
@@ -251,40 +273,11 @@ kfspPollForQueueEmpty_IMPL
GPU_TIMEOUT_FLAGS_OSTIMER |
GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
while (!kfspIsQueueEmpty(pGpu, pKernelFsp))
status = gpuTimeoutCondWait(pGpu, _kfspWaitForQueuesEmpty, pKernelFsp, &timeout);
if (status != NV_OK)
{
//
// For now we assume that any response from FSP before RM message
// send is complete indicates an error and we should abort.
//
// Ongoing dicussion on usefullness of this check. Bug to be filed.
//
if (!kfspIsMsgQueueEmpty(pGpu, pKernelFsp))
{
kfspReadMessage(pGpu, pKernelFsp, NULL, 0);
NV_PRINTF(LEVEL_ERROR,
"Received error message from FSP while waiting for CMDQ to be empty.\n");
status = NV_ERR_GENERIC;
break;
}
osSpinLoop();
status = gpuCheckTimeout(pGpu, &timeout);
if (status != NV_OK)
{
if ((status == NV_ERR_TIMEOUT) &&
kfspIsQueueEmpty(pGpu, pKernelFsp))
{
status = NV_OK;
}
else
{
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP command queue to be empty.\n");
}
break;
}
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP queues to be empty.\n");
}
return status;

2
src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c
View File

@@ -421,7 +421,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
.inst.request.requestFlags = pParams->flags
};
if (!hypervisorIsVgxHyper())
if (!gpuIsSriovEnabled(pGpu))
{
request.inst.request.requestFlags = FLD_SET_DRF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _WITH_PART_ID, _FALSE, request.inst.request.requestFlags);
}

13
src/nvidia/src/kernel/platform/chipset/chipset_info.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -903,17 +903,6 @@ Intel_7A04_setupFunc
return NV_OK;
}
static NV_STATUS
Intel_1B81_setupFunc
(
OBJCL *pCl
)
{
pCl->setProperty(pCl, PDB_PROP_CL_RELAXED_ORDERING_NOT_CAPABLE, NV_TRUE);
return NV_OK;
}
static NV_STATUS
Nvidia_T210_setupFunc
(

55
src/nvidia/src/kernel/platform/chipset/chipset_pcie.c
View File

@@ -73,6 +73,7 @@ static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *);
static void objClGpuUnmapEnhCfgSpace(OBJGPU *);
static NV_STATUS objClGpuIs3DController(OBJGPU *);
static void objClLoadPcieVirtualP2PApproval(OBJGPU *);
static void objClLoadPcieVirtualConfigBits(OBJGPU *);
static void objClCheckForExternalGpu(OBJGPU *, OBJCL *);
static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *);
static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *);
@@ -953,6 +954,9 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl)
// Load PCI Express virtual P2P approval config
objClLoadPcieVirtualP2PApproval(pGpu);
// Load additional configuraiton bits from virtualized cfg space
objClLoadPcieVirtualConfigBits(pGpu);
//
// Disable NOSNOOP bit for Passthrough.
//
@@ -4329,6 +4333,57 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu)
gpuGetInstance(pGpu), pGpu->pciePeerClique.id);
}
static void
objClLoadPcieVirtualConfigBits(OBJGPU *pGpu)
{
void *handle;
NvU32 data32;
NvU8 cap;
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU32 domain = gpuGetDomain(pGpu);
NvU32 offset = 0;
NvU32 sig = 0;
if (!IS_PASSTHRU(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"Skipping non-pass-through GPU%u\n", gpuGetInstance(pGpu));
return;
}
handle = osPciInitHandle(domain, bus, device, 0, NULL, NULL);
//
// Walk the list and find enable bits
//
cap = osPciReadByte(handle, PCI_CAPABILITY_LIST);
while ((cap != 0) && (sig != NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE))
{
offset = cap;
data32 = osPciReadDword(handle, offset);
cap = (NvU8)((data32 >> 8) & 0xFF);
if ((data32 & CAP_ID_MASK) != CAP_ID_VENDOR_SPECIFIC)
continue;
sig = DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_0, _SIG_LO, data32);
data32 = osPciReadDword(handle, offset + 4);
sig |= (DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _SIG_HI, data32) << 8);
}
if (sig == NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE)
{
// data32 now contains the second dword of the capability structure.
pGpu->virtualConfigBits =
(NvU16) DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _VALUE, data32);
NV_PRINTF(LEVEL_INFO,
"Hypervisor has specified config bits %u for GPU%u\n",
pGpu->virtualConfigBits, gpuGetInstance(pGpu));
}
}
/*!
* @brief Traverse bus topology till Gpu's root port.
* If any of the intermediate bridge has TB3 supported vendorId and hotplug

2
version.mk
View File

@@ -1,4 +1,4 @@
NVIDIA_VERSION = 535.247.01
NVIDIA_VERSION = 535.261.03
# This file.
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))