No longer supported by sonar scans, the preview feature is now disabled and internal PRs from project contributors are also scanned for vulnerabilities/bugs as part of CI
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
For testing purposes it should be possible to share .deb packages across a variety of Debian builds or .rpm packages across systems that have dnf/yum available
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
Removed installing for node.js section as latest versions of node have issues building until Swig is patched. Also make it clear some mainstream Linux don't have binaries available in official repos.
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
e.g.:
cv2 import at the beginning throws the error:
import cv2
import mraa
import time
...
Error:
ValueError: Error initialising PWM on pin
Signed-off-by: Brian Lee <brian@vamrs.com>
After rebase UP Xtreme supported platform enum value was changed
to 24 in types.h, this commit updates the enum value in types.hpp
to this value.
Signed-off-by: Michael Campion <michael.campion@emutex.com>
UP Xtreme is based on the Intel(R) Core(TM) i3/i5/i7 Whiskey Lake SoCs.
The UP Xtreme presents one Raspberry Pi compatible HAT connector.
This implementaion supports i2c, spi, uart, adc and gpio through the
40pin HAT connector.
Gpio chardev capabilities have been disabled in this implementation. When
gpio chardev capabilities are enabled an input becomes unreadable after an
isr has been registered to the pin. See here for details:
https://github.com/intel-iot-devkit/mraa/issues/937
Tested on UP Xtreme, with UP Board Linux kernel 5.0.0
Features tested: gpio, gpio interrupts, i2c, spi, adc and uart.
Signed-off-by: Michael Campion <michael.campion@emutex.com>
This commit introduces mraa_gpio_init_by_name API for initializing
a GPIO by its line name provided by the kernel. This feature depends
on the GPIO chardev support and also the line names present in devicetree
or board files. Accessing GPIO using its line name, removes the dependency
from MRAA specific pin mapping and provides a cleaner way to access GPIOs.
This will solve the issue created by an external gpiochip probing before
the SoC's internal gpio controller and thereby making the MRAA pin mapping
wrong.
Currently, this API only supports initializing a single GPIO at a time.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
