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RISC-V has some GNU disassembly quirks, e.g. it requires '-D' to
properly disassemble .2byte directives similar to Arm [1]. Further,
GNU objdump groups RISC-V instruction by 2 or 4 byte chunks, instead
doing byte-for-byte.
Add the required switches, and translate from short/word to bytes when
ARCH is "riscv".
An example how to invoke decodecode for RISC-V:
$ echo 'Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7)
6140' | AFLAGS="-march=rv64imac_zicbom_zihintpause" \
ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- ./scripts/decodecode
Code: bf45 f793 1007 f7d9 50ef 37af d541 b7d9 7097 00c8 (80e7) 6140
All code
========
0: bf45 c.j 0xffffffffffffffb0
2: 1007f793 andi a5,a5,256
6: f7d9 c.bnez a5,0xffffffffffffff94
8: 37af50ef jal ra,0xf5382
c: d541 c.beqz a0,0xffffffffffffff94
e: b7d9 c.j 0xffffffffffffffd4
10: 00c87097 auipc ra,0xc87
14:* 614080e7 jalr ra,1556(ra) # 0xc87624 <-- trapping instruction
Code starting with the faulting instruction
===========================================
0: 614080e7 jalr ra,1556(ra)
[1] https://sourceware.org/bugzilla/show_bug.cgi?id=10263
Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20230119074738.708301-3-bjorn@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.