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media: dvb-frontends/cxd2878: dos2unix
This commit is contained in:
CrazyCat
File diff suppressed because it is too large
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@@ -1,103 +1,103 @@
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#ifndef _CXD2878_H_
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#define _CXD2878_H_
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enum sony_demod_xtal_t{
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SONY_DEMOD_XTAL_16000KHz = 0, /**< 16 MHz */
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SONY_DEMOD_XTAL_24000KHz = 1, /**< 24 MHz */
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SONY_DEMOD_XTAL_32000KHz = 2 /**< 32 MHz */
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} ;
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enum sony_ascot3_xtal_t{
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SONY_ASCOT3_XTAL_16000KHz, /**< 16 MHz */
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SONY_ASCOT3_XTAL_20500KHz, /**< 20.5 MHz */
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SONY_ASCOT3_XTAL_24000KHz, /**< 24 MHz */
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SONY_ASCOT3_XTAL_41000KHz /**< 41 MHz */
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} ;
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#define SONY_DEMOD_MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/48.0)*16777216.0 + 0.5))
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#define SONY_DEMOD_ATSC_MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/24.0)*4294967296.0 + 0.5))
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struct cxd2878_config{
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u8 addr_slvt;
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enum sony_demod_xtal_t xtal;
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u8 tuner_addr;
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enum sony_ascot3_xtal_t tuner_xtal;
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//for ts
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// - 0: Serial output.
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// - 1: Parallel output (Default).
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u8 ts_mode;
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/**
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@brief Serial output pin of TS data.
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Value:
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- 0: Output from TSDATA0
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- 1: Output from TSDATA7 (Default).
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*/
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u8 ts_ser_data;
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/**
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@brief Serial TS clock gated on valid TS data or is continuous.
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Value is stored in demodulator structure to be applied during Sleep to Active
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transition.
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Value:
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- 0: Gated
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- 1: Continuous (Default)
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*/
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u8 ts_clk;
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/**
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@brief Disable/Enable TS clock during specified TS region.
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bit flags: ( can be bitwise ORed )
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- 0 : Always Active
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- 1 : Disable during TS packet gap (default)
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- 2 : Disable during TS parity (default)
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- 4 : Disable during TS payload
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- 8 : Disable during TS header
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- 16: Disable during TS sync
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*/
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u8 ts_clk_mask;
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/**
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@brief Disable/Enable TSVALID during specified TS region.
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bit flags: ( can be bitwise ORed )
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- 0 : Always Active
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- 1 : Disable during TS packet gap (default)
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- 2 : Disable during TS parity (default)
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- 4 : Disable during TS payload
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- 8 : Disable during TS header
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- 16: Disable during TS sync
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*/
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u8 ts_valid;
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u8 atscCoreDisable;
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bool lock_flag; //for usb device
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//for ecp3 update
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void (*write_properties) (struct i2c_adapter *i2c,u8 reg, u32 buf);
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void (*read_properties) (struct i2c_adapter *i2c,u8 reg, u32 *buf);
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// EEPROM access
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void (*write_eeprom) (struct i2c_adapter *i2c,u8 reg, u8 buf);
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void (*read_eeprom) (struct i2c_adapter *i2c,u8 reg, u8 *buf);
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//for 6590SE mode change(T or s);
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void (*RF_switch)(struct i2c_adapter * i2c,u8 rf_in,u8 flag);
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u8 rf_port; //for change command
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};
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#if IS_REACHABLE(CONFIG_DVB_CXD2878)
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extern struct dvb_frontend *cxd2878_attach(
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const struct cxd2878_config *config,
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struct i2c_adapter *i2c);
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#else
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static inline struct dvb_frontend *cxd2878_attach(
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const struct cxd2878_config *config,
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struct i2c_adapter *i2c)
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{
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dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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#endif
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#endif
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#ifndef _CXD2878_H_
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#define _CXD2878_H_
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enum sony_demod_xtal_t{
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SONY_DEMOD_XTAL_16000KHz = 0, /**< 16 MHz */
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SONY_DEMOD_XTAL_24000KHz = 1, /**< 24 MHz */
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SONY_DEMOD_XTAL_32000KHz = 2 /**< 32 MHz */
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} ;
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enum sony_ascot3_xtal_t{
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SONY_ASCOT3_XTAL_16000KHz, /**< 16 MHz */
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SONY_ASCOT3_XTAL_20500KHz, /**< 20.5 MHz */
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SONY_ASCOT3_XTAL_24000KHz, /**< 24 MHz */
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SONY_ASCOT3_XTAL_41000KHz /**< 41 MHz */
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} ;
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#define SONY_DEMOD_MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/48.0)*16777216.0 + 0.5))
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#define SONY_DEMOD_ATSC_MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/24.0)*4294967296.0 + 0.5))
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struct cxd2878_config{
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u8 addr_slvt;
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enum sony_demod_xtal_t xtal;
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u8 tuner_addr;
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enum sony_ascot3_xtal_t tuner_xtal;
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//for ts
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// - 0: Serial output.
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// - 1: Parallel output (Default).
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u8 ts_mode;
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/**
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@brief Serial output pin of TS data.
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Value:
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- 0: Output from TSDATA0
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- 1: Output from TSDATA7 (Default).
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*/
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u8 ts_ser_data;
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/**
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@brief Serial TS clock gated on valid TS data or is continuous.
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Value is stored in demodulator structure to be applied during Sleep to Active
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transition.
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Value:
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- 0: Gated
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- 1: Continuous (Default)
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*/
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u8 ts_clk;
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/**
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@brief Disable/Enable TS clock during specified TS region.
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bit flags: ( can be bitwise ORed )
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- 0 : Always Active
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- 1 : Disable during TS packet gap (default)
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- 2 : Disable during TS parity (default)
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- 4 : Disable during TS payload
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- 8 : Disable during TS header
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- 16: Disable during TS sync
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*/
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u8 ts_clk_mask;
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/**
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@brief Disable/Enable TSVALID during specified TS region.
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bit flags: ( can be bitwise ORed )
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- 0 : Always Active
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- 1 : Disable during TS packet gap (default)
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- 2 : Disable during TS parity (default)
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- 4 : Disable during TS payload
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- 8 : Disable during TS header
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- 16: Disable during TS sync
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*/
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u8 ts_valid;
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u8 atscCoreDisable;
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bool lock_flag; //for usb device
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//for ecp3 update
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void (*write_properties) (struct i2c_adapter *i2c,u8 reg, u32 buf);
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void (*read_properties) (struct i2c_adapter *i2c,u8 reg, u32 *buf);
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// EEPROM access
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void (*write_eeprom) (struct i2c_adapter *i2c,u8 reg, u8 buf);
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void (*read_eeprom) (struct i2c_adapter *i2c,u8 reg, u8 *buf);
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//for 6590SE mode change(T or s);
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void (*RF_switch)(struct i2c_adapter * i2c,u8 rf_in,u8 flag);
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u8 rf_port; //for change command
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};
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#if IS_REACHABLE(CONFIG_DVB_CXD2878)
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extern struct dvb_frontend *cxd2878_attach(
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const struct cxd2878_config *config,
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struct i2c_adapter *i2c);
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#else
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static inline struct dvb_frontend *cxd2878_attach(
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const struct cxd2878_config *config,
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struct i2c_adapter *i2c)
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{
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dev_warn(&i2c->dev, "%s: driver disabled by Kconfig\n", __func__);
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return NULL;
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}
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#endif
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#endif
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@@ -1,161 +1,161 @@
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#ifndef _CXD2878_PRIV_H_
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#define _CXD2878_PRIV_H_
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#define AUTO (0xFF) /* For IF_OUT_SEL and AGC_SEL, it means that the value is desided by config flags. */
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/* For RF_GAIN, it means that RF_GAIN_SEL(SubAddr:0x4E) = 1 */
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#define OFFSET(ofs) ((u8)(ofs) & 0x1F)
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#define BW_6 (0x00)
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#define BW_7 (0x01)
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#define BW_8 (0x02)
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#define BW_1_7 (0x03)
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#define MAX_BIT_PRECISION 5
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#define FRAC_BITMASK 0x1F
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#define LOG2_10_100X 332 /**< log2 (10) */
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#define LOG2_E_100X 144 /**< log2 (e) */
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//////////////////////////////
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enum sony_ascot3_tv_system_t{
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SONY_ASCOT3_TV_SYSTEM_UNKNOWN,
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/* Analog */
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SONY_ASCOT3_ATV_MN_EIAJ, /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
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SONY_ASCOT3_ATV_MN_SAP, /**< System-M (US) (IF: Fp=5.75MHz in default) */
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SONY_ASCOT3_ATV_MN_A2, /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
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SONY_ASCOT3_ATV_BG, /**< System-B/G (IF: Fp=7.3MHz in default) */
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SONY_ASCOT3_ATV_I, /**< System-I (IF: Fp=7.85MHz in default) */
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SONY_ASCOT3_ATV_DK, /**< System-D/K (IF: Fp=7.85MHz in default) */
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SONY_ASCOT3_ATV_L, /**< System-L (IF: Fp=7.85MHz in default) */
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SONY_ASCOT3_ATV_L_DASH, /**< System-L DASH (IF: Fp=2.2MHz in default) */
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/* Digital */
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SONY_ASCOT3_DTV_8VSB, /**< ATSC 8VSB (IF: Fc=3.7MHz in default) */
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SONY_ASCOT3_DTV_QAM, /**< US QAM (IF: Fc=3.7MHz in default) */
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SONY_ASCOT3_DTV_ISDBT_6, /**< ISDB-T 6MHzBW (IF: Fc=3.55MHz in default) */
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SONY_ASCOT3_DTV_ISDBT_7, /**< ISDB-T 7MHzBW (IF: Fc=4.15MHz in default) */
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SONY_ASCOT3_DTV_ISDBT_8, /**< ISDB-T 8MHzBW (IF: Fc=4.75MHz in default) */
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SONY_ASCOT3_DTV_DVBT_5, /**< DVB-T 5MHzBW (IF: Fc=3.6MHz in default) */
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SONY_ASCOT3_DTV_DVBT_6, /**< DVB-T 6MHzBW (IF: Fc=3.6MHz in default) */
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SONY_ASCOT3_DTV_DVBT_7, /**< DVB-T 7MHzBW (IF: Fc=4.2MHz in default) */
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SONY_ASCOT3_DTV_DVBT_8, /**< DVB-T 8MHzBW (IF: Fc=4.8MHz in default) */
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SONY_ASCOT3_DTV_DVBT2_1_7,/**< DVB-T2 1.7MHzBW (IF: Fc=3.5MHz in default) */
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SONY_ASCOT3_DTV_DVBT2_5, /**< DVB-T2 5MHzBW (IF: Fc=3.6MHz in default) */
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SONY_ASCOT3_DTV_DVBT2_6, /**< DVB-T2 6MHzBW (IF: Fc=3.6MHz in default) */
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SONY_ASCOT3_DTV_DVBT2_7, /**< DVB-T2 7MHzBW (IF: Fc=4.2MHz in default) */
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SONY_ASCOT3_DTV_DVBT2_8, /**< DVB-T2 8MHzBW (IF: Fc=4.8MHz in default) */
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SONY_ASCOT3_DTV_DVBC_6, /**< DVB-C 6MHzBW (IF: Fc=3.7MHz in default) */
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SONY_ASCOT3_DTV_DVBC_8, /**< DVB-C 8MHzBW (IF: Fc=4.9MHz in default) */
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SONY_ASCOT3_DTV_DVBC2_6, /**< DVB-C2 6MHzBW (IF: Fc=3.7MHz in default) */
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SONY_ASCOT3_DTV_DVBC2_8, /**< DVB-C2 8MHzBW (IF: Fc=4.9MHz in default) */
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SONY_ASCOT3_DTV_ATSC3_6, /**< ATSC 3.0 6MHzBW (IF: Fc=3.6MHz in default) */
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SONY_ASCOT3_DTV_ATSC3_7, /**< ATSC 3.0 7MHzBW (IF: Fc=4.2MHz in default) */
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SONY_ASCOT3_DTV_ATSC3_8, /**< ATSC 3.0 8MHzBW (IF: Fc=4.8MHz in default) */
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SONY_ASCOT3_DTV_J83B_5_6, /**< J.83B 5.6Msps (IF: Fc=3.75MHz in default) */
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SONY_ASCOT3_DTV_DTMB, /**< DTMB (IF: Fc=5.1MHz in default) */
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SONY_ASCOT3_ATV_MIN = SONY_ASCOT3_ATV_MN_EIAJ, /**< Minimum analog terrestrial system */
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SONY_ASCOT3_ATV_MAX = SONY_ASCOT3_ATV_L_DASH, /**< Maximum analog terrestrial system */
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SONY_ASCOT3_DTV_MIN = SONY_ASCOT3_DTV_8VSB, /**< Minimum digital terrestrial system */
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SONY_ASCOT3_DTV_MAX = SONY_ASCOT3_DTV_DTMB, /**< Maximum digital terrestrial system */
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SONY_ASCOT3_TV_SYSTEM_NUM /**< Number of supported broadcasting system */
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} ;
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struct sony_ascot3_adjust_param_t {
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u8 OUTLMT; /**< Addr:0x68 Bit[1:0] : Maximum IF output. (0: 1.5Vp-p, 1: 1.2Vp-p) */
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u8 RF_GAIN; /**< Addr:0x69 Bit[6:4] : RFVGA gain. 0xFF means Auto. (RF_GAIN_SEL = 1) */
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u8 IF_BPF_GC; /**< Addr:0x69 Bit[3:0] : IF_BPF gain. */
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u8 RFOVLD_DET_LV1_VL; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (FRF <= 172MHz) */
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u8 RFOVLD_DET_LV1_VH; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (172MHz < FRF <= 464MHz) */
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u8 RFOVLD_DET_LV1_U; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (FRF > 464MHz) */
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u8 IFOVLD_DET_LV_VL; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (FRF <= 172MHz) */
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u8 IFOVLD_DET_LV_VH; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (172MHz < FRF <= 464MHz) */
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u8 IFOVLD_DET_LV_U; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (FRF > 464MHz) */
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u8 IF_BPF_F0; /**< Addr:0x6D Bit[5:4] : IF filter center offset. */
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u8 BW; /**< Addr:0x6D Bit[1:0] : 6MHzBW(0x00) or 7MHzBW(0x01) or 8MHzBW(0x02) or 1.7MHzBW(0x03) */
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u8 FIF_OFFSET; /**< Addr:0x6E Bit[4:0] : 5bit signed. IF offset (kHz) = FIF_OFFSET x 50 */
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u8 BW_OFFSET; /**< Addr:0x6F Bit[4:0] : 5bit signed. BW offset (kHz) = BW_OFFSET x 50 (BW_OFFSET x 10 in 1.7MHzBW) */
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u8 AGC_SEL; /**< Addr:0x74 Bit[5:4] : AGC pin select. (0: AGC1, 1: AGC2) 0xFF means Auto (by config flags) */
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u8 IF_OUT_SEL; /**< Addr:0x74 Bit[1:0] : IFOUT pin select. (0: IFOUT1, 1: IFOUT2) 0xFF means Auto. (by config flags) */
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u8 IS_LOWERLOCAL; /**< Addr:0x9C Bit[0] : Local polarity. (0: Upper Local, 1: Lower Local) */
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} ;
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////////////////////////
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enum sony_demod_chip_id_t{
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SONY_DEMOD_CHIP_ID_UNKNOWN = 0, /**< Unknown */
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SONY_DEMOD_CHIP_ID_CXD2856 = 0x090, /**< CXD2856 / CXD6800(SiP) */
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SONY_DEMOD_CHIP_ID_CXD2857 = 0x091, /**< CXD2857 */
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SONY_DEMOD_CHIP_ID_CXD2878 = 0x396, /**< CXD2878 / CXD6801(SiP) */
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SONY_DEMOD_CHIP_ID_CXD2879 = 0x297, /**< CXD2879 */
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SONY_DEMOD_CHIP_ID_CXD6802 = 0x197 /**< CXD6802(SiP) */
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} ;
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enum sony_ascot3_chip_id_t{
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SONY_ASCOT3_CHIP_ID_UNKNOWN, /**< Unknown */
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SONY_ASCOT3_CHIP_ID_2871, /**< CXD2871 (for TV) */
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SONY_ASCOT3_CHIP_ID_2872, /**< CXD2872 (for STB) */
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SONY_ASCOT3_CHIP_ID_2871A, /**< CXD2871A (ASCOT3I) (for TV) */
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SONY_ASCOT3_CHIP_ID_2875 /**< CXD2875 */
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} ;
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enum sony_dtv_system_t{
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SONY_DTV_SYSTEM_UNKNOWN, /**< Unknown. */
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SONY_DTV_SYSTEM_DVBT, /**< DVB-T */
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SONY_DTV_SYSTEM_DVBT2, /**< DVB-T2 */
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SONY_DTV_SYSTEM_DVBC, /**< DVB-C(J.83A) */
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SONY_DTV_SYSTEM_DVBC2, /**< DVB-C2(J.382) */
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SONY_DTV_SYSTEM_ATSC, /**< ATSC */
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SONY_DTV_SYSTEM_ATSC3, /**< ATSC3.0 */
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SONY_DTV_SYSTEM_ISDBT, /**< ISDB-T */
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SONY_DTV_SYSTEM_ISDBC, /**< ISDB-C(J.83C) */
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SONY_DTV_SYSTEM_J83B, /**< J.83B */
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SONY_DTV_SYSTEM_DVBS, /**< DVB-S */
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SONY_DTV_SYSTEM_DVBS2, /**< DVB-S2 */
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SONY_DTV_SYSTEM_ISDBS, /**< ISDB-S */
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SONY_DTV_SYSTEM_ISDBS3, /**< ISDB-S3 */
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SONY_DTV_SYSTEM_ANY /**< Used for multiple system scanning / blind tuning */
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} ;
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enum sony_dtv_bandwidth_t{
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SONY_DTV_BW_UNKNOWN = 0, /**< Unknown bandwidth. */
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SONY_DTV_BW_1_7_MHZ = 1, /**< 1.7MHz bandwidth. */
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SONY_DTV_BW_5_MHZ = 5, /**< 5MHz bandwidth. */
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SONY_DTV_BW_6_MHZ = 6, /**< 6MHz bandwidth. */
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SONY_DTV_BW_7_MHZ = 7, /**< 7MHz bandwidth. */
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SONY_DTV_BW_8_MHZ = 8, /**< 8MHz bandwidth. */
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SONY_DTV_BW_J83B_5_06_5_36_MSPS = 50, /**< For J.83B. 5.06/5.36Msps auto selection commonly used in US. */
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SONY_DTV_BW_J83B_5_60_MSPS = 51 /**< For J.83B. 5.6Msps used by SKY PerfecTV! Hikari in Japan. */
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} ;
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enum sony_demod_state_t{
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SONY_DEMOD_STATE_UNKNOWN, /**< Unknown. */
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SONY_DEMOD_STATE_SHUTDOWN, /**< Chip is in Shutdown state. */
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SONY_DEMOD_STATE_SLEEP, /**< Chip is in Sleep state. */
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SONY_DEMOD_STATE_ACTIVE, /**< Chip is in Active state. */
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SONY_DEMOD_STATE_INVALID /**< Invalid, result of an error during a state change. */
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} ;
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struct sony_demod_ts_clk_configuration_t{
|
||||
u8 serialClkMode; /**< Serial clock mode (gated or continuous) */
|
||||
u8 serialDutyMode; /**< Serial clock duty mode (full rate or half rate) */
|
||||
u8 tsClkPeriod; /**< TS clock period */
|
||||
u8 clkSelTSIf; /**< TS clock frequency (low, mid or high) */
|
||||
} ;
|
||||
struct sony_demod_iffreq_config_t{
|
||||
u32 configDVBT_5; /**< DVB-T 5MHz */
|
||||
u32 configDVBT_6; /**< DVB-T 6MHz */
|
||||
u32 configDVBT_7; /**< DVB-T 7MHz */
|
||||
u32 configDVBT_8; /**< DVB-T 8MHz */
|
||||
u32 configDVBT2_1_7; /**< DVB-T2 1.7MHz */
|
||||
u32 configDVBT2_5; /**< DVB-T2 5MHz */
|
||||
u32 configDVBT2_6; /**< DVB-T2 6MHz */
|
||||
u32 configDVBT2_7; /**< DVB-T2 7MHz */
|
||||
u32 configDVBT2_8; /**< DVB-T2 8MHz */
|
||||
u32 configDVBC_6; /**< DVB-C 6MHz */
|
||||
u32 configDVBC_7; /**< DVB-C 7MHz */
|
||||
u32 configDVBC_8; /**< DVB-C 8MHz */
|
||||
u32 configATSC; /**< ATSC 1.0 */
|
||||
u32 configISDBT_6; /**< ISDB-T 6MHz */
|
||||
u32 configISDBT_7; /**< ISDB-T 7MHz */
|
||||
u32 configISDBT_8; /**< ISDB-T 8MHz */
|
||||
u32 configJ83B_5_06_5_36; /**< J.83B 5.06/5.36Msps auto selection */
|
||||
u32 configJ83B_5_60; /**< J.83B. 5.6Msps */
|
||||
} ;
|
||||
|
||||
|
||||
#endif
|
||||
#ifndef _CXD2878_PRIV_H_
|
||||
#define _CXD2878_PRIV_H_
|
||||
|
||||
#define AUTO (0xFF) /* For IF_OUT_SEL and AGC_SEL, it means that the value is desided by config flags. */
|
||||
/* For RF_GAIN, it means that RF_GAIN_SEL(SubAddr:0x4E) = 1 */
|
||||
#define OFFSET(ofs) ((u8)(ofs) & 0x1F)
|
||||
#define BW_6 (0x00)
|
||||
#define BW_7 (0x01)
|
||||
#define BW_8 (0x02)
|
||||
#define BW_1_7 (0x03)
|
||||
|
||||
#define MAX_BIT_PRECISION 5
|
||||
#define FRAC_BITMASK 0x1F
|
||||
#define LOG2_10_100X 332 /**< log2 (10) */
|
||||
#define LOG2_E_100X 144 /**< log2 (e) */
|
||||
|
||||
//////////////////////////////
|
||||
enum sony_ascot3_tv_system_t{
|
||||
SONY_ASCOT3_TV_SYSTEM_UNKNOWN,
|
||||
/* Analog */
|
||||
SONY_ASCOT3_ATV_MN_EIAJ, /**< System-M (Japan) (IF: Fp=5.75MHz in default) */
|
||||
SONY_ASCOT3_ATV_MN_SAP, /**< System-M (US) (IF: Fp=5.75MHz in default) */
|
||||
SONY_ASCOT3_ATV_MN_A2, /**< System-M (Korea) (IF: Fp=5.9MHz in default) */
|
||||
SONY_ASCOT3_ATV_BG, /**< System-B/G (IF: Fp=7.3MHz in default) */
|
||||
SONY_ASCOT3_ATV_I, /**< System-I (IF: Fp=7.85MHz in default) */
|
||||
SONY_ASCOT3_ATV_DK, /**< System-D/K (IF: Fp=7.85MHz in default) */
|
||||
SONY_ASCOT3_ATV_L, /**< System-L (IF: Fp=7.85MHz in default) */
|
||||
SONY_ASCOT3_ATV_L_DASH, /**< System-L DASH (IF: Fp=2.2MHz in default) */
|
||||
/* Digital */
|
||||
SONY_ASCOT3_DTV_8VSB, /**< ATSC 8VSB (IF: Fc=3.7MHz in default) */
|
||||
SONY_ASCOT3_DTV_QAM, /**< US QAM (IF: Fc=3.7MHz in default) */
|
||||
SONY_ASCOT3_DTV_ISDBT_6, /**< ISDB-T 6MHzBW (IF: Fc=3.55MHz in default) */
|
||||
SONY_ASCOT3_DTV_ISDBT_7, /**< ISDB-T 7MHzBW (IF: Fc=4.15MHz in default) */
|
||||
SONY_ASCOT3_DTV_ISDBT_8, /**< ISDB-T 8MHzBW (IF: Fc=4.75MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT_5, /**< DVB-T 5MHzBW (IF: Fc=3.6MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT_6, /**< DVB-T 6MHzBW (IF: Fc=3.6MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT_7, /**< DVB-T 7MHzBW (IF: Fc=4.2MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT_8, /**< DVB-T 8MHzBW (IF: Fc=4.8MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT2_1_7,/**< DVB-T2 1.7MHzBW (IF: Fc=3.5MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT2_5, /**< DVB-T2 5MHzBW (IF: Fc=3.6MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT2_6, /**< DVB-T2 6MHzBW (IF: Fc=3.6MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT2_7, /**< DVB-T2 7MHzBW (IF: Fc=4.2MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBT2_8, /**< DVB-T2 8MHzBW (IF: Fc=4.8MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBC_6, /**< DVB-C 6MHzBW (IF: Fc=3.7MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBC_8, /**< DVB-C 8MHzBW (IF: Fc=4.9MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBC2_6, /**< DVB-C2 6MHzBW (IF: Fc=3.7MHz in default) */
|
||||
SONY_ASCOT3_DTV_DVBC2_8, /**< DVB-C2 8MHzBW (IF: Fc=4.9MHz in default) */
|
||||
SONY_ASCOT3_DTV_ATSC3_6, /**< ATSC 3.0 6MHzBW (IF: Fc=3.6MHz in default) */
|
||||
SONY_ASCOT3_DTV_ATSC3_7, /**< ATSC 3.0 7MHzBW (IF: Fc=4.2MHz in default) */
|
||||
SONY_ASCOT3_DTV_ATSC3_8, /**< ATSC 3.0 8MHzBW (IF: Fc=4.8MHz in default) */
|
||||
SONY_ASCOT3_DTV_J83B_5_6, /**< J.83B 5.6Msps (IF: Fc=3.75MHz in default) */
|
||||
SONY_ASCOT3_DTV_DTMB, /**< DTMB (IF: Fc=5.1MHz in default) */
|
||||
|
||||
SONY_ASCOT3_ATV_MIN = SONY_ASCOT3_ATV_MN_EIAJ, /**< Minimum analog terrestrial system */
|
||||
SONY_ASCOT3_ATV_MAX = SONY_ASCOT3_ATV_L_DASH, /**< Maximum analog terrestrial system */
|
||||
SONY_ASCOT3_DTV_MIN = SONY_ASCOT3_DTV_8VSB, /**< Minimum digital terrestrial system */
|
||||
SONY_ASCOT3_DTV_MAX = SONY_ASCOT3_DTV_DTMB, /**< Maximum digital terrestrial system */
|
||||
SONY_ASCOT3_TV_SYSTEM_NUM /**< Number of supported broadcasting system */
|
||||
} ;
|
||||
|
||||
struct sony_ascot3_adjust_param_t {
|
||||
u8 OUTLMT; /**< Addr:0x68 Bit[1:0] : Maximum IF output. (0: 1.5Vp-p, 1: 1.2Vp-p) */
|
||||
u8 RF_GAIN; /**< Addr:0x69 Bit[6:4] : RFVGA gain. 0xFF means Auto. (RF_GAIN_SEL = 1) */
|
||||
u8 IF_BPF_GC; /**< Addr:0x69 Bit[3:0] : IF_BPF gain. */
|
||||
u8 RFOVLD_DET_LV1_VL; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (FRF <= 172MHz) */
|
||||
u8 RFOVLD_DET_LV1_VH; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (172MHz < FRF <= 464MHz) */
|
||||
u8 RFOVLD_DET_LV1_U; /**< Addr:0x6B Bit[3:0] : RF overload RF input detect level. (FRF > 464MHz) */
|
||||
u8 IFOVLD_DET_LV_VL; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (FRF <= 172MHz) */
|
||||
u8 IFOVLD_DET_LV_VH; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (172MHz < FRF <= 464MHz) */
|
||||
u8 IFOVLD_DET_LV_U; /**< Addr:0x6C Bit[2:0] : Internal RFAGC detect level. (FRF > 464MHz) */
|
||||
u8 IF_BPF_F0; /**< Addr:0x6D Bit[5:4] : IF filter center offset. */
|
||||
u8 BW; /**< Addr:0x6D Bit[1:0] : 6MHzBW(0x00) or 7MHzBW(0x01) or 8MHzBW(0x02) or 1.7MHzBW(0x03) */
|
||||
u8 FIF_OFFSET; /**< Addr:0x6E Bit[4:0] : 5bit signed. IF offset (kHz) = FIF_OFFSET x 50 */
|
||||
u8 BW_OFFSET; /**< Addr:0x6F Bit[4:0] : 5bit signed. BW offset (kHz) = BW_OFFSET x 50 (BW_OFFSET x 10 in 1.7MHzBW) */
|
||||
u8 AGC_SEL; /**< Addr:0x74 Bit[5:4] : AGC pin select. (0: AGC1, 1: AGC2) 0xFF means Auto (by config flags) */
|
||||
u8 IF_OUT_SEL; /**< Addr:0x74 Bit[1:0] : IFOUT pin select. (0: IFOUT1, 1: IFOUT2) 0xFF means Auto. (by config flags) */
|
||||
u8 IS_LOWERLOCAL; /**< Addr:0x9C Bit[0] : Local polarity. (0: Upper Local, 1: Lower Local) */
|
||||
} ;
|
||||
////////////////////////
|
||||
enum sony_demod_chip_id_t{
|
||||
SONY_DEMOD_CHIP_ID_UNKNOWN = 0, /**< Unknown */
|
||||
SONY_DEMOD_CHIP_ID_CXD2856 = 0x090, /**< CXD2856 / CXD6800(SiP) */
|
||||
SONY_DEMOD_CHIP_ID_CXD2857 = 0x091, /**< CXD2857 */
|
||||
SONY_DEMOD_CHIP_ID_CXD2878 = 0x396, /**< CXD2878 / CXD6801(SiP) */
|
||||
SONY_DEMOD_CHIP_ID_CXD2879 = 0x297, /**< CXD2879 */
|
||||
SONY_DEMOD_CHIP_ID_CXD6802 = 0x197 /**< CXD6802(SiP) */
|
||||
} ;
|
||||
enum sony_ascot3_chip_id_t{
|
||||
SONY_ASCOT3_CHIP_ID_UNKNOWN, /**< Unknown */
|
||||
SONY_ASCOT3_CHIP_ID_2871, /**< CXD2871 (for TV) */
|
||||
SONY_ASCOT3_CHIP_ID_2872, /**< CXD2872 (for STB) */
|
||||
SONY_ASCOT3_CHIP_ID_2871A, /**< CXD2871A (ASCOT3I) (for TV) */
|
||||
SONY_ASCOT3_CHIP_ID_2875 /**< CXD2875 */
|
||||
} ;
|
||||
enum sony_dtv_system_t{
|
||||
SONY_DTV_SYSTEM_UNKNOWN, /**< Unknown. */
|
||||
SONY_DTV_SYSTEM_DVBT, /**< DVB-T */
|
||||
SONY_DTV_SYSTEM_DVBT2, /**< DVB-T2 */
|
||||
SONY_DTV_SYSTEM_DVBC, /**< DVB-C(J.83A) */
|
||||
SONY_DTV_SYSTEM_DVBC2, /**< DVB-C2(J.382) */
|
||||
SONY_DTV_SYSTEM_ATSC, /**< ATSC */
|
||||
SONY_DTV_SYSTEM_ATSC3, /**< ATSC3.0 */
|
||||
SONY_DTV_SYSTEM_ISDBT, /**< ISDB-T */
|
||||
SONY_DTV_SYSTEM_ISDBC, /**< ISDB-C(J.83C) */
|
||||
SONY_DTV_SYSTEM_J83B, /**< J.83B */
|
||||
SONY_DTV_SYSTEM_DVBS, /**< DVB-S */
|
||||
SONY_DTV_SYSTEM_DVBS2, /**< DVB-S2 */
|
||||
SONY_DTV_SYSTEM_ISDBS, /**< ISDB-S */
|
||||
SONY_DTV_SYSTEM_ISDBS3, /**< ISDB-S3 */
|
||||
SONY_DTV_SYSTEM_ANY /**< Used for multiple system scanning / blind tuning */
|
||||
} ;
|
||||
|
||||
|
||||
enum sony_dtv_bandwidth_t{
|
||||
SONY_DTV_BW_UNKNOWN = 0, /**< Unknown bandwidth. */
|
||||
SONY_DTV_BW_1_7_MHZ = 1, /**< 1.7MHz bandwidth. */
|
||||
SONY_DTV_BW_5_MHZ = 5, /**< 5MHz bandwidth. */
|
||||
SONY_DTV_BW_6_MHZ = 6, /**< 6MHz bandwidth. */
|
||||
SONY_DTV_BW_7_MHZ = 7, /**< 7MHz bandwidth. */
|
||||
SONY_DTV_BW_8_MHZ = 8, /**< 8MHz bandwidth. */
|
||||
|
||||
SONY_DTV_BW_J83B_5_06_5_36_MSPS = 50, /**< For J.83B. 5.06/5.36Msps auto selection commonly used in US. */
|
||||
SONY_DTV_BW_J83B_5_60_MSPS = 51 /**< For J.83B. 5.6Msps used by SKY PerfecTV! Hikari in Japan. */
|
||||
} ;
|
||||
|
||||
enum sony_demod_state_t{
|
||||
SONY_DEMOD_STATE_UNKNOWN, /**< Unknown. */
|
||||
SONY_DEMOD_STATE_SHUTDOWN, /**< Chip is in Shutdown state. */
|
||||
SONY_DEMOD_STATE_SLEEP, /**< Chip is in Sleep state. */
|
||||
SONY_DEMOD_STATE_ACTIVE, /**< Chip is in Active state. */
|
||||
SONY_DEMOD_STATE_INVALID /**< Invalid, result of an error during a state change. */
|
||||
} ;
|
||||
struct sony_demod_ts_clk_configuration_t{
|
||||
u8 serialClkMode; /**< Serial clock mode (gated or continuous) */
|
||||
u8 serialDutyMode; /**< Serial clock duty mode (full rate or half rate) */
|
||||
u8 tsClkPeriod; /**< TS clock period */
|
||||
u8 clkSelTSIf; /**< TS clock frequency (low, mid or high) */
|
||||
} ;
|
||||
struct sony_demod_iffreq_config_t{
|
||||
u32 configDVBT_5; /**< DVB-T 5MHz */
|
||||
u32 configDVBT_6; /**< DVB-T 6MHz */
|
||||
u32 configDVBT_7; /**< DVB-T 7MHz */
|
||||
u32 configDVBT_8; /**< DVB-T 8MHz */
|
||||
u32 configDVBT2_1_7; /**< DVB-T2 1.7MHz */
|
||||
u32 configDVBT2_5; /**< DVB-T2 5MHz */
|
||||
u32 configDVBT2_6; /**< DVB-T2 6MHz */
|
||||
u32 configDVBT2_7; /**< DVB-T2 7MHz */
|
||||
u32 configDVBT2_8; /**< DVB-T2 8MHz */
|
||||
u32 configDVBC_6; /**< DVB-C 6MHz */
|
||||
u32 configDVBC_7; /**< DVB-C 7MHz */
|
||||
u32 configDVBC_8; /**< DVB-C 8MHz */
|
||||
u32 configATSC; /**< ATSC 1.0 */
|
||||
u32 configISDBT_6; /**< ISDB-T 6MHz */
|
||||
u32 configISDBT_7; /**< ISDB-T 7MHz */
|
||||
u32 configISDBT_8; /**< ISDB-T 8MHz */
|
||||
u32 configJ83B_5_06_5_36; /**< J.83B 5.06/5.36Msps auto selection */
|
||||
u32 configJ83B_5_60; /**< J.83B. 5.6Msps */
|
||||
} ;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user