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Merge patch series "RISC-V: Fixes for riscv_has_extension[un]likely()'s alternative dependency"

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Conor Dooley <conor.dooley@microchip.com> says:

Here's my attempt at fixing both the use of an FPU on XIP kernels and
the issue that Jason ran into where CONFIG_FPU, which needs the
alternatives frame work for has_fpu() checks, could be enabled without
the alternatives actually being present.

For the former, a "slow" fallback that does not use alternatives is
added to riscv_has_extension_[un]likely() that can be used with XIP.
Obviously, we want to make use of Jisheng's alternatives based approach
where possible, so any users of riscv_has_extension_[un]likely() will
want to make sure that they select RISCV_ALTERNATIVE.
If they don't however, they'll hit the fallback path which (should,
sparing a silly mistake from me!) behave in the same way, thus
succeeding silently. Sounds like a

To prevent "depends on !XIP_KERNEL; select RISCV_ALTERNATIVE" spreading
like the plague through the various places that want to check for the
presence of extensions, and sidestep the potential silent "success"
mentioned above, all users RISCV_ALTERNATIVE are converted from selects
to dependencies, with the option being selected for all !XIP_KERNEL
builds.

I know that the VDSO was a key place that Jisheng wanted to use the new
helper rather than static branches, and I think the fallback path
should not cause issues there.

See the thread at [1] for the prior discussion.

1 - https://lore.kernel.org/linux-riscv/20230128172856.3814-1-jszhang@kernel.org/T/#m21390d570997145d31dd8bb95002fd61f99c6573

[Palmer: these were also merged into fixes, but there's a cleanup that
depends on the merge so I'm taking it into for-next as well.]

* b4-shazam-merge:
  RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
  RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()

Link: https://lore.kernel.org/r/20230324100538.3514663-1-conor.dooley@microchip.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

* commit '1ee7fc3f4d0a93831a20d5566f203d5ad6d44de8':
  RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
  RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()
This commit is contained in:
Palmer Dabbelt
2023-03-29 11:56:08 -07:00
parent e97be4fbc1 1ee7fc3f4d
commit be693ef2a4
3 changed files with 38 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/riscv/Kconfig
View File

@@ -127,6 +127,7 @@ config RISCV
select OF_IRQ select OF_IRQ
select PCI_DOMAINS_GENERIC if PCI select PCI_DOMAINS_GENERIC if PCI
select PCI_MSI if PCI select PCI_MSI if PCI
select RISCV_ALTERNATIVE if !XIP_KERNEL
select RISCV_INTC select RISCV_INTC
select RISCV_TIMER if RISCV_SBI select RISCV_TIMER if RISCV_SBI
select SIFIVE_PLIC select SIFIVE_PLIC
@@ -420,9 +421,8 @@ config RISCV_ISA_SVNAPOT
config RISCV_ISA_SVPBMT config RISCV_ISA_SVPBMT
bool "SVPBMT extension support" bool "SVPBMT extension support"
depends on 64BIT && MMU depends on 64BIT && MMU
depends on !XIP_KERNEL depends on RISCV_ALTERNATIVE
default y default y
select RISCV_ALTERNATIVE
help help
Adds support to dynamically detect the presence of the SVPBMT Adds support to dynamically detect the presence of the SVPBMT
ISA-extension (Supervisor-mode: page-based memory types) and ISA-extension (Supervisor-mode: page-based memory types) and
@@ -447,8 +447,8 @@ config TOOLCHAIN_HAS_ZBB
config RISCV_ISA_ZBB config RISCV_ISA_ZBB
bool "Zbb extension support for bit manipulation instructions" bool "Zbb extension support for bit manipulation instructions"
depends on TOOLCHAIN_HAS_ZBB depends on TOOLCHAIN_HAS_ZBB
depends on !XIP_KERNEL && MMU depends on MMU
select RISCV_ALTERNATIVE depends on RISCV_ALTERNATIVE
default y default y
help help
Adds support to dynamically detect the presence of the ZBB Adds support to dynamically detect the presence of the ZBB
@@ -462,9 +462,9 @@ config RISCV_ISA_ZBB
config RISCV_ISA_ZICBOM config RISCV_ISA_ZICBOM
bool "Zicbom extension support for non-coherent DMA operation" bool "Zicbom extension support for non-coherent DMA operation"
depends on !XIP_KERNEL && MMU depends on MMU
depends on RISCV_ALTERNATIVE
default y default y
select RISCV_ALTERNATIVE
select RISCV_DMA_NONCOHERENT select RISCV_DMA_NONCOHERENT
help help
Adds support to dynamically detect the presence of the ZICBOM Adds support to dynamically detect the presence of the ZICBOM

6
arch/riscv/Kconfig.errata
View File

@@ -2,8 +2,7 @@ menu "CPU errata selection"
config ERRATA_SIFIVE config ERRATA_SIFIVE
bool "SiFive errata" bool "SiFive errata"
depends on !XIP_KERNEL depends on RISCV_ALTERNATIVE
select RISCV_ALTERNATIVE
help help
All SiFive errata Kconfig depend on this Kconfig. Disabling All SiFive errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all SiFive errata. Please say "Y" this Kconfig will disable all SiFive errata. Please say "Y"
@@ -35,8 +34,7 @@ config ERRATA_SIFIVE_CIP_1200
config ERRATA_THEAD config ERRATA_THEAD
bool "T-HEAD errata" bool "T-HEAD errata"
depends on !XIP_KERNEL depends on RISCV_ALTERNATIVE
select RISCV_ALTERNATIVE
help help
All T-HEAD errata Kconfig depend on this Kconfig. Disabling All T-HEAD errata Kconfig depend on this Kconfig. Disabling
this Kconfig will disable all T-HEAD errata. Please say "Y" this Kconfig will disable all T-HEAD errata. Please say "Y"

50
arch/riscv/include/asm/hwcap.h
View File

@@ -59,18 +59,31 @@ struct riscv_isa_ext_data {
unsigned int isa_ext_id; unsigned int isa_ext_id;
}; };
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
#define riscv_isa_extension_available(isa_bitmap, ext) \
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
static __always_inline bool static __always_inline bool
riscv_has_extension_likely(const unsigned long ext) riscv_has_extension_likely(const unsigned long ext)
{ {
compiletime_assert(ext < RISCV_ISA_EXT_MAX, compiletime_assert(ext < RISCV_ISA_EXT_MAX,
"ext must be < RISCV_ISA_EXT_MAX"); "ext must be < RISCV_ISA_EXT_MAX");
asm_volatile_goto( if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) asm_volatile_goto(
: ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
: [ext] "i" (ext) :
: : [ext] "i" (ext)
: l_no); :
: l_no);
} else {
if (!__riscv_isa_extension_available(NULL, ext))
goto l_no;
}
return true; return true;
l_no: l_no:
@@ -83,26 +96,23 @@ riscv_has_extension_unlikely(const unsigned long ext)
compiletime_assert(ext < RISCV_ISA_EXT_MAX, compiletime_assert(ext < RISCV_ISA_EXT_MAX,
"ext must be < RISCV_ISA_EXT_MAX"); "ext must be < RISCV_ISA_EXT_MAX");
asm_volatile_goto( if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) asm_volatile_goto(
: ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
: [ext] "i" (ext) :
: : [ext] "i" (ext)
: l_yes); :
: l_yes);
} else {
if (__riscv_isa_extension_available(NULL, ext))
goto l_yes;
}
return false; return false;
l_yes: l_yes:
return true; return true;
} }
unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
#define riscv_isa_extension_available(isa_bitmap, ext) \
__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
#endif #endif
#endif /* _ASM_RISCV_HWCAP_H */ #endif /* _ASM_RISCV_HWCAP_H */