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be693ef2a4
Conor Dooley <conor.dooley@microchip.com> says: Here's my attempt at fixing both the use of an FPU on XIP kernels and the issue that Jason ran into where CONFIG_FPU, which needs the alternatives frame work for has_fpu() checks, could be enabled without the alternatives actually being present. For the former, a "slow" fallback that does not use alternatives is added to riscv_has_extension_[un]likely() that can be used with XIP. Obviously, we want to make use of Jisheng's alternatives based approach where possible, so any users of riscv_has_extension_[un]likely() will want to make sure that they select RISCV_ALTERNATIVE. If they don't however, they'll hit the fallback path which (should, sparing a silly mistake from me!) behave in the same way, thus succeeding silently. Sounds like a To prevent "depends on !XIP_KERNEL; select RISCV_ALTERNATIVE" spreading like the plague through the various places that want to check for the presence of extensions, and sidestep the potential silent "success" mentioned above, all users RISCV_ALTERNATIVE are converted from selects to dependencies, with the option being selected for all !XIP_KERNEL builds. I know that the VDSO was a key place that Jisheng wanted to use the new helper rather than static branches, and I think the fallback path should not cause issues there. See the thread at [1] for the prior discussion. 1 - https://lore.kernel.org/linux-riscv/20230128172856.3814-1-jszhang@kernel.org/T/#m21390d570997145d31dd8bb95002fd61f99c6573 [Palmer: these were also merged into fixes, but there's a cleanup that depends on the merge so I'm taking it into for-next as well.] * b4-shazam-merge: RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely() Link: https://lore.kernel.org/r/20230324100538.3514663-1-conor.dooley@microchip.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> * commit '1ee7fc3f4d0a93831a20d5566f203d5ad6d44de8': RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()
119 lines
3.0 KiB
C
119 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copied from arch/arm64/include/asm/hwcap.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_HWCAP_H
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#define _ASM_RISCV_HWCAP_H
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#include <asm/alternative-macros.h>
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#include <asm/errno.h>
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#include <linux/bits.h>
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#include <uapi/asm/hwcap.h>
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#define RISCV_ISA_EXT_a ('a' - 'a')
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#define RISCV_ISA_EXT_c ('c' - 'a')
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#define RISCV_ISA_EXT_d ('d' - 'a')
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#define RISCV_ISA_EXT_f ('f' - 'a')
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#define RISCV_ISA_EXT_h ('h' - 'a')
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#define RISCV_ISA_EXT_i ('i' - 'a')
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#define RISCV_ISA_EXT_m ('m' - 'a')
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#define RISCV_ISA_EXT_s ('s' - 'a')
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#define RISCV_ISA_EXT_u ('u' - 'a')
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/*
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* These macros represent the logical IDs of each multi-letter RISC-V ISA
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* extension and are used in the ISA bitmap. The logical IDs start from
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* RISCV_ISA_EXT_BASE, which allows the 0-25 range to be reserved for single
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* letter extensions. The maximum, RISCV_ISA_EXT_MAX, is defined in order
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* to allocate the bitmap and may be increased when necessary.
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*
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* New extensions should just be added to the bottom, rather than added
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* alphabetically, in order to avoid unnecessary shuffling.
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*/
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#define RISCV_ISA_EXT_BASE 26
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#define RISCV_ISA_EXT_SSCOFPMF 26
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#define RISCV_ISA_EXT_SSTC 27
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#define RISCV_ISA_EXT_SVINVAL 28
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#define RISCV_ISA_EXT_SVPBMT 29
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#define RISCV_ISA_EXT_ZBB 30
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#define RISCV_ISA_EXT_ZICBOM 31
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#define RISCV_ISA_EXT_ZIHINTPAUSE 32
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#define RISCV_ISA_EXT_SVNAPOT 33
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#define RISCV_ISA_EXT_ZICBOZ 34
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#define RISCV_ISA_EXT_MAX 64
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#define RISCV_ISA_EXT_NAME_LEN_MAX 32
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#ifndef __ASSEMBLY__
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#include <linux/jump_label.h>
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struct riscv_isa_ext_data {
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/* Name of the extension displayed to userspace via /proc/cpuinfo */
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char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
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/* The logical ISA extension ID */
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unsigned int isa_ext_id;
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};
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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static __always_inline bool
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riscv_has_extension_likely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_no);
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} else {
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if (!__riscv_isa_extension_available(NULL, ext))
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goto l_no;
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}
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return true;
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l_no:
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return false;
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}
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static __always_inline bool
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riscv_has_extension_unlikely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_yes);
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} else {
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if (__riscv_isa_extension_available(NULL, ext))
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goto l_yes;
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}
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return false;
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l_yes:
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return true;
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}
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#endif
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#endif /* _ASM_RISCV_HWCAP_H */
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