ich777/linux_media
1
0
Fork 0
mirror of https://github.com/tbsdtv/linux_media.git synced 2025-07-23 12:43:29 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Browse Source 
Pull more clk updates from Stephen Boyd:
 "Another set of clk driver updates and fixes for the merge window. The
  driver updates needed more time to bake in linux-next.

  Updates:
   - Support for more clk controllers in Qualcomm SoCs such as SM8350,
     SM8450, SDX75, SC8280XP, and IPQ9574
   - Runtime PM enablement of some more Qualcomm clk controllers
   - Various fixes to Qualcomm clk driver data to use correct clk_ops
     and to check halt bits properly
   - AT91 updates to modernize with clk_parent_data structures

  Fixes:
   - Remove 'syscon' from dt binding fix for ti,j721e-system-controller
   - Fix determine rate in the Tegra driver that got wrecked by the
     refactorting of muxes this merge window"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (69 commits)
  clk: tegra: Avoid calling an uninitialized function
  dt-bindings: mfd: ti,j721e-system-controller: Remove syscon from example
  clk: at91: sama7g5: s/ep_chg_chg_id/ep_chg_id
  clk: at91: sama7g5: switch to parent_hw and parent_data
  clk: at91: sckc: switch to parent_data/parent_hw
  clk: at91: clk-sam9x60-pll: add support for parent_hw
  clk: at91: clk-utmi: add support for parent_hw
  clk: at91: clk-system: add support for parent_hw
  clk: at91: clk-programmable: add support for parent_hw
  clk: at91: clk-peripheral: add support for parent_hw
  clk: at91: clk-master: add support for parent_hw
  clk: at91: clk-generated: add support for parent_hw
  clk: at91: clk-main: add support for parent_data/parent_hw
  clk: qcom: gcc-sc8280xp: Add runtime PM
  clk: qcom: gpucc-sc8280xp: Add runtime PM
  clk: qcom: mmcc-msm8974: fix MDSS_GDSC power flags
  clk: qcom: gpucc-sm6375: Enable runtime pm
  dt-bindings: clock: sm6375-gpucc: Add VDD_GX
  clk: qcom: gcc-sm6115: Add missing PLL config properties
  clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)
  ...
This commit is contained in:
Linus Torvalds
2023-07-04 11:07:45 -07:00
parent 406fb9eb19 f679e89acd
commit b869e9f499
69 changed files with 7623 additions and 870 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@@ -19,6 +19,7 @@ properties:
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,ipq9574-a73pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll

73
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml Normal file
View File

@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8953
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
- Sireesh Kodali <sireeshkodali@protonmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8953.
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
properties:
compatible:
const: qcom,gcc-msm8953
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
clock-names:
items:
- const: xo
- const: sleep
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@1800000 {
compatible = "qcom,gcc-msm8953";
reg = <0x01800000 0x80000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
<&dsi1_phy 1>,
<&dsi1_phy 0>;
clock-names = "xo",
"sleep",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
"dsi1pllbyte";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

1
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
View File

@@ -30,7 +30,6 @@ properties:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8953
- qcom,gcc-mdm9615
required:

7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View File

@@ -32,6 +32,10 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
@@ -45,6 +49,8 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7180";
reg = <0x00100000 0x1f0000>;
@@ -52,6 +58,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd SC7180_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
View File

@@ -43,6 +43,10 @@ properties:
- const: ufs_phy_tx_symbol_0_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
@@ -56,6 +60,8 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0x00100000 0x1f0000>;
@@ -71,6 +77,7 @@ examples:
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
power-domains = <&rpmhpd SC7280_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

5
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View File

@@ -23,11 +23,13 @@ properties:
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
required:
@@ -47,8 +49,9 @@ examples:
compatible = "qcom,gcc-sm8250";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

3
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View File

@@ -50,6 +50,9 @@ properties:
- const: gcc_gpu_gpll0_clk_src
- const: gcc_gpu_gpll0_div_clk_src
power-domains:
maxItems: 1
'#clock-cells':
const: 1

1
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
View File

@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ9574
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Anusha Rao <quic_anusha@quicinc.com>
description: |

32
Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
View File

@@ -31,11 +31,11 @@ properties:
- qcom,mmcc-sdm660
clocks:
minItems: 8
minItems: 7
maxItems: 13
clock-names:
minItems: 8
minItems: 7
maxItems: 13
'#clock-cells':
@@ -99,6 +99,34 @@ allOf:
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8226
then:
properties:
clocks:
items:
- description: Board XO source
- description: MMSS GPLL0 voted clock
- description: GPLL0 voted clock
- description: GPLL1 voted clock
- description: GFX3D clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
clock-names:
items:
- const: xo
- const: mmss_gpll0_vote
- const: gpll0_vote
- const: gpll1_vote
- const: gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- if:
properties:
compatible:

1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
View File

@@ -27,6 +27,7 @@ properties:
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk

15
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml
View File

@@ -27,9 +27,21 @@ properties:
- description: GPLL0 div branch source
- description: SNoC DVM GFX source
power-domains:
description:
A phandle and PM domain specifier for the VDD_GX power rail
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required VDD_GX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
@@ -40,6 +52,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
soc {
#address-cells = <2>;
@@ -52,6 +65,8 @@ examples:
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
power-domains = <&rpmpd SM6375_VDDGX>;
required-opps = <&rpmpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

68
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml Normal file
View File

@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 Video Clock & Reset Controller
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,videocc-sm8350.h
include/dt-bindings/reset/qcom,videocc-sm8350.h
properties:
compatible:
const: qcom,sm8350-videocc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Board sleep clock
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@abf0000 {
compatible = "qcom,sm8350-videocc";
reg = <0x0abf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8350_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

4
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -17,7 +17,9 @@ description: |
properties:
compatible:
const: qcom,sm8450-videocc
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
reg:
maxItems: 1

2
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
View File

@@ -101,7 +101,7 @@ examples:
};
clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};