mirror of
https://github.com/tbsdtv/linux_media.git
synced 2025-07-22 20:30:58 +02:00
2aae5eaa94
SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
69 lines
1.6 KiB
YAML
69 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm SM8350 Video Clock & Reset Controller
|
|
|
|
maintainers:
|
|
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
|
|
|
description: |
|
|
Qualcomm video clock control module provides the clocks, resets and power
|
|
domains on Qualcomm SoCs.
|
|
|
|
See also::
|
|
include/dt-bindings/clock/qcom,videocc-sm8350.h
|
|
include/dt-bindings/reset/qcom,videocc-sm8350.h
|
|
|
|
properties:
|
|
compatible:
|
|
const: qcom,sm8350-videocc
|
|
|
|
clocks:
|
|
items:
|
|
- description: Board XO source
|
|
- description: Board active XO source
|
|
- description: Board sleep clock
|
|
|
|
power-domains:
|
|
description:
|
|
A phandle and PM domain specifier for the MMCX power domain.
|
|
maxItems: 1
|
|
|
|
required-opps:
|
|
description:
|
|
A phandle to an OPP node describing required MMCX performance point.
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- power-domains
|
|
- required-opps
|
|
|
|
allOf:
|
|
- $ref: qcom,gcc.yaml#
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/power/qcom-rpmpd.h>
|
|
|
|
clock-controller@abf0000 {
|
|
compatible = "qcom,sm8350-videocc";
|
|
reg = <0x0abf0000 0x10000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
power-domains = <&rpmhpd SM8350_MMCX>;
|
|
required-opps = <&rpmhpd_opp_low_svs>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
...
|