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dt-bindings: clock: Add LPASS AUDIOCC and reset controller for SC8280XP
The LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608125315.11454-3-srinivas.kandagatla@linaro.org
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committed by
Bjorn Andersson
parent
bfc43a9c0c
commit
83da70da40
@@ -19,6 +19,7 @@ description: |
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-lpassaudiocc
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- qcom,sc8280xp-lpasscc
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reg:
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@@ -39,6 +40,15 @@ required:
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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lpass_audiocc: clock-controller@32a9000 {
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compatible = "qcom,sc8280xp-lpassaudiocc";
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reg = <0x032a9000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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- |
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#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
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lpasscc: clock-controller@33e0000 {
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@@ -6,6 +6,11 @@
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
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#define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H
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/* LPASS AUDIO CC CSR */
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#define LPASS_AUDIO_SWR_RX_CGCR 0
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#define LPASS_AUDIO_SWR_WSA_CGCR 1
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#define LPASS_AUDIO_SWR_WSA2_CGCR 2
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/* LPASS TCSR */
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#define LPASS_AUDIO_SWR_TX_CGCR 0
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