CyrIng d2fd467fdf [AMD][Zen5] Introduced a UMC capabilities decoder for STX families

2025-07-16 04:46:04 +02:00

..

amd_reg.h

[AMD][Raphael] Attempt to read the SoC voltage

2025-05-31 11:46:19 +02:00

bitasm.h

[AMD] Improved EPYC Genoa support

2025-05-09 19:44:16 +02:00

corefreq-api.h

[AMD][Zen5/Strix Halo] Probe Memory Controller from DID 0x12b8

2025-07-10 11:21:01 +02:00

corefreq-cli-extra.c

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq-cli-extra.h

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq-cli-json.c

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq-cli-json.h

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq-cli-rsc-en.h

[UI] Rephrased string for the CPUID.80000001.ECX[27] feature

2025-06-21 12:31:59 +02:00

corefreq-cli-rsc-fr.h

[UI] Rephrased string for the CPUID.80000001.ECX[27] feature

2025-06-21 12:31:59 +02:00

corefreq-cli-rsc-theme-dflt.h

[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots

2025-05-03 16:42:40 +02:00

corefreq-cli-rsc-theme-usr1.h

[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots

2025-05-03 16:42:40 +02:00

corefreq-cli-rsc-theme-usr2.h

[x86_64] SMBIOS dump resized to 12 channels multiplied 4 DIMM slots

2025-05-03 16:42:40 +02:00

corefreq-cli-rsc.c

[UI] Optimize POWERED() macro with branchless 3-state array lookup

2025-06-21 10:55:45 +02:00

corefreq-cli-rsc.h

[UI] Optimize POWERED() macro with branchless 3-state array lookup

2025-06-21 10:55:45 +02:00

corefreq-cli.c

[UI] Optimize POWERED() macro with branchless 3-state array lookup

2025-06-21 10:55:45 +02:00

corefreq-cli.h

[CR] In _F4() cast complement mask to the type of bit argument

2025-06-21 19:27:41 +02:00

corefreq-ui.c

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq-ui.h

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreq.h

[AMD][Genoa] Accumulate the power consumed by RAM

2025-05-04 18:22:35 +02:00

corefreqd.c

[AMD][Zen5] Introduced a UMC capabilities decoder for STX families

2025-07-16 04:46:04 +02:00

corefreqk.c

[AMD][Zen5][STX/KRK/STXH] Avoid undefined COF and Power registers

2025-07-13 09:19:17 +02:00

corefreqk.h

[AMD][Zen5][STX/KRK/STXH] Avoid undefined COF and Power registers

2025-07-13 09:19:17 +02:00

corefreqm.c

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

corefreqm.h

Copyright (C) 2015-2025 CYRIL COURTIAT

2025-01-19 13:15:05 +01:00

coretypes.h

[Intel] Added the Bartlett Lake/S entry

2025-05-26 13:44:53 +02:00

intel_reg.h

[Code Review] Intel Core Ultra: Registers name and address updated

2025-05-18 12:30:34 +02:00