mirror of
https://github.com/cyring/CoreFreq.git
synced 2025-07-23 12:13:07 +02:00
slab fixed: per CPU memory cache allocation.
This commit is contained in:
Cyril Courtiat
541
intelfreq.c
541
intelfreq.c
@@ -195,12 +195,13 @@ void Proc_Features(FEATURES *features)
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{
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__asm__ volatile
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(
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"cpuid \n\t"
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"and $0x100, %%rdx \n\t"
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"shr $8, %%rdx"
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"cpuid"
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: "=d" (features->InvariantTSC)
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: "a" (0x80000007)
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);
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features->InvariantTSC &= 0x100;
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features->InvariantTSC >>= 8;
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__asm__ volatile
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(
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"cpuid"
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@@ -211,38 +212,7 @@ void Proc_Features(FEATURES *features)
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}
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Proc_Brand(features->Brand);
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}
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/*
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void Copy_Features(FEATURES *dest, FEATURES *src)
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{
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dest->Std.AX=src->Std.AX;
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dest->Std.BX=src->Std.BX;
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dest->Std.CX=src->Std.CX;
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dest->Std.DX=src->Std.DX;
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dest->MONITOR_MWAIT_Leaf.AX=src->MONITOR_MWAIT_Leaf.AX;
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dest->MONITOR_MWAIT_Leaf.BX=src->MONITOR_MWAIT_Leaf.BX;
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dest->MONITOR_MWAIT_Leaf.CX=src->MONITOR_MWAIT_Leaf.CX;
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dest->MONITOR_MWAIT_Leaf.DX=src->MONITOR_MWAIT_Leaf.DX;
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dest->Thermal_Power_Leaf.AX=src->Thermal_Power_Leaf.AX;
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dest->Thermal_Power_Leaf.BX=src->Thermal_Power_Leaf.BX;
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dest->Thermal_Power_Leaf.CX=src->Thermal_Power_Leaf.CX;
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dest->Thermal_Power_Leaf.DX=src->Thermal_Power_Leaf.DX;
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dest->Perf_Monitoring_Leaf.AX=src->Perf_Monitoring_Leaf.AX;
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dest->Perf_Monitoring_Leaf.BX=src->Perf_Monitoring_Leaf.BX;
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dest->Perf_Monitoring_Leaf.CX=src->Perf_Monitoring_Leaf.CX;
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dest->Perf_Monitoring_Leaf.DX=src->Perf_Monitoring_Leaf.DX;
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dest->ExtFeature.AX=src->ExtFeature.AX;
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dest->ExtFeature.BX=src->ExtFeature.BX;
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dest->ExtFeature.CX=src->ExtFeature.CX;
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dest->ExtFeature.DX=src->ExtFeature.DX;
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dest->LargestExtFunc=src->LargestExtFunc;
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dest->ExtFunc.CX=src->ExtFunc.CX;
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dest->ExtFunc.DX=src->ExtFunc.DX;
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dest->InvariantTSC=src->InvariantTSC;
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dest->HTT_enabled=src->HTT_enabled;
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// MOVSB(dest->VendorID, src->VendorID, 16);
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// MOVSB(dest->Brand, src->Brand, 48+1);
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}
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*/
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CLOCK Proc_Clock(unsigned int ratio)
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{
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unsigned long long TSC[2];
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@@ -319,10 +289,6 @@ signed int Read_APIC(void *arg)
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SMT_Select_Mask = ~((-1) << SMT_Mask_Width);
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Core->T.ThreadID= ExtTopology.DX.x2ApicID \
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& SMT_Select_Mask;
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if((Core->T.ThreadID > 0)
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&& !Proc->Features.HTT_enabled)
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Proc->Features.HTT_enabled=1;
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}
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break;
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case LEVEL_CORE:
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@@ -355,6 +321,9 @@ unsigned int Proc_Topology(void)
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for(cpu=0; cpu < Proc->CPU.Count; cpu++)
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{
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Proc->Core[cpu]->T.ApicID=-1;
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Proc->Core[cpu]->T.CoreID=-1;
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Proc->Core[cpu]->T.ThreadID=-1;
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if(!Proc->Core[cpu]->OffLine)
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{
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Proc->Core[cpu]->TID[APIC_TID]= \
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@@ -370,24 +339,22 @@ unsigned int Proc_Topology(void)
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}
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CountEnabledCPU++;
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}
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else
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{
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Proc->Core[cpu]->T.ApicID=-1;
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Proc->Core[cpu]->T.CoreID=-1;
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Proc->Core[cpu]->T.ThreadID=-1;
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}
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}
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for(cpu=0; cpu < Proc->CPU.Count; cpu++)
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if(!Proc->Core[cpu]->OffLine
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&& !IS_ERR(Proc->Core[cpu]->TID[APIC_TID]))
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{
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kthread_stop(Proc->Core[cpu]->TID[APIC_TID]);
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if(!Proc->Features.HTT_enabled
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&& (Proc->Core[cpu]->T.ThreadID > 0))
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Proc->Features.HTT_enabled=1;
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}
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return(CountEnabledCPU);
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}
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void Counters_Set(unsigned int cpu)
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void Counters_Set(CORE *Core)
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{
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GLOBAL_PERF_COUNTER GlobalPerfCounter={0};
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FIXED_PERF_COUNTER FixedPerfCounter={0};
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@@ -396,7 +363,7 @@ void Counters_Set(unsigned int cpu)
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RDMSR(GlobalPerfCounter, MSR_CORE_PERF_GLOBAL_CTRL);
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Proc->Core[cpu]->SaveArea.GlobalPerfCounter=GlobalPerfCounter;
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Core->SaveArea.GlobalPerfCounter=GlobalPerfCounter;
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GlobalPerfCounter.EN_FIXED_CTR0=1;
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GlobalPerfCounter.EN_FIXED_CTR1=1;
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GlobalPerfCounter.EN_FIXED_CTR2=1;
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@@ -405,7 +372,7 @@ void Counters_Set(unsigned int cpu)
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RDMSR(FixedPerfCounter, MSR_CORE_PERF_FIXED_CTR_CTRL);
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Proc->Core[cpu]->SaveArea.FixedPerfCounter=FixedPerfCounter;
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Core->SaveArea.FixedPerfCounter=FixedPerfCounter;
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FixedPerfCounter.EN0_OS=1;
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FixedPerfCounter.EN1_OS=1;
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FixedPerfCounter.EN2_OS=1;
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@@ -439,114 +406,114 @@ void Counters_Set(unsigned int cpu)
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WRMSR(OvfControl, MSR_CORE_PERF_GLOBAL_OVF_CTRL);
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}
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void Counters_Clear(unsigned int cpu)
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void Counters_Clear(CORE *Core)
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{
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WRMSR( Proc->Core[cpu]->SaveArea.FixedPerfCounter,
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WRMSR( Core->SaveArea.FixedPerfCounter,
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MSR_CORE_PERF_FIXED_CTR_CTRL);
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WRMSR( Proc->Core[cpu]->SaveArea.GlobalPerfCounter,
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WRMSR( Core->SaveArea.GlobalPerfCounter,
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MSR_CORE_PERF_GLOBAL_CTRL);
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}
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void Counters_Genuine(unsigned int cpu, unsigned int T)
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void Counters_Genuine(CORE *Core, unsigned int T)
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{
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// Actual & Maximum Performance Frequency Clock counters.
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RDCNT(Proc->Core[cpu]->Counter[T].C0.UCC, MSR_IA32_APERF);
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RDCNT(Proc->Core[cpu]->Counter[T].C0.URC, MSR_IA32_MPERF);
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RDCNT(Core->Counter[T].C0.UCC, MSR_IA32_APERF);
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RDCNT(Core->Counter[T].C0.URC, MSR_IA32_MPERF);
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// TSC in relation to the Core.
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RDCNT(Proc->Core[cpu]->Counter[T].TSC, MSR_IA32_TSC);
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RDCNT(Core->Counter[T].TSC, MSR_IA32_TSC);
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// Derive C1
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Proc->Core[cpu]->Counter[T].C1= \
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(Proc->Core[cpu]->Counter[T].TSC > Proc->Core[cpu]->Counter[T].C0.URC)?\
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Proc->Core[cpu]->Counter[T].TSC - Proc->Core[cpu]->Counter[T].C0.URC \
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Core->Counter[T].C1= \
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(Core->Counter[T].TSC > Core->Counter[T].C0.URC)?\
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Core->Counter[T].TSC - Core->Counter[T].C0.URC \
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: 0;
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}
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void Counters_Core2(unsigned int cpu, unsigned int T)
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void Counters_Core2(CORE *Core, unsigned int T)
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{
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// Instructions Retired
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RDCNT(Proc->Core[cpu]->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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RDCNT(Core->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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// Unhalted Core & Reference Cycles.
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RDCNT(Proc->Core[cpu]->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Proc->Core[cpu]->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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RDCNT(Core->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Core->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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// TSC in relation to the Logical Core.
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RDCNT(Proc->Core[cpu]->Counter[T].TSC, MSR_IA32_TSC);
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RDCNT(Core->Counter[T].TSC, MSR_IA32_TSC);
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// Derive C1
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Proc->Core[cpu]->Counter[T].C1= \
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(Proc->Core[cpu]->Counter[T].TSC > Proc->Core[cpu]->Counter[T].C0.URC)?\
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Proc->Core[cpu]->Counter[T].TSC - Proc->Core[cpu]->Counter[T].C0.URC \
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Core->Counter[T].C1= \
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(Core->Counter[T].TSC > Core->Counter[T].C0.URC)?\
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Core->Counter[T].TSC - Core->Counter[T].C0.URC \
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: 0;
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}
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void Counters_Nehalem(unsigned int cpu, unsigned int T)
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void Counters_Nehalem(CORE *Core, unsigned int T)
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{
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register unsigned long long Cx=0;
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// Instructions Retired
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RDCNT(Proc->Core[cpu]->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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RDCNT(Core->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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// Unhalted Core & Reference Cycles.
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RDCNT(Proc->Core[cpu]->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Proc->Core[cpu]->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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RDCNT(Core->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Core->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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// TSC in relation to the Logical Core.
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RDCNT(Proc->Core[cpu]->Counter[T].TSC, MSR_IA32_TSC);
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RDCNT(Core->Counter[T].TSC, MSR_IA32_TSC);
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// C-States.
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RDCNT(Proc->Core[cpu]->Counter[T].C3, MSR_CORE_C3_RESIDENCY);
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RDCNT(Proc->Core[cpu]->Counter[T].C6, MSR_CORE_C6_RESIDENCY);
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RDCNT(Core->Counter[T].C3, MSR_CORE_C3_RESIDENCY);
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RDCNT(Core->Counter[T].C6, MSR_CORE_C6_RESIDENCY);
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// Derive C1
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Cx= Proc->Core[cpu]->Counter[T].C6 \
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+ Proc->Core[cpu]->Counter[T].C3 \
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+ Proc->Core[cpu]->Counter[T].C0.URC;
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Cx= Core->Counter[T].C6 \
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+ Core->Counter[T].C3 \
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+ Core->Counter[T].C0.URC;
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Proc->Core[cpu]->Counter[T].C1= \
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(Proc->Core[cpu]->Counter[T].TSC > Cx) ? \
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Proc->Core[cpu]->Counter[T].TSC - Cx \
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Core->Counter[T].C1= \
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(Core->Counter[T].TSC > Cx) ? \
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Core->Counter[T].TSC - Cx \
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: 0;
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}
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void Counters_SandyBridge(unsigned int cpu, unsigned int T)
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void Counters_SandyBridge(CORE *Core, unsigned int T)
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{
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register unsigned long long Cx=0;
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// Instructions Retired
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RDCNT(Proc->Core[cpu]->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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RDCNT(Core->Counter[T].INST, MSR_CORE_PERF_FIXED_CTR0);
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// Unhalted Core & Reference Cycles.
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RDCNT(Proc->Core[cpu]->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Proc->Core[cpu]->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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RDCNT(Core->Counter[T].C0.UCC, MSR_CORE_PERF_FIXED_CTR1);
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RDCNT(Core->Counter[T].C0.URC, MSR_CORE_PERF_FIXED_CTR2);
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// TSC in relation to the Logical Core.
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RDCNT(Proc->Core[cpu]->Counter[T].TSC, MSR_IA32_TSC);
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RDCNT(Core->Counter[T].TSC, MSR_IA32_TSC);
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// C-States.
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RDCNT(Proc->Core[cpu]->Counter[T].C3, MSR_CORE_C3_RESIDENCY);
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RDCNT(Proc->Core[cpu]->Counter[T].C6, MSR_CORE_C6_RESIDENCY);
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RDCNT(Proc->Core[cpu]->Counter[T].C7, MSR_CORE_C7_RESIDENCY);
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RDCNT(Core->Counter[T].C3, MSR_CORE_C3_RESIDENCY);
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RDCNT(Core->Counter[T].C6, MSR_CORE_C6_RESIDENCY);
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RDCNT(Core->Counter[T].C7, MSR_CORE_C7_RESIDENCY);
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// Derive C1
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Cx= Proc->Core[cpu]->Counter[T].C7 \
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+ Proc->Core[cpu]->Counter[T].C6 \
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+ Proc->Core[cpu]->Counter[T].C3 \
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+ Proc->Core[cpu]->Counter[T].C0.URC;
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Cx= Core->Counter[T].C7 \
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+ Core->Counter[T].C6 \
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+ Core->Counter[T].C3 \
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+ Core->Counter[T].C0.URC;
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Proc->Core[cpu]->Counter[T].C1= \
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(Proc->Core[cpu]->Counter[T].TSC > Cx) ? \
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Proc->Core[cpu]->Counter[T].TSC - Cx \
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Core->Counter[T].C1= \
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(Core->Counter[T].TSC > Cx) ? \
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Core->Counter[T].TSC - Cx \
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: 0;
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}
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void Core_Temp(unsigned int cpu)
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void Core_Temp(CORE *Core)
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{
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RDMSR(Proc->Core[cpu]->TjMax, MSR_IA32_TEMPERATURE_TARGET);
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RDMSR(Proc->Core[cpu]->ThermStat, MSR_IA32_THERM_STATUS);
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RDMSR(Core->TjMax, MSR_IA32_TEMPERATURE_TARGET);
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RDMSR(Core->ThermStat, MSR_IA32_THERM_STATUS);
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}
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int Cycle_Genuine(void *arg)
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@@ -554,10 +521,10 @@ int Cycle_Genuine(void *arg)
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if(arg != NULL)
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{
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CORE *Core=(CORE *) arg;
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unsigned int cpu=Core->Bind;
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// unsigned int cpu=Core->Bind;
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unsigned int leave=0, down=0, steps=Proc->msleep / 100;
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Counters_Genuine(cpu, 0);
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Counters_Genuine(Core, 0);
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while(!leave)
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{
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@@ -569,49 +536,49 @@ int Cycle_Genuine(void *arg)
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leave=1;
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} while(--down && !leave);
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Counters_Genuine(cpu, 1);
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Core_Temp(cpu);
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Counters_Genuine(Core, 1);
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Core_Temp(Core);
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// Absolute Delta of Unhalted (Core & Ref) C0 Counter.
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Proc->Core[cpu]->Delta.C0.UCC= \
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(Proc->Core[cpu]->Counter[0].C0.UCC > \
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Proc->Core[cpu]->Counter[1].C0.UCC) ? \
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Proc->Core[cpu]->Counter[0].C0.UCC \
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- Proc->Core[cpu]->Counter[1].C0.UCC \
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: Proc->Core[cpu]->Counter[1].C0.UCC \
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- Proc->Core[cpu]->Counter[0].C0.UCC;
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Core->Delta.C0.UCC= \
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(Core->Counter[0].C0.UCC > \
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Core->Counter[1].C0.UCC) ? \
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Core->Counter[0].C0.UCC \
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- Core->Counter[1].C0.UCC \
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: Core->Counter[1].C0.UCC \
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- Core->Counter[0].C0.UCC;
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Proc->Core[cpu]->Delta.C0.URC= \
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Proc->Core[cpu]->Counter[1].C0.URC \
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- Proc->Core[cpu]->Counter[0].C0.URC;
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Core->Delta.C0.URC= \
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Core->Counter[1].C0.URC \
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- Core->Counter[0].C0.URC;
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Proc->Core[cpu]->Delta.TSC= \
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Proc->Core[cpu]->Counter[1].TSC \
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- Proc->Core[cpu]->Counter[0].TSC;
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Core->Delta.TSC= \
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Core->Counter[1].TSC \
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- Core->Counter[0].TSC;
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Proc->Core[cpu]->Delta.C1= \
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(Proc->Core[cpu]->Counter[0].C1 > \
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Proc->Core[cpu]->Counter[1].C1) ? \
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Proc->Core[cpu]->Counter[0].C1 \
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- Proc->Core[cpu]->Counter[1].C1 \
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: Proc->Core[cpu]->Counter[1].C1 \
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- Proc->Core[cpu]->Counter[0].C1;
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Core->Delta.C1= \
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(Core->Counter[0].C1 > \
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Core->Counter[1].C1) ? \
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Core->Counter[0].C1 \
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- Core->Counter[1].C1 \
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: Core->Counter[1].C1 \
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- Core->Counter[0].C1;
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// Save TSC.
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Proc->Core[cpu]->Counter[0].TSC= \
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Proc->Core[cpu]->Counter[1].TSC;
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Core->Counter[0].TSC= \
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Core->Counter[1].TSC;
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// Save the Unhalted Core & Reference Counter
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// for next iteration.
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Proc->Core[cpu]->Counter[0].C0.UCC= \
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Proc->Core[cpu]->Counter[1].C0.UCC;
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Proc->Core[cpu]->Counter[1].C0.URC= \
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Proc->Core[cpu]->Counter[1].C0.URC;
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Core->Counter[0].C0.UCC= \
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Core->Counter[1].C0.UCC;
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Core->Counter[1].C0.URC= \
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Core->Counter[1].C0.URC;
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Proc->Core[cpu]->Counter[0].C1= \
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Proc->Core[cpu]->Counter[1].C1;
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Core->Counter[0].C1= \
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Core->Counter[1].C1;
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atomic_store(&Proc->Core[cpu]->Sync, 0x1);
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atomic_store(&Core->Sync, 0x1);
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}
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}
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do_exit(0);
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||||
@@ -635,14 +602,14 @@ void Arch_Genuine(unsigned int stage)
|
||||
RDMSR(Platform, MSR_NHM_PLATFORM_INFO);
|
||||
RDMSR(Turbo, MSR_NHM_TURBO_RATIO_LIMIT);
|
||||
|
||||
if(Platform.qword != 0)
|
||||
if(Platform.value != 0)
|
||||
{
|
||||
Proc->Boost[0]=MINCNT(Platform.MinimumRatio, \
|
||||
Platform.MaxNonTurboRatio);
|
||||
Proc->Boost[1]=MAXCNT(Platform.MinimumRatio, \
|
||||
Platform.MaxNonTurboRatio);
|
||||
}
|
||||
if(Turbo.qword != 0)
|
||||
if(Turbo.value != 0)
|
||||
{
|
||||
Proc->Boost[2]=Turbo.MaxRatio_8C;
|
||||
Proc->Boost[3]=Turbo.MaxRatio_7C;
|
||||
@@ -693,11 +660,11 @@ int Cycle_Core2(void *arg)
|
||||
if(arg != NULL)
|
||||
{
|
||||
CORE *Core=(CORE *) arg;
|
||||
unsigned int cpu=Core->Bind;
|
||||
// unsigned int cpu=Core->Bind;
|
||||
unsigned int leave=0, down=0, steps=Proc->msleep / 100;
|
||||
|
||||
Counters_Set(cpu);
|
||||
Counters_Core2(cpu, 0);
|
||||
Counters_Set(Core);
|
||||
Counters_Core2(Core, 0);
|
||||
|
||||
while(!leave)
|
||||
{
|
||||
@@ -709,60 +676,60 @@ int Cycle_Core2(void *arg)
|
||||
leave=1;
|
||||
} while(--down && !leave);
|
||||
|
||||
Counters_Core2(cpu, 1);
|
||||
Core_Temp(cpu);
|
||||
Counters_Core2(Core, 1);
|
||||
Core_Temp(Core);
|
||||
|
||||
// Delta of Instructions Retired
|
||||
Proc->Core[cpu]->Delta.INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST \
|
||||
- Proc->Core[cpu]->Counter[0].INST;
|
||||
Core->Delta.INST= \
|
||||
Core->Counter[1].INST \
|
||||
- Core->Counter[0].INST;
|
||||
|
||||
// Absolute Delta of Unhalted (Core & Ref) C0 Counter.
|
||||
Proc->Core[cpu]->Delta.C0.UCC= \
|
||||
(Proc->Core[cpu]->Counter[0].C0.UCC > \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC) ? \
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
: Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.UCC;
|
||||
Core->Delta.C0.UCC= \
|
||||
(Core->Counter[0].C0.UCC > \
|
||||
Core->Counter[1].C0.UCC) ? \
|
||||
Core->Counter[0].C0.UCC \
|
||||
- Core->Counter[1].C0.UCC \
|
||||
: Core->Counter[1].C0.UCC \
|
||||
- Core->Counter[0].C0.UCC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.URC;
|
||||
Core->Delta.C0.URC= \
|
||||
Core->Counter[1].C0.URC \
|
||||
- Core->Counter[0].C0.URC;
|
||||
|
||||
Proc->Core[cpu]->Delta.TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC \
|
||||
- Proc->Core[cpu]->Counter[0].TSC;
|
||||
Core->Delta.TSC= \
|
||||
Core->Counter[1].TSC \
|
||||
- Core->Counter[0].TSC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C1= \
|
||||
(Proc->Core[cpu]->Counter[0].C1 > \
|
||||
Proc->Core[cpu]->Counter[1].C1) ? \
|
||||
Proc->Core[cpu]->Counter[0].C1 \
|
||||
- Proc->Core[cpu]->Counter[1].C1 \
|
||||
: Proc->Core[cpu]->Counter[1].C1 \
|
||||
- Proc->Core[cpu]->Counter[0].C1;
|
||||
Core->Delta.C1= \
|
||||
(Core->Counter[0].C1 > \
|
||||
Core->Counter[1].C1) ? \
|
||||
Core->Counter[0].C1 \
|
||||
- Core->Counter[1].C1 \
|
||||
: Core->Counter[1].C1 \
|
||||
- Core->Counter[0].C1;
|
||||
|
||||
// Save the Instructions counter.
|
||||
Proc->Core[cpu]->Counter[0].INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST;
|
||||
Core->Counter[0].INST= \
|
||||
Core->Counter[1].INST;
|
||||
|
||||
// Save TSC.
|
||||
Proc->Core[cpu]->Counter[0].TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC;
|
||||
Core->Counter[0].TSC= \
|
||||
Core->Counter[1].TSC;
|
||||
|
||||
// Save the Unhalted Core & Reference Counter
|
||||
// for next iteration.
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC;
|
||||
Proc->Core[cpu]->Counter[1].C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC;
|
||||
Core->Counter[0].C0.UCC= \
|
||||
Core->Counter[1].C0.UCC;
|
||||
Core->Counter[1].C0.URC= \
|
||||
Core->Counter[1].C0.URC;
|
||||
|
||||
Proc->Core[cpu]->Counter[0].C1= \
|
||||
Proc->Core[cpu]->Counter[1].C1;
|
||||
Core->Counter[0].C1= \
|
||||
Core->Counter[1].C1;
|
||||
|
||||
atomic_store(&Proc->Core[cpu]->Sync, 0x1);
|
||||
atomic_store(&Core->Sync, 0x1);
|
||||
}
|
||||
Counters_Clear(cpu);
|
||||
Counters_Clear(Core);
|
||||
}
|
||||
do_exit(0);
|
||||
}
|
||||
@@ -785,14 +752,14 @@ void Arch_Core2(unsigned int stage)
|
||||
RDMSR(Platform, MSR_NHM_PLATFORM_INFO);
|
||||
RDMSR(Turbo, MSR_NHM_TURBO_RATIO_LIMIT);
|
||||
|
||||
if(Platform.qword != 0)
|
||||
if(Platform.value != 0)
|
||||
{
|
||||
Proc->Boost[0]=MINCNT(Platform.MinimumRatio, \
|
||||
Platform.MaxNonTurboRatio);
|
||||
Proc->Boost[1]=MAXCNT(Platform.MinimumRatio, \
|
||||
Platform.MaxNonTurboRatio);
|
||||
}
|
||||
if(Turbo.qword != 0)
|
||||
if(Turbo.value != 0)
|
||||
{
|
||||
Proc->Boost[2]=Turbo.MaxRatio_8C;
|
||||
Proc->Boost[3]=Turbo.MaxRatio_7C;
|
||||
@@ -843,11 +810,11 @@ int Cycle_Nehalem(void *arg)
|
||||
if(arg != NULL)
|
||||
{
|
||||
CORE *Core=(CORE *) arg;
|
||||
unsigned int cpu=Core->Bind;
|
||||
// unsigned int cpu=Core->Bind;
|
||||
unsigned int leave=0, down=0, steps=Proc->msleep / 100;
|
||||
|
||||
Counters_Set(cpu);
|
||||
Counters_Nehalem(cpu, 0);
|
||||
Counters_Set(Core);
|
||||
Counters_Nehalem(Core, 0);
|
||||
|
||||
while(!leave)
|
||||
{
|
||||
@@ -859,72 +826,72 @@ int Cycle_Nehalem(void *arg)
|
||||
leave=1;
|
||||
} while(--down && !leave);
|
||||
|
||||
Counters_Nehalem(cpu, 1);
|
||||
Core_Temp(cpu);
|
||||
Counters_Nehalem(Core, 1);
|
||||
Core_Temp(Core);
|
||||
|
||||
// Delta of Instructions Retired
|
||||
Proc->Core[cpu]->Delta.INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST \
|
||||
- Proc->Core[cpu]->Counter[0].INST;
|
||||
Core->Delta.INST= \
|
||||
Core->Counter[1].INST \
|
||||
- Core->Counter[0].INST;
|
||||
|
||||
// Absolute Delta of Unhalted (Core & Ref) C0 Counter.
|
||||
Proc->Core[cpu]->Delta.C0.UCC= \
|
||||
(Proc->Core[cpu]->Counter[0].C0.UCC > \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC) ? \
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
: Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.UCC;
|
||||
Core->Delta.C0.UCC= \
|
||||
(Core->Counter[0].C0.UCC > \
|
||||
Core->Counter[1].C0.UCC) ? \
|
||||
Core->Counter[0].C0.UCC \
|
||||
- Core->Counter[1].C0.UCC \
|
||||
: Core->Counter[1].C0.UCC \
|
||||
- Core->Counter[0].C0.UCC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.URC;
|
||||
Core->Delta.C0.URC= \
|
||||
Core->Counter[1].C0.URC \
|
||||
- Core->Counter[0].C0.URC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C3= \
|
||||
Proc->Core[cpu]->Counter[1].C3 \
|
||||
- Proc->Core[cpu]->Counter[0].C3;
|
||||
Proc->Core[cpu]->Delta.C6= \
|
||||
Proc->Core[cpu]->Counter[1].C6 \
|
||||
- Proc->Core[cpu]->Counter[0].C6;
|
||||
Core->Delta.C3= \
|
||||
Core->Counter[1].C3 \
|
||||
- Core->Counter[0].C3;
|
||||
Core->Delta.C6= \
|
||||
Core->Counter[1].C6 \
|
||||
- Core->Counter[0].C6;
|
||||
|
||||
Proc->Core[cpu]->Delta.TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC \
|
||||
- Proc->Core[cpu]->Counter[0].TSC;
|
||||
Core->Delta.TSC= \
|
||||
Core->Counter[1].TSC \
|
||||
- Core->Counter[0].TSC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C1= \
|
||||
(Proc->Core[cpu]->Counter[0].C1 > \
|
||||
Proc->Core[cpu]->Counter[1].C1) ? \
|
||||
Proc->Core[cpu]->Counter[0].C1 \
|
||||
- Proc->Core[cpu]->Counter[1].C1 \
|
||||
: Proc->Core[cpu]->Counter[1].C1 \
|
||||
- Proc->Core[cpu]->Counter[0].C1;
|
||||
Core->Delta.C1= \
|
||||
(Core->Counter[0].C1 > \
|
||||
Core->Counter[1].C1) ? \
|
||||
Core->Counter[0].C1 \
|
||||
- Core->Counter[1].C1 \
|
||||
: Core->Counter[1].C1 \
|
||||
- Core->Counter[0].C1;
|
||||
|
||||
// Save the Instructions counter.
|
||||
Proc->Core[cpu]->Counter[0].INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST;
|
||||
Core->Counter[0].INST= \
|
||||
Core->Counter[1].INST;
|
||||
|
||||
// Save TSC.
|
||||
Proc->Core[cpu]->Counter[0].TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC;
|
||||
Core->Counter[0].TSC= \
|
||||
Core->Counter[1].TSC;
|
||||
|
||||
// Save the Unhalted Core & Reference Counter
|
||||
// for next iteration.
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC;
|
||||
Proc->Core[cpu]->Counter[1].C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC;
|
||||
Core->Counter[0].C0.UCC= \
|
||||
Core->Counter[1].C0.UCC;
|
||||
Core->Counter[1].C0.URC= \
|
||||
Core->Counter[1].C0.URC;
|
||||
|
||||
// Save also the C-State Reference Counter.
|
||||
Proc->Core[cpu]->Counter[0].C3= \
|
||||
Proc->Core[cpu]->Counter[1].C3;
|
||||
Proc->Core[cpu]->Counter[0].C6= \
|
||||
Proc->Core[cpu]->Counter[1].C6;
|
||||
Proc->Core[cpu]->Counter[0].C1= \
|
||||
Proc->Core[cpu]->Counter[1].C1;
|
||||
Core->Counter[0].C3= \
|
||||
Core->Counter[1].C3;
|
||||
Core->Counter[0].C6= \
|
||||
Core->Counter[1].C6;
|
||||
Core->Counter[0].C1= \
|
||||
Core->Counter[1].C1;
|
||||
|
||||
atomic_store(&Proc->Core[cpu]->Sync, 0x1);
|
||||
atomic_store(&Core->Sync, 0x1);
|
||||
}
|
||||
Counters_Clear(cpu);
|
||||
Counters_Clear(Core);
|
||||
}
|
||||
do_exit(0);
|
||||
}
|
||||
@@ -995,11 +962,11 @@ int Cycle_SandyBridge(void *arg)
|
||||
if(arg != NULL)
|
||||
{
|
||||
CORE *Core=(CORE *) arg;
|
||||
unsigned int cpu=Core->Bind;
|
||||
// unsigned int cpu=Core->Bind;
|
||||
unsigned int leave=0, down=0, steps=Proc->msleep / 100;
|
||||
|
||||
Counters_Set(cpu);
|
||||
Counters_SandyBridge(cpu, 0);
|
||||
Counters_Set(Core);
|
||||
Counters_SandyBridge(Core, 0);
|
||||
|
||||
while(!leave)
|
||||
{
|
||||
@@ -1011,77 +978,77 @@ int Cycle_SandyBridge(void *arg)
|
||||
leave=1;
|
||||
} while(--down && !leave);
|
||||
|
||||
Counters_SandyBridge(cpu, 1);
|
||||
Core_Temp(cpu);
|
||||
Counters_SandyBridge(Core, 1);
|
||||
Core_Temp(Core);
|
||||
|
||||
// Delta of Instructions Retired
|
||||
Proc->Core[cpu]->Delta.INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST \
|
||||
- Proc->Core[cpu]->Counter[0].INST;
|
||||
Core->Delta.INST= \
|
||||
Core->Counter[1].INST \
|
||||
- Core->Counter[0].INST;
|
||||
|
||||
// Absolute Delta of Unhalted (Core & Ref) C0 Counter.
|
||||
Proc->Core[cpu]->Delta.C0.UCC= \
|
||||
(Proc->Core[cpu]->Counter[0].C0.UCC > \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC) ? \
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
: Proc->Core[cpu]->Counter[1].C0.UCC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.UCC;
|
||||
Core->Delta.C0.UCC= \
|
||||
(Core->Counter[0].C0.UCC > \
|
||||
Core->Counter[1].C0.UCC) ? \
|
||||
Core->Counter[0].C0.UCC \
|
||||
- Core->Counter[1].C0.UCC \
|
||||
: Core->Counter[1].C0.UCC \
|
||||
- Core->Counter[0].C0.UCC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC \
|
||||
- Proc->Core[cpu]->Counter[0].C0.URC;
|
||||
Core->Delta.C0.URC= \
|
||||
Core->Counter[1].C0.URC \
|
||||
- Core->Counter[0].C0.URC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C3= \
|
||||
Proc->Core[cpu]->Counter[1].C3 \
|
||||
- Proc->Core[cpu]->Counter[0].C3;
|
||||
Proc->Core[cpu]->Delta.C6= \
|
||||
Proc->Core[cpu]->Counter[1].C6 \
|
||||
- Proc->Core[cpu]->Counter[0].C6;
|
||||
Proc->Core[cpu]->Delta.C7= \
|
||||
Proc->Core[cpu]->Counter[1].C7 \
|
||||
- Proc->Core[cpu]->Counter[0].C7;
|
||||
Core->Delta.C3= \
|
||||
Core->Counter[1].C3 \
|
||||
- Core->Counter[0].C3;
|
||||
Core->Delta.C6= \
|
||||
Core->Counter[1].C6 \
|
||||
- Core->Counter[0].C6;
|
||||
Core->Delta.C7= \
|
||||
Core->Counter[1].C7 \
|
||||
- Core->Counter[0].C7;
|
||||
|
||||
Proc->Core[cpu]->Delta.TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC \
|
||||
- Proc->Core[cpu]->Counter[0].TSC;
|
||||
Core->Delta.TSC= \
|
||||
Core->Counter[1].TSC \
|
||||
- Core->Counter[0].TSC;
|
||||
|
||||
Proc->Core[cpu]->Delta.C1= \
|
||||
(Proc->Core[cpu]->Counter[0].C1 > \
|
||||
Proc->Core[cpu]->Counter[1].C1) ? \
|
||||
Proc->Core[cpu]->Counter[0].C1 \
|
||||
- Proc->Core[cpu]->Counter[1].C1 \
|
||||
: Proc->Core[cpu]->Counter[1].C1 \
|
||||
- Proc->Core[cpu]->Counter[0].C1;
|
||||
Core->Delta.C1= \
|
||||
(Core->Counter[0].C1 > \
|
||||
Core->Counter[1].C1) ? \
|
||||
Core->Counter[0].C1 \
|
||||
- Core->Counter[1].C1 \
|
||||
: Core->Counter[1].C1 \
|
||||
- Core->Counter[0].C1;
|
||||
|
||||
// Save the Instructions counter.
|
||||
Proc->Core[cpu]->Counter[0].INST= \
|
||||
Proc->Core[cpu]->Counter[1].INST;
|
||||
Core->Counter[0].INST= \
|
||||
Core->Counter[1].INST;
|
||||
|
||||
// Save TSC.
|
||||
Proc->Core[cpu]->Counter[0].TSC= \
|
||||
Proc->Core[cpu]->Counter[1].TSC;
|
||||
Core->Counter[0].TSC= \
|
||||
Core->Counter[1].TSC;
|
||||
|
||||
// Save the Unhalted Core & Reference Counter
|
||||
// for next iteration.
|
||||
Proc->Core[cpu]->Counter[0].C0.UCC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.UCC;
|
||||
Proc->Core[cpu]->Counter[1].C0.URC= \
|
||||
Proc->Core[cpu]->Counter[1].C0.URC;
|
||||
Core->Counter[0].C0.UCC= \
|
||||
Core->Counter[1].C0.UCC;
|
||||
Core->Counter[1].C0.URC= \
|
||||
Core->Counter[1].C0.URC;
|
||||
|
||||
// Save also the C-State Reference Counter.
|
||||
Proc->Core[cpu]->Counter[0].C3= \
|
||||
Proc->Core[cpu]->Counter[1].C3;
|
||||
Proc->Core[cpu]->Counter[0].C6= \
|
||||
Proc->Core[cpu]->Counter[1].C6;
|
||||
Proc->Core[cpu]->Counter[0].C7= \
|
||||
Proc->Core[cpu]->Counter[1].C7;
|
||||
Proc->Core[cpu]->Counter[0].C1= \
|
||||
Proc->Core[cpu]->Counter[1].C1;
|
||||
Core->Counter[0].C3= \
|
||||
Core->Counter[1].C3;
|
||||
Core->Counter[0].C6= \
|
||||
Core->Counter[1].C6;
|
||||
Core->Counter[0].C7= \
|
||||
Core->Counter[1].C7;
|
||||
Core->Counter[0].C1= \
|
||||
Core->Counter[1].C1;
|
||||
|
||||
atomic_store(&Proc->Core[cpu]->Sync, 0x1);
|
||||
atomic_store(&Core->Sync, 0x1);
|
||||
}
|
||||
Counters_Clear(cpu);
|
||||
Counters_Clear(Core);
|
||||
}
|
||||
do_exit(0);
|
||||
}
|
||||
@@ -1196,8 +1163,9 @@ printk("Stage 0: Welcome\n");
|
||||
IntelFreq.mkdev, NULL,
|
||||
DRV_DEVNAME)) != NULL)
|
||||
{
|
||||
unsigned int cpu=0;
|
||||
unsigned long vmSize=sizeof(PROC);
|
||||
unsigned int cpu=0, count=Core_Count();
|
||||
unsigned long vmSize=sizeof(PROC)
|
||||
+ sizeof(void *) * count;
|
||||
|
||||
printk("Stage 1: Requesting %lu Bytes\n", vmSize);
|
||||
if((Proc=kmalloc(vmSize, GFP_KERNEL)) == NULL)
|
||||
@@ -1205,10 +1173,9 @@ printk("Stage 1: Requesting %lu Bytes\n", vmSize);
|
||||
else {
|
||||
vmSize=ksize(Proc);
|
||||
|
||||
printk("Stage 2: Proc at %p w/ Kernel mem size of %zd Bytes\n", Proc, vmSize);
|
||||
printk("Stage 2: Proc at %p allocated %zd Bytes\n", Proc, vmSize);
|
||||
|
||||
cpu=Core_Count();
|
||||
Proc->CPU.Count=cpu;
|
||||
Proc->CPU.Count=count;
|
||||
Proc->msleep=LOOP_DEF_MS;
|
||||
Proc->PerCore=0;
|
||||
Proc_Features(&Proc->Features);
|
||||
@@ -1216,10 +1183,10 @@ printk("Stage 2: Proc at %p w/ Kernel mem size of %zd Bytes\n", Proc, vmSize);
|
||||
printk("Stage 3: CPU Count=%u\n", Proc->CPU.Count);
|
||||
|
||||
vmSize=sizeof(CORE);
|
||||
vmSize=PAGE_SIZE * ((vmSize / PAGE_SIZE) + ((vmSize % PAGE_SIZE)? 1:0));
|
||||
// vmSize=PAGE_SIZE * ((vmSize / PAGE_SIZE) + ((vmSize % PAGE_SIZE)? 1:0));
|
||||
printk("Stage 4: Requesting KMem Cache of %lu Bytes\n", vmSize);
|
||||
|
||||
if((Proc->Cache=kmem_cache_create("intelfreq_cache",
|
||||
if((Proc->Cache=kmem_cache_create("intelfreq-cache",
|
||||
vmSize, 0,
|
||||
SLAB_HWCACHE_ALIGN, NULL)) == NULL)
|
||||
return(-ENOMEM);
|
||||
@@ -1342,7 +1309,7 @@ printk("Stage 2: KMem Cache destroyed at %p\n", Proc->Cache);
|
||||
kmem_cache_destroy(Proc->Cache);
|
||||
}
|
||||
if(Proc != NULL) {
|
||||
printk("Stage 3: Releasing %zd Bytes of Kernel memory\n", ksize(Proc));
|
||||
printk("Stage 3: Releasing %zd allocated Bytes\n", ksize(Proc));
|
||||
kfree(Proc);
|
||||
}
|
||||
device_destroy(IntelFreq.clsdev, IntelFreq.mkdev);
|
||||
|
||||
26
intelfreq.h
26
intelfreq.h
@@ -37,7 +37,7 @@
|
||||
"d" ((unsigned int) (_val >> 32)) \
|
||||
);
|
||||
|
||||
#define RDMSR(_val, _reg) \
|
||||
#define RDMSR(_data, _reg) \
|
||||
({ \
|
||||
unsigned int _lo, _hi; \
|
||||
\
|
||||
@@ -48,17 +48,17 @@
|
||||
"=d" (_hi) \
|
||||
: "c" (_reg) \
|
||||
); \
|
||||
_val.qword=_lo | ((unsigned long long) _hi << 32); \
|
||||
_data.value=_lo | ((unsigned long long) _hi << 32); \
|
||||
})
|
||||
|
||||
#define WRMSR(_val, _reg) \
|
||||
#define WRMSR(_data, _reg) \
|
||||
__asm__ volatile \
|
||||
( \
|
||||
"wrmsr" \
|
||||
: \
|
||||
: "c" (_reg), \
|
||||
"a" ((unsigned int) _val.qword & 0xFFFFFFFF), \
|
||||
"d" ((unsigned int) (_val.qword >> 32)) \
|
||||
"a" ((unsigned int) _data.value & 0xFFFFFFFF),\
|
||||
"d" ((unsigned int) (_data.value >> 32)) \
|
||||
);
|
||||
/*
|
||||
#define MOVSB(_dest, _src, _count) \
|
||||
@@ -461,7 +461,7 @@ typedef struct
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -499,7 +499,7 @@ typedef struct
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -555,7 +555,7 @@ typedef struct
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -573,7 +573,7 @@ typedef union
|
||||
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -595,7 +595,7 @@ typedef union
|
||||
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -616,7 +616,7 @@ typedef union
|
||||
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -637,7 +637,7 @@ typedef union
|
||||
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
@@ -665,7 +665,7 @@ typedef union
|
||||
|
||||
typedef union
|
||||
{
|
||||
unsigned long long qword;
|
||||
unsigned long long value;
|
||||
struct
|
||||
{
|
||||
unsigned long long
|
||||
|
||||
Reference in New Issue
Block a user