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Introducing a new ThermalOffset parameter:

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* Temperature offset is implemented per Intel architecture class.
This commit is contained in:
CyrIng
2022-10-29 10:19:09 +00:00
parent 3084c10c3b
commit 6af7d895b3
2 changed files with 62 additions and 0 deletions
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1
README.md
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@@ -513,6 +513,7 @@ parm: HDC_Enable:Hardware Duty Cycling (short)
parm: EEO_Disable:Disable Energy Efficiency Optimization (short)
parm: R2H_Disable:Disable Race to Halt (short)
parm: Clear_Events:Clear Thermal and Power Events (ullong)
parm: ThermalOffset:Thermal Offset (short)
parm: ThermalScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)
parm: VoltageScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)
parm: PowerScope:[0:None; 1:SMT; 2:Core; 3:Package] (int)

61
corefreqk.c
View File

@@ -340,6 +340,10 @@ module_param_array(PkgThermalPoint, short, &PkgThermalPoint_Count, \
S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(PkgThermalPoint, "Package Thermal Point");
static signed short ThermalOffset = 0;
module_param(ThermalOffset, short, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ThermalOffset, "Thermal Offset");
static int ThermalScope = -1;
module_param(ThermalScope, int, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH);
MODULE_PARM_DESC(ThermalScope, "[0:None; 1:SMT; 2:Core; 3:Package]");
@@ -3679,6 +3683,61 @@ void Intel_Pkg_CST_IRTL(const unsigned int MSR, PKGCST_IRTL *PCST)
RDMSR((*PCST), MSR);
}
long Intel_ThermalOffset(bool programmableTj)
{
long rc = -EINVAL;
if (ThermalOffset != 0) {
if (programmableTj)
{
TJMAX TjMax = {.value = 0};
RDMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
switch (PUBLIC(RO(Proc))->ArchID) {
case Atom_Goldmont:
case Xeon_Phi: /* TODO(06_85h) */ {
const short offset = TjMax.Atom.Offset + ThermalOffset;
if ((offset >= 0) && (offset <= 0b111111)) {
TjMax.Atom.Offset = offset;
WRMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
RDMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
rc = RC_OK_COMPUTE;
}
}
break;
case IvyBridge_EP:
case Broadwell_EP:
case Broadwell_D:
case Skylake_X: {
const short offset = TjMax.EP.Offset + ThermalOffset;
if ((offset >= 0) && (offset <= 0b1111)) {
TjMax.EP.Offset = offset;
WRMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
RDMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
rc = RC_OK_COMPUTE;
}
}
break;
default: {
const short offset = TjMax.Offset + ThermalOffset;
if ((offset >= 0) && (offset <= 0b1111)) {
TjMax.Offset = offset;
WRMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
RDMSR(TjMax, MSR_IA32_TEMPERATURE_TARGET);
rc = RC_OK_COMPUTE;
}
}
break;
case Core_Yonah ... Core_Dunnington:
rc = -RC_UNIMPLEMENTED;
break;
}
} else {
rc = -RC_UNIMPLEMENTED;
}
}
return rc;
}
void Intel_Processor_PIN(bool capable)
{
if (capable) {
@@ -3823,6 +3882,8 @@ void Query_Same_Platform_Features(unsigned int cpu)
Intel_Processor_PIN(PfInfo.PPIN_CAP);
Intel_ThermalOffset(PfInfo.ProgrammableTj);
PUBLIC(RO(Proc))->Features.SpecTurboRatio = 0;
}