mirror of
https://github.com/sarah-walker-pcem/pcem.git
synced 2025-07-23 03:33:02 +02:00
773 lines
20 KiB
C
773 lines
20 KiB
C
#ifndef _X86_OPS_STRING_H_
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#define _X86_OPS_STRING_H_
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static int opMOVSB_a16(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmemb(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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writememb(es, DI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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DI--;
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SI--;
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} else {
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DI++;
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SI++;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 1, 0, 0);
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return 0;
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}
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static int opMOVSB_a32(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmemb(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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writememb(es, EDI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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EDI--;
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ESI--;
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} else {
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EDI++;
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ESI++;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 1, 0, 1);
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return 0;
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}
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static int opMOVSW_a16(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmemw(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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writememw(es, DI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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DI -= 2;
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SI -= 2;
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} else {
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DI += 2;
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SI += 2;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 1, 0, 0);
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return 0;
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}
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static int opMOVSW_a32(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmemw(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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writememw(es, EDI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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EDI -= 2;
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ESI -= 2;
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} else {
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EDI += 2;
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ESI += 2;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 1, 0, 1);
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return 0;
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}
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static int opMOVSL_a16(uint32_t fetchdat) {
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmeml(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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writememl(es, DI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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DI -= 4;
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SI -= 4;
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} else {
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DI += 4;
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SI += 4;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 0, 1, 0, 1, 0);
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return 0;
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}
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static int opMOVSL_a32(uint32_t fetchdat) {
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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temp = readmeml(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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writememl(es, EDI, temp);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG) {
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EDI -= 4;
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ESI -= 4;
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} else {
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EDI += 4;
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ESI += 4;
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}
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 0, 1, 0, 1, 1);
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return 0;
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}
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static int opCMPSB_a16(uint32_t fetchdat) {
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uint8_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmemb(cpu_state.ea_seg->base, SI);
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dst = readmemb(es, DI);
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if (cpu_state.abrt)
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return 1;
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setsub8(src, dst);
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if (cpu_state.flags & D_FLAG) {
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DI--;
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SI--;
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} else {
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DI++;
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SI++;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2, 0, 0, 0, 0);
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return 0;
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}
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static int opCMPSB_a32(uint32_t fetchdat) {
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uint8_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmemb(cpu_state.ea_seg->base, ESI);
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dst = readmemb(es, EDI);
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if (cpu_state.abrt)
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return 1;
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setsub8(src, dst);
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if (cpu_state.flags & D_FLAG) {
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EDI--;
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ESI--;
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} else {
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EDI++;
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ESI++;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2, 0, 0, 0, 1);
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return 0;
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}
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static int opCMPSW_a16(uint32_t fetchdat) {
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uint16_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmemw(cpu_state.ea_seg->base, SI);
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dst = readmemw(es, DI);
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if (cpu_state.abrt)
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return 1;
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setsub16(src, dst);
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if (cpu_state.flags & D_FLAG) {
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DI -= 2;
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SI -= 2;
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} else {
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DI += 2;
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SI += 2;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2, 0, 0, 0, 0);
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return 0;
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}
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static int opCMPSW_a32(uint32_t fetchdat) {
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uint16_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmemw(cpu_state.ea_seg->base, ESI);
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dst = readmemw(es, EDI);
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if (cpu_state.abrt)
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return 1;
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setsub16(src, dst);
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if (cpu_state.flags & D_FLAG) {
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EDI -= 2;
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ESI -= 2;
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} else {
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EDI += 2;
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ESI += 2;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 2, 0, 0, 0, 1);
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return 0;
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}
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static int opCMPSL_a16(uint32_t fetchdat) {
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uint32_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmeml(cpu_state.ea_seg->base, SI);
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dst = readmeml(es, DI);
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if (cpu_state.abrt)
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return 1;
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setsub32(src, dst);
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if (cpu_state.flags & D_FLAG) {
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DI -= 4;
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SI -= 4;
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} else {
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DI += 4;
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SI += 4;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0, 2, 0, 0, 0);
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return 0;
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}
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static int opCMPSL_a32(uint32_t fetchdat) {
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uint32_t src, dst;
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SEG_CHECK_READ(cpu_state.ea_seg);
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SEG_CHECK_READ(&cpu_state.seg_es);
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src = readmeml(cpu_state.ea_seg->base, ESI);
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dst = readmeml(es, EDI);
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if (cpu_state.abrt)
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return 1;
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setsub32(src, dst);
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if (cpu_state.flags & D_FLAG) {
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EDI -= 4;
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ESI -= 4;
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} else {
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EDI += 4;
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ESI += 4;
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}
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CLOCK_CYCLES((is486) ? 8 : 10);
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PREFETCH_RUN((is486) ? 8 : 10, 1, -1, 0, 2, 0, 0, 1);
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return 0;
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}
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static int opSTOSB_a16(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememb(es, DI, AL);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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DI--;
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else
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DI++;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 1, 0, 0);
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return 0;
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}
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static int opSTOSB_a32(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememb(es, EDI, AL);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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EDI--;
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else
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EDI++;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 1, 0, 1);
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return 0;
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}
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static int opSTOSW_a16(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememw(es, DI, AX);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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DI -= 2;
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else
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DI += 2;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 1, 0, 0);
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return 0;
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}
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static int opSTOSW_a32(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememw(es, EDI, AX);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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EDI -= 2;
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else
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EDI += 2;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 1, 0, 1);
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return 0;
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}
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static int opSTOSL_a16(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememl(es, DI, EAX);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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DI -= 4;
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else
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DI += 4;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 0, 1, 0);
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return 0;
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}
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static int opSTOSL_a32(uint32_t fetchdat) {
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SEG_CHECK_WRITE(&cpu_state.seg_es);
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writememl(es, EDI, EAX);
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if (cpu_state.abrt)
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return 1;
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if (cpu_state.flags & D_FLAG)
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EDI -= 4;
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else
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EDI += 4;
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CLOCK_CYCLES(4);
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PREFETCH_RUN(4, 1, -1, 0, 0, 0, 1, 1);
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return 0;
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}
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static int opLODSB_a16(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmemb(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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AL = temp;
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if (cpu_state.flags & D_FLAG)
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SI--;
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else
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SI++;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opLODSB_a32(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmemb(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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AL = temp;
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if (cpu_state.flags & D_FLAG)
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ESI--;
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else
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ESI++;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 1);
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return 0;
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}
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static int opLODSW_a16(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmemw(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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AX = temp;
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if (cpu_state.flags & D_FLAG)
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SI -= 2;
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else
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SI += 2;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opLODSW_a32(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmemw(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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AX = temp;
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if (cpu_state.flags & D_FLAG)
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ESI -= 2;
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else
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ESI += 2;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 1, 0, 0, 0, 1);
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return 0;
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}
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static int opLODSL_a16(uint32_t fetchdat) {
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmeml(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt)
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return 1;
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EAX = temp;
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if (cpu_state.flags & D_FLAG)
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SI -= 4;
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else
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SI += 4;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 0, 1, 0, 0, 0);
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return 0;
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}
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static int opLODSL_a32(uint32_t fetchdat) {
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uint32_t temp;
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SEG_CHECK_READ(cpu_state.ea_seg);
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temp = readmeml(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt)
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return 1;
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EAX = temp;
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if (cpu_state.flags & D_FLAG)
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ESI -= 4;
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else
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ESI += 4;
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CLOCK_CYCLES(5);
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PREFETCH_RUN(5, 1, -1, 0, 1, 0, 0, 1);
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return 0;
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}
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static int opSCASB_a16(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(&cpu_state.seg_es);
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temp = readmemb(es, DI);
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if (cpu_state.abrt)
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return 1;
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setsub8(AL, temp);
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if (cpu_state.flags & D_FLAG)
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DI--;
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else
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DI++;
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opSCASB_a32(uint32_t fetchdat) {
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uint8_t temp;
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SEG_CHECK_READ(&cpu_state.seg_es);
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temp = readmemb(es, EDI);
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if (cpu_state.abrt)
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return 1;
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setsub8(AL, temp);
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if (cpu_state.flags & D_FLAG)
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EDI--;
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else
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EDI++;
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 0, 0, 1);
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return 0;
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}
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static int opSCASW_a16(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(&cpu_state.seg_es);
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temp = readmemw(es, DI);
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if (cpu_state.abrt)
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return 1;
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setsub16(AX, temp);
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if (cpu_state.flags & D_FLAG)
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DI -= 2;
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else
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DI += 2;
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 0, 0, 0);
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return 0;
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}
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static int opSCASW_a32(uint32_t fetchdat) {
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uint16_t temp;
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SEG_CHECK_READ(&cpu_state.seg_es);
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temp = readmemw(es, EDI);
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if (cpu_state.abrt)
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return 1;
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setsub16(AX, temp);
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if (cpu_state.flags & D_FLAG)
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EDI -= 2;
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else
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EDI += 2;
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CLOCK_CYCLES(7);
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PREFETCH_RUN(7, 1, -1, 1, 0, 0, 0, 1);
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return 0;
|
|
}
|
|
|
|
static int opSCASL_a16(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_READ(&cpu_state.seg_es);
|
|
temp = readmeml(es, DI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
setsub32(EAX, temp);
|
|
if (cpu_state.flags & D_FLAG)
|
|
DI -= 4;
|
|
else
|
|
DI += 4;
|
|
CLOCK_CYCLES(7);
|
|
PREFETCH_RUN(7, 1, -1, 0, 1, 0, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opSCASL_a32(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_READ(&cpu_state.seg_es);
|
|
temp = readmeml(es, EDI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
setsub32(EAX, temp);
|
|
if (cpu_state.flags & D_FLAG)
|
|
EDI -= 4;
|
|
else
|
|
EDI += 4;
|
|
CLOCK_CYCLES(7);
|
|
PREFETCH_RUN(7, 1, -1, 0, 1, 0, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opINSB_a16(uint32_t fetchdat) {
|
|
uint8_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
temp = inb(DX);
|
|
writememb(es, DI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
DI--;
|
|
else
|
|
DI++;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 1, 0, 1, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opINSB_a32(uint32_t fetchdat) {
|
|
uint8_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
temp = inb(DX);
|
|
writememb(es, EDI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
EDI--;
|
|
else
|
|
EDI++;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 1, 0, 1, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opINSW_a16(uint32_t fetchdat) {
|
|
uint16_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
temp = inw(DX);
|
|
writememw(es, DI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
DI -= 2;
|
|
else
|
|
DI += 2;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 1, 0, 1, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opINSW_a32(uint32_t fetchdat) {
|
|
uint16_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
temp = inw(DX);
|
|
writememw(es, EDI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
EDI -= 2;
|
|
else
|
|
EDI += 2;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 1, 0, 1, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opINSL_a16(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
check_io_perm(DX + 2);
|
|
check_io_perm(DX + 3);
|
|
temp = inl(DX);
|
|
writememl(es, DI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
DI -= 4;
|
|
else
|
|
DI += 4;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 0, 1, 0, 1, 0);
|
|
return 0;
|
|
}
|
|
static int opINSL_a32(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_WRITE(&cpu_state.seg_es);
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
check_io_perm(DX + 2);
|
|
check_io_perm(DX + 3);
|
|
temp = inl(DX);
|
|
writememl(es, EDI, temp);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
if (cpu_state.flags & D_FLAG)
|
|
EDI -= 4;
|
|
else
|
|
EDI += 4;
|
|
CLOCK_CYCLES(15);
|
|
PREFETCH_RUN(15, 1, -1, 0, 1, 0, 1, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opOUTSB_a16(uint32_t fetchdat) {
|
|
uint8_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmemb(cpu_state.ea_seg->base, SI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
if (cpu_state.flags & D_FLAG)
|
|
SI--;
|
|
else
|
|
SI++;
|
|
outb(DX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 1, 0, 1, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opOUTSB_a32(uint32_t fetchdat) {
|
|
uint8_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmemb(cpu_state.ea_seg->base, ESI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
if (cpu_state.flags & D_FLAG)
|
|
ESI--;
|
|
else
|
|
ESI++;
|
|
outb(DX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 1, 0, 1, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opOUTSW_a16(uint32_t fetchdat) {
|
|
uint16_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmemw(cpu_state.ea_seg->base, SI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
if (cpu_state.flags & D_FLAG)
|
|
SI -= 2;
|
|
else
|
|
SI += 2;
|
|
outw(DX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 1, 0, 1, 0, 0);
|
|
return 0;
|
|
}
|
|
static int opOUTSW_a32(uint32_t fetchdat) {
|
|
uint16_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmemw(cpu_state.ea_seg->base, ESI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
if (cpu_state.flags & D_FLAG)
|
|
ESI -= 2;
|
|
else
|
|
ESI += 2;
|
|
outw(DX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 1, 0, 1, 0, 1);
|
|
return 0;
|
|
}
|
|
|
|
static int opOUTSL_a16(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmeml(cpu_state.ea_seg->base, SI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
check_io_perm(DX + 2);
|
|
check_io_perm(DX + 3);
|
|
if (cpu_state.flags & D_FLAG)
|
|
SI -= 4;
|
|
else
|
|
SI += 4;
|
|
outl(EDX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 0, 1, 0, 1, 0);
|
|
return 0;
|
|
}
|
|
static int opOUTSL_a32(uint32_t fetchdat) {
|
|
uint32_t temp;
|
|
|
|
SEG_CHECK_READ(cpu_state.ea_seg);
|
|
temp = readmeml(cpu_state.ea_seg->base, ESI);
|
|
if (cpu_state.abrt)
|
|
return 1;
|
|
check_io_perm(DX);
|
|
check_io_perm(DX + 1);
|
|
check_io_perm(DX + 2);
|
|
check_io_perm(DX + 3);
|
|
if (cpu_state.flags & D_FLAG)
|
|
ESI -= 4;
|
|
else
|
|
ESI += 4;
|
|
outl(EDX, temp);
|
|
CLOCK_CYCLES(14);
|
|
PREFETCH_RUN(14, 1, -1, 0, 1, 0, 1, 1);
|
|
return 0;
|
|
}
|
|
|
|
#endif /* _X86_OPS_STRING_H_ */
|