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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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388 lines
12 KiB
C
388 lines
12 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _OS_DSI_PANEL_PARAMS_H_
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#define _OS_DSI_PANEL_PARAMS_H_
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#define DSI_GENERIC_LONG_WRITE 0x29
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#define DSI_DCS_LONG_WRITE 0x39
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#define DSI_GENERIC_SHORT_WRITE_1_PARAMS 0x13
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#define DSI_GENERIC_SHORT_WRITE_2_PARAMS 0x23
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#define DSI_DCS_WRITE_0_PARAM 0x05
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#define DSI_DCS_WRITE_1_PARAM 0x15
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#define DSI_DCS_READ_PARAM 0x06
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#define DSI_DCS_COMPRESSION_MODE 0x07
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#define DSI_DCS_PPS_LONG_WRITE 0x0A
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#define DSI_DCS_SET_ADDR_MODE 0x36
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#define DSI_DCS_EXIT_SLEEP_MODE 0x11
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#define DSI_DCS_ENTER_SLEEP_MODE 0x10
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#define DSI_DCS_SET_DISPLAY_ON 0x29
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#define DSI_DCS_SET_DISPLAY_OFF 0x28
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#define DSI_DCS_SET_TEARING_EFFECT_OFF 0x34
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#define DSI_DCS_SET_TEARING_EFFECT_ON 0x35
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#define DSI_DCS_NO_OP 0x0
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#define DSI_NULL_PKT_NO_DATA 0x9
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#define DSI_BLANKING_PKT_NO_DATA 0x19
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#define DSI_DCS_SET_COMPRESSION_METHOD 0xC0
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/* DCS commands for command mode */
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#define DSI_ENTER_PARTIAL_MODE 0x12
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#define DSI_SET_PIXEL_FORMAT 0x3A
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#define DSI_AREA_COLOR_MODE 0x4C
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#define DSI_SET_PARTIAL_AREA 0x30
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#define DSI_SET_PAGE_ADDRESS 0x2B
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#define DSI_SET_ADDRESS_MODE 0x36
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#define DSI_SET_COLUMN_ADDRESS 0x2A
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#define DSI_WRITE_MEMORY_START 0x2C
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#define DSI_WRITE_MEMORY_CONTINUE 0x3C
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#define PKT_ID0(id) ((((id) & 0x3f) << 3) | \
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(((DSI_ENABLE) & 0x1) << 9))
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#define PKT_LEN0(len) (((len) & 0x7) << 0)
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#define PKT_ID1(id) ((((id) & 0x3f) << 13) | \
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(((DSI_ENABLE) & 0x1) << 19))
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#define PKT_LEN1(len) (((len) & 0x7) << 10)
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#define PKT_ID2(id) ((((id) & 0x3f) << 23) | \
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(((DSI_ENABLE) & 0x1) << 29))
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#define PKT_LEN2(len) (((len) & 0x7) << 20)
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#define PKT_ID3(id) ((((id) & 0x3f) << 3) | \
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(((DSI_ENABLE) & 0x1) << 9))
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#define PKT_LEN3(len) (((len) & 0x7) << 0)
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#define PKT_ID4(id) ((((id) & 0x3f) << 13) | \
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(((DSI_ENABLE) & 0x1) << 19))
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#define PKT_LEN4(len) (((len) & 0x7) << 10)
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#define PKT_ID5(id) ((((id) & 0x3f) << 23) | \
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(((DSI_ENABLE) & 0x1) << 29))
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#define PKT_LEN5(len) (((len) & 0x7) << 20)
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#define PKT_LP (((DSI_ENABLE) & 0x1) << 30)
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#define NUMOF_PKT_SEQ 12
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/* DSI pixel data format, enum values should match with dt-bindings in tegra-panel.h */
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typedef enum
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{
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DSI_PIXEL_FORMAT_16BIT_P,
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DSI_PIXEL_FORMAT_18BIT_P,
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DSI_PIXEL_FORMAT_18BIT_NP,
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DSI_PIXEL_FORMAT_24BIT_P,
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DSI_PIXEL_FORMAT_8BIT_DSC,
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DSI_PIXEL_FORMAT_12BIT_DSC,
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DSI_PIXEL_FORMAT_16BIT_DSC,
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DSI_PIXEL_FORMAT_10BIT_DSC,
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DSI_PIXEL_FORMAT_30BIT_P,
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DSI_PIXEL_FORMAT_36BIT_P,
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} DSIPIXELFORMAT;
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/* DSI virtual channel number */
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typedef enum
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{
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DSI_VIRTUAL_CHANNEL_0,
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DSI_VIRTUAL_CHANNEL_1,
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DSI_VIRTUAL_CHANNEL_2,
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DSI_VIRTUAL_CHANNEL_3,
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} DSIVIRTUALCHANNEL;
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/* DSI transmit method for video data */
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typedef enum
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{
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DSI_VIDEO_TYPE_VIDEO_MODE,
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DSI_VIDEO_TYPE_COMMAND_MODE,
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} DSIVIDEODATAMODE;
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/* DSI HS clock mode */
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typedef enum
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{
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DSI_VIDEO_CLOCK_CONTINUOUS,
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DSI_VIDEO_CLOCK_TX_ONLY,
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} DSICLOCKMODE;
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/* DSI burst mode setting in video mode. Each mode is assigned with a
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* fixed value. The rationale behind this is to avoid change of these
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* values, since the calculation of dsi clock depends on them. */
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typedef enum
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{
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DSI_VIDEO_NON_BURST_MODE = 0,
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DSI_VIDEO_NON_BURST_MODE_WITH_SYNC_END = 1,
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DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
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DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
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DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
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DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
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DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
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} DSIVIDEOBURSTMODE;
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/* DSI Ganged Mode */
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typedef enum
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{
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DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
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DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
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DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP = 3,
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} DSIGANGEDTYPE;
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typedef enum
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{
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DSI_LINK0,
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DSI_LINK1,
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} DSILINKNUM;
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/* DSI Command Packet type */
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typedef enum
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{
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DSI_PACKET_CMD,
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DSI_DELAY_MS,
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DSI_GPIO_SET,
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DSI_SEND_FRAME,
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DSI_PACKET_VIDEO_VBLANK_CMD,
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DSI_DELAY_US,
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} DSICMDPKTTYPE;
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/* DSI Phy type */
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typedef enum
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{
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DSI_DPHY,
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DSI_CPHY,
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} DSIPHYTYPE;
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enum {
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DSI_GPIO_LCD_RESET,
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DSI_GPIO_PANEL_EN,
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DSI_GPIO_PANEL_EN_1,
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DSI_GPIO_BL_ENABLE,
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DSI_GPIO_BL_PWM,
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DSI_GPIO_AVDD_AVEE_EN,
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DSI_GPIO_VDD_1V8_LCD_EN,
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DSI_GPIO_TE,
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DSI_GPIO_BRIDGE_EN_0,
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DSI_GPIO_BRIDGE_EN_1,
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DSI_GPIO_BRIDGE_REFCLK_EN,
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DSI_N_GPIO_PANEL, /* add new gpio above this entry */
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};
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enum
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{
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DSI_DISABLE,
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DSI_ENABLE,
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};
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typedef struct
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{
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NvU8 cmd_type;
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NvU8 data_id;
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union
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{
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NvU16 data_len;
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NvU16 delay_ms;
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NvU16 delay_us;
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NvU32 gpio;
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NvU16 frame_cnt;
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struct
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{
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NvU8 data0;
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NvU8 data1;
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} sp;
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} sp_len_dly;
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NvU32 *pdata;
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NvU8 link_id;
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NvBool club_cmd;
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} DSI_CMD, *PDSICMD;
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typedef struct
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{
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NvU16 t_hsdexit_ns;
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NvU16 t_hstrail_ns;
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NvU16 t_datzero_ns;
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NvU16 t_hsprepare_ns;
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NvU16 t_hsprebegin_ns;
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NvU16 t_hspost_ns;
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NvU16 t_clktrail_ns;
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NvU16 t_clkpost_ns;
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NvU16 t_clkzero_ns;
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NvU16 t_tlpx_ns;
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NvU16 t_clkprepare_ns;
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NvU16 t_clkpre_ns;
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NvU16 t_wakeup_ns;
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NvU16 t_taget_ns;
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NvU16 t_tasure_ns;
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NvU16 t_tago_ns;
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} DSI_PHY_TIMING_IN_NS;
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typedef struct
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{
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NvU32 hActive;
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NvU32 vActive;
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NvU32 hFrontPorch;
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NvU32 vFrontPorch;
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NvU32 hBackPorch;
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NvU32 vBackPorch;
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NvU32 hSyncWidth;
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NvU32 vSyncWidth;
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NvU32 hPulsePolarity;
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NvU32 vPulsePolarity;
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NvU32 pixelClkRate;
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} DSITIMINGS, *PDSITIMINGS;
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typedef struct
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{
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NvU8 n_data_lanes; /* required */
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NvU8 pixel_format; /* required */
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NvU8 refresh_rate; /* required */
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NvU8 rated_refresh_rate;
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NvU8 panel_reset; /* required */
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NvU8 virtual_channel; /* required */
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NvU8 dsi_instance;
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NvU16 dsi_panel_rst_gpio;
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NvU16 dsi_panel_bl_en_gpio;
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NvU16 dsi_panel_bl_pwm_gpio;
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NvU16 even_odd_split_width;
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NvU8 controller_vs;
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NvBool panel_has_frame_buffer; /* required*/
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/* Deprecated. Use DSI_SEND_FRAME panel command instead. */
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NvBool panel_send_dc_frames;
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DSI_CMD *dsi_init_cmd; /* required */
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NvU16 n_init_cmd; /* required */
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NvU32 *dsi_init_cmd_array;
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NvU32 init_cmd_array_size;
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NvBool sendInitCmdsEarly;
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DSI_CMD *dsi_early_suspend_cmd;
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NvU16 n_early_suspend_cmd;
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NvU32 *dsi_early_suspend_cmd_array;
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NvU32 early_suspend_cmd_array_size;
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DSI_CMD *dsi_late_resume_cmd;
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NvU16 n_late_resume_cmd;
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NvU32 *dsi_late_resume_cmd_array;
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NvU32 late_resume_cmd_array_size;
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DSI_CMD *dsi_postvideo_cmd;
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NvU16 n_postvideo_cmd;
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NvU32 *dsi_postvideo_cmd_array;
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NvU32 postvideo_cmd_array_size;
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DSI_CMD *dsi_suspend_cmd; /* required */
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NvU16 n_suspend_cmd; /* required */
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NvU32 *dsi_suspend_cmd_array;
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NvU32 suspend_cmd_array_size;
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NvU8 video_data_type; /* required */
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NvU8 video_clock_mode;
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NvU8 video_burst_mode;
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NvU8 ganged_type;
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NvU16 ganged_overlap;
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NvBool ganged_swap_links;
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NvBool ganged_write_to_all_links;
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NvU8 split_link_type;
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NvU8 suspend_aggr;
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NvU16 panel_buffer_size_byte;
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NvU16 panel_reset_timeout_msec;
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NvBool hs_cmd_mode_supported;
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NvBool hs_cmd_mode_on_blank_supported;
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NvBool enable_hs_clock_on_lp_cmd_mode;
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NvBool no_pkt_seq_eot; /* 1st generation panel may not
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* support eot. Don't set it for
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* most panels.*/
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const NvU32 *pktSeq;
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NvU32 *pktSeq_array;
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NvU32 pktSeq_array_size;
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NvBool skip_dsi_pkt_header;
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NvBool power_saving_suspend;
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NvBool suspend_stop_stream_late;
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NvBool dsi2lvds_bridge_enable;
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NvBool dsi2edp_bridge_enable;
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NvU32 max_panel_freq_khz;
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NvU32 lp_cmd_mode_freq_khz;
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NvU32 lp_read_cmd_mode_freq_khz;
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NvU32 hs_clk_in_lp_cmd_mode_freq_khz;
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NvU32 burst_mode_freq_khz;
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NvU32 fpga_freq_khz;
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NvU32 te_gpio;
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NvBool te_polarity_low;
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NvBool dsiEnVRR;
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NvBool dsiVrrPanelSupportsTe;
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NvBool dsiForceSetTePin;
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int panel_gpio[DSI_N_GPIO_PANEL];
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NvBool panel_gpio_populated;
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NvU32 dpd_dsi_pads;
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DSI_PHY_TIMING_IN_NS phyTimingNs;
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NvU8 *bl_name;
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NvBool lp00_pre_panel_wakeup;
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NvBool ulpm_not_supported;
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NvBool use_video_host_fifo_for_cmd;
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NvBool dsi_csi_loopback;
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NvBool set_max_timeout;
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NvBool use_legacy_dphy_core;
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// Swap P/N pins polarity of all data lanes
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NvBool swap_data_lane_polarity;
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// Swap P/N pins polarity of clock lane
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NvBool swap_clock_lane_polarity;
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// Reverse clock polarity for partition A/B. 1st SOT bit goes on negedge of Clock lane
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NvBool reverse_clock_polarity;
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// DSI Lane Crossbar. Allocating xbar array for max number of lanes
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NvBool lane_xbar_exists;
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NvU32 lane_xbar_ctrl[8];
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NvU32 refresh_rate_adj;
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NvU8 dsiPhyType;
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NvBool en_data_scrambling;
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NvU32 dsipll_vco_rate_hz;
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NvU32 dsipll_clkoutpn_rate_hz;
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NvU32 dsipll_clkouta_rate_hz;
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NvU32 vpll0_rate_hz;
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DSITIMINGS dsiTimings;
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// DSC Parameters
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NvBool dsiDscEnable;
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NvU32 dsiDscBpp;
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NvU32 dsiDscNumSlices;
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NvU32 dsiDscSliceWidth;
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NvU32 dsiDscSliceHeight;
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NvBool dsiDscEnBlockPrediction;
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NvBool dsiDscEnDualDsc;
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NvU32 dsiDscDecoderMajorVersion;
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NvU32 dsiDscDecoderMinorVersion;
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NvBool dsiDscUseCustomPPS;
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NvU32 dsiDscCustomPPSData[32];
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// Driver allocates memory for PPS cmd to be sent to Panel
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NvBool ppsCmdMemAllocated;
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} DSI_PANEL_INFO;
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#endif
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