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97 lines
3.6 KiB
C
97 lines
3.6 KiB
C
/*
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* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/******************************************************************************\
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* *
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* Description: *
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* Accommodates sharing of IMP-related structures between kernel interface *
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* files and core RM. *
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* *
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\******************************************************************************/
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#pragma once
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#include <nvtypes.h>
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#if defined(_MSC_VER)
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#pragma warning(disable:4324)
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#endif
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//
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// This file was generated with FINN, an NVIDIA coding tool.
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// Source file: nvimpshared.finn
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//
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//
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// There are only a small number of discrete dramclk frequencies available on
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// the system. This structure contains IMP-relevant information associated
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// with a specific dramclk frequency.
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//
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typedef struct DRAM_CLK_INSTANCE {
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NvU32 dram_clk_freq_khz;
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NvU32 mchub_clk_khz;
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NvU32 mc_clk_khz;
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NvU32 max_iso_bw_kbps;
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//
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// switch_latency_ns is the maximum time required to switch the dramclk
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// frequency to the frequency specified in dram_clk_freq_khz.
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//
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NvU32 switch_latency_ns;
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} DRAM_CLK_INSTANCE;
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//
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// This table is used to collect information from other modules that is needed
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// for RM IMP calculations. (Used on Tegra only.)
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//
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typedef struct TEGRA_IMP_IMPORT_DATA {
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//
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// max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
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// display, assuming display is the only active ISO client. (Note that ISO
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// bandwidth will typically be allocated to multiple clients, so display
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// will generally not have access to the maximum possible bandwidth.)
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//
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NvU32 max_iso_bw_kbps;
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// On Orin, each dram channel is 16 bits wide.
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NvU32 num_dram_channels;
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//
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// dram_clk_instance stores entries for all possible dramclk frequencies,
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// sorted by dramclk frequency in increasing order.
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//
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// "24" is expected to be larger than the actual number of required entries
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// (which is provided by a BPMP API), but it can be increased if necessary.
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//
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// num_dram_clk_entries is filled in with the actual number of distinct
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// dramclk entries.
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//
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NvU32 num_dram_clk_entries;
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DRAM_CLK_INSTANCE dram_clk_instance[24];
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} TEGRA_IMP_IMPORT_DATA;
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