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4bd1d80efb
Current implementation of update_mmu_cache function performs local TLB
flush. It does not take into account ASID information. Besides, it does
not take into account other harts currently running the same mm context
or possible migration of the running context to other harts. Meanwhile
TLB flush is not performed for every context switch if ASID support
is enabled.
Patch [1] proposed to add ASID support to update_mmu_cache to avoid
flushing local TLB entirely. This patch takes into account other
harts currently running the same mm context as well as possible
migration of this context to other harts.
For this purpose the approach from flush_icache_mm is reused. Remote
harts currently running the same mm context are informed via SBI calls
that they need to flush their local TLBs. All the other harts are marked
as needing a deferred TLB flush when this mm context runs on them.
[1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@163.com/
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Fixes: 65d4b9c530 ("RISC-V: Implement ASID allocator")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/#t
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009 Chen Liqin <liqin.chen@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_TLBFLUSH_H
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#define _ASM_RISCV_TLBFLUSH_H
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#include <linux/mm_types.h>
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#include <asm/smp.h>
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#include <asm/errata_list.h>
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#ifdef CONFIG_MMU
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static inline void local_flush_tlb_all(void)
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{
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__asm__ __volatile__ ("sfence.vma" : : : "memory");
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}
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/* Flush one page from local TLB */
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static inline void local_flush_tlb_page(unsigned long addr)
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{
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ALT_FLUSH_TLB_PAGE(__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"));
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}
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static inline void local_flush_tlb_all_asid(unsigned long asid)
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{
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__asm__ __volatile__ ("sfence.vma x0, %0"
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:
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: "r" (asid)
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: "memory");
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}
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static inline void local_flush_tlb_page_asid(unsigned long addr,
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unsigned long asid)
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{
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__asm__ __volatile__ ("sfence.vma %0, %1"
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:
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: "r" (addr), "r" (asid)
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: "memory");
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}
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#else /* CONFIG_MMU */
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#define local_flush_tlb_all() do { } while (0)
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#define local_flush_tlb_page(addr) do { } while (0)
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#endif /* CONFIG_MMU */
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#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
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void flush_tlb_all(void);
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void flush_tlb_mm(struct mm_struct *mm);
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
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void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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#endif
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#else /* CONFIG_SMP && CONFIG_MMU */
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#define flush_tlb_all() local_flush_tlb_all()
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#define flush_tlb_page(vma, addr) local_flush_tlb_page(addr)
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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local_flush_tlb_all();
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}
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#define flush_tlb_mm(mm) flush_tlb_all()
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#endif /* !CONFIG_SMP || !CONFIG_MMU */
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/* Flush a range of kernel pages */
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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flush_tlb_all();
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}
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#endif /* _ASM_RISCV_TLBFLUSH_H */
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