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4bd1d80efb
Current implementation of update_mmu_cache function performs local TLB
flush. It does not take into account ASID information. Besides, it does
not take into account other harts currently running the same mm context
or possible migration of the running context to other harts. Meanwhile
TLB flush is not performed for every context switch if ASID support
is enabled.
Patch [1] proposed to add ASID support to update_mmu_cache to avoid
flushing local TLB entirely. This patch takes into account other
harts currently running the same mm context as well as possible
migration of this context to other harts.
For this purpose the approach from flush_icache_mm is reused. Remote
harts currently running the same mm context are informed via SBI calls
that they need to flush their local TLBs. All the other harts are marked
as needing a deferred TLB flush when this mm context runs on them.
[1] https://lore.kernel.org/linux-riscv/20220821013926.8968-1-tjytimi@163.com/
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Fixes: 65d4b9c530 ("RISC-V: Implement ASID allocator")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/#t
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
32 lines
706 B
C
32 lines
706 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_MMU_H
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#define _ASM_RISCV_MMU_H
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#ifndef __ASSEMBLY__
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typedef struct {
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#ifndef CONFIG_MMU
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unsigned long end_brk;
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#else
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atomic_long_t id;
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#endif
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void *vdso;
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#ifdef CONFIG_SMP
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/* A local icache flush is needed before user execution can resume. */
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cpumask_t icache_stale_mask;
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/* A local tlb flush is needed before user execution can resume. */
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cpumask_t tlb_stale_mask;
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#endif
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} mm_context_t;
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void __init create_pgd_mapping(pgd_t *pgdp, uintptr_t va, phys_addr_t pa,
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phys_addr_t sz, pgprot_t prot);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_MMU_H */
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