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Create the /sys/bus/cxl hierarchy to enumerate: * Memory Devices (per-endpoint control devices) * Memory Address Space Devices (platform address ranges with interleaving, performance, and persistence attributes) * Memory Regions (active provisioned memory from an address space device that is in use as System RAM or delegated to libnvdimm as Persistent Memory regions). For now, only the per-endpoint control devices are registered on the 'cxl' bus. However, going forward it will provide a mechanism to coordinate cross-device interleave. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2) Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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1.0 KiB
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35 lines
1.0 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===================================
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Compute Express Link Memory Devices
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===================================
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A Compute Express Link Memory Device is a CXL component that implements the
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CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
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or both. It is enumerated as a PCI device for configuration and passing
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messages over an MMIO mailbox. Its contribution to the System Physical
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Address space is handled via HDM (Host Managed Device Memory) decoders
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that optionally define a device's contribution to an interleaved address
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range across multiple devices underneath a host-bridge or interleaved
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across host-bridges.
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Driver Infrastructure
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=====================
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This section covers the driver infrastructure for a CXL memory device.
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CXL Memory Device
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-----------------
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.. kernel-doc:: drivers/cxl/mem.c
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:doc: cxl mem
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.. kernel-doc:: drivers/cxl/mem.c
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:internal:
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CXL Bus
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-------
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.. kernel-doc:: drivers/cxl/bus.c
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:doc: cxl bus
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