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0499220d6d
DT properties which can have multiple entries need to specify what the entries are and define how many entries there can be. In the case of only a single entry, just 'maxItems: 1' is sufficient. Add the missing entry constraints. These were found with a modified meta-schema. Unfortunately, there are a few cases where the size constraints are not defined such as common bindings, so the meta-schema can't be part of the normal checks. Cc: Jens Axboe <axboe@kernel.dk> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Jonathan Cameron <jic23@kernel.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Marc Zyngier <maz@kernel.org> Cc: Mauro Carvalho Chehab <mchehab@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Sebastian Reichel <sre@kernel.org> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sre@kernel.org> Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Suman Anna <s-anna@ti.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210104230253.2805217-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
100 lines
2.1 KiB
YAML
100 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive L2 Cache Controller
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maintainers:
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- Sagar Kadam <sagar.kadam@sifive.com>
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- Yash Shah <yash.shah@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description:
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The SiFive Level 2 Cache Controller is used to provide access to fast copies
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of memory for masters in a Core Complex. The Level 2 Cache Controller also
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acts as directory-based coherency manager.
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All the properties in ePAPR/DeviceTree specification applies for this platform.
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allOf:
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- $ref: /schemas/cache-controller.yaml#
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select:
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properties:
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compatible:
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items:
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- enum:
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- sifive,fu540-c000-ccache
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: sifive,fu540-c000-ccache
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- const: cache
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cache-block-size:
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const: 64
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cache-level:
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const: 2
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cache-sets:
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const: 1024
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cache-size:
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const: 2097152
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cache-unified: true
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interrupts:
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description: |
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Must contain entries for DirError, DataError and DataFail signals.
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minItems: 3
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maxItems: 3
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reg:
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maxItems: 1
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next-level-cache: true
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memory-region:
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maxItems: 1
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description: |
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The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
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The reserved memory node should be defined as per the bindings in reserved-memory.txt.
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additionalProperties: false
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required:
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- compatible
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- cache-block-size
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- cache-level
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- cache-sets
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- cache-size
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- cache-unified
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- interrupts
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- reg
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examples:
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- |
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cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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reg = <0x2010000 0x1000>;
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interrupt-parent = <&plic0>;
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interrupts = <1>,
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<2>,
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<3>;
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next-level-cache = <&L25>;
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memory-region = <&l2_lim>;
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};
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