mirror of
https://github.com/tbsdtv/linux_media.git
synced 2025-07-22 12:21:00 +02:00
147 lines
4.2 KiB
C
147 lines
4.2 KiB
C
#ifndef _TBSMOD_IO_H
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#define _TBSMOD_IO_H
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//spi flash
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#define SPI_CONFIG 0x10
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#define SPI_STATUS 0x10
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#define SPI_COMMAND 0x14
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#define SPI_WT_DATA 0x18
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#define SPI_RD_DATA 0x1c
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#define SPI_ENABLE 0x1c
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#define SPI_MAX2871 0x2c // spi config ad4351
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#define SPI_DEVICE 0x20 // spi choose: 0 is for 9789, 1 is for fpga , default is 0
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#define SPI_RESET 0x24 // spi config 9789 reset , default 0, 1 is valid. read for qamb is mod and control
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#define SPI_AD4351 0x2c // spi config ad4351
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#define AD9789_MODULATION 0x28 // spi mod set
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#define AD9789B_MODULATION 0x38 // spi mod set for tbs6008
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#define SPI_9789B_RESET 0x34 // spi config 9789b reset , default 0, 1 is valid. read for qamb is mod and control
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#define SPI_BW_LIGHT 0x34 // spi bw light set
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#define SPI_TESTREG 0x30 // debug
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#define MOD_RESET_IPCORE 0x38 //qamb reset ipcore
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#define ISDBT_IPRST 0x38
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#define MOD_ASI_DEVICE 0X14
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#define MOD_ASI_BASEADDRESS 0x4000
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#define MOD_GPIO_BASEADDRESS 0x0000
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#define MOD_ASI_RST 0x00
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//ASI spi flash
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#define ASI_SPI_CONFIG 0x04
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#define ASI_SPI_STATUS 0x00
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#define ASI_SPI_COMMAND 0x08
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#define ASI_SPI_WT_DATA 0x0c
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#define ASI_SPI_RD_DATA 0x04
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#define ASI_SPI_ENABLE 0x10
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#define ASI_SPI_TESTREG 0x28 // debug
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#define I2C_STATUS 0x00
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#define I2C_COMMAND 0x00
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#define I2C_W_DATA 0x04
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#define I2C_R_DATA 0x04
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#define I2C_SPEED 0x08
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#define I2C0_BASEADDRESS 0x4000
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#define I2C1_BASEADDRESS 0x5000
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enum{
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AD9789_SPI_CTL = 0x00,
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AD9789_SATURA_CNT = 0x01,
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AD9789_PARITY_CNT = 0x02,
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AD9789_INT_ENABLE = 0x03,
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AD9789_INT_STATUS = 0x04,
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AD9789_CHANNEL_ENABLE = 0x05,
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AD9789_BYPASS = 0x06,
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AD9789_QAM_CONFIG = 0x07,
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AD9789_SUM_SCALAR = 0x08,
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AD9789_INPUT_SCALAR = 0x09,
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AD9789_NCO_0_FRE = 0x0C,
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AD9789_NCO_1_FRE = 0x0F,
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AD9789_NCO_2_FRE = 0x12,
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AD9789_NCO_3_FRE = 0x15,
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AD9789_RATE_CONVERT_Q = 0x18,
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AD9789_RATE_CONVERT_P = 0x1B,
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AD9789_CENTER_FRE_BPF = 0x1D,
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AD9789_FRE_UPDATE = 0x1E,
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AD9789_HARDWARE_VERSION = 0x1F,
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AD9789_INTERFACE_CONFIG = 0x20,
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AD9789_DATA_CONTROL = 0x21,
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AD9789_DCO_FRE = 0x22,
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AD9789_INTERNAL_COLCK_ADJUST = 0x23,
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AD9789_PARAMETER_UPDATE = 0x24,
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AD9789_CHANNEL_0_GAIN = 0x25,
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AD9789_CHANNEL_1_GAIN = 0x26,
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AD9789_CHANNEL_2_GAIN = 0x27,
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AD9789_CHANNEL_3_GAIN = 0x28,
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AD9789_SPEC_SHAPING = 0x29,
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AD9789_Mu_DELAY_CONTROL_1 = 0x2F,
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AD9789_Mu_CONTROL_DUTY_CYCLE = 0x30,
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AD9789_CLOCK_RECIVER_1 = 0x31,
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AD9789_CLOCK_RECIVER_2 = 0x32,
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AD9789_Mu_DELAY_CONTROL_2 = 0x33,
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AD9789_DAC_BIAS = 0x36,
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AD9789_DAC_DECODER = 0x38,
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AD9789_Mu_DELAY_CONTROL_3 = 0x39,
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AD9789_Mu_DELAY_CONTROL_4 = 0x3A,
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AD9789_FULL_SCALE_CURRENT_1 = 0X3C,
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AD9789_FULL_SCALE_CURRENT_2 = 0X3D,
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AD9789_PHASE_DETECTOR_CONTROL = 0x3E,
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AD9789_BIST_CONTROL = 0x40,
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AD9789_BIST_STATUS = 0x41,
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AD9789_BIST_ZERO_LENGTH = 0x42,
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AD9789_BIST_VECTOR_LENGTH = 0x44,
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AD9789_BIST_CLOCK_ADJUST = 0x47,
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AD9789_SIGN_0_CONTROL = 0x48,
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AD9789_SIGN_0_CLOCK_ADJUST = 0x49,
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AD9789_SIGN_1_CONTROL = 0x4A,
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AD9789_SIGN_1_CLOCK_ADJUST = 0x4B,
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AD9789_REGFNL_0_FREQ = 0x4C,
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AD9789_REGFNL_1_FREQ = 0x4D,
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AD9789_BITS_SIGNATURE_0 = 0x50,
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AD9789_BITS_SIGNATURE_1 = 0x53
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};
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#define DMA_STATUS 0x00
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#define DMA_GO 0x00
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#define DMA_SIZE 0x04
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#define DMA_SIZE_TOTAL 0x04
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#define DMA_ADDR_HIGH 0x08
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#define DMA_ADDR_LOW 0x0c
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#define DMA_ADDR_CELL 0x48
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#define DMA_DELAY 0x14
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#define DMA_DELAYSHORT 0x18
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#define DMA_SPEED_CTRL 0x20
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#define DMA_INT_MONITOR 0x1c
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#define DMARD_SPEED 0x54 //add<64><64>6032
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#define EMPTY_PACKAGE_SPEED 0x58 //add<64><64>6032
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#define DMARD_SIZE 0x5C //add<64><64>6032
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#define DMA_FRAME_CNT 0x24
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#define Dmaout_adapter0 0x8000
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#define Dmaout_adapter1 0x9000
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#define Dmaout_adapter2 0xa000
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#define Dmaout_adapter3 0xb000
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#define Dmaout_adapter4 0x8800
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#define Dmaout_adapter5 0x9800
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#define Dmaout_adapter6 0xa800
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#define Dmaout_adapter7 0xb800
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#define DMA_BASEADDRESS(_type,_n) ((_type == 0x6032)?(0x8000+0x200*_n):(0x8000+0x1000*_n))
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#define DMA_MASK(_n) (0x18 + 4*_n )
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#define DMA_STATUS(_n) (0x0010<<_n)
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#define Int_adapter 0xc000
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#endif
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