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b96b0c5de6
The nVHE KVM hyp drains and disables the SPE buffer, before
entering the guest, as the EL1&0 translation regime
is going to be loaded with that of the guest.
But this operation is performed way too late, because :
- The owning translation regime of the SPE buffer
is transferred to EL2. (MDCR_EL2_E2PB == 0)
- The guest Stage1 is loaded.
Thus the flush could use the host EL1 virtual address,
but use the EL2 translations instead of host EL1, for writing
out any cached data.
Fix this by moving the SPE buffer handling early enough.
The restore path is doing the right thing.
Fixes: 014c4c77aa ("KVM: arm64: Improve debug register save/restore flow")
Cc: stable@vger.kernel.org
Cc: Christoffer Dall <christoffer.dall@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210302120345.3102874-1-suzuki.poulose@arm.com
Message-Id: <20210305185254.3730990-2-maz@kernel.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
86 lines
1.8 KiB
C
86 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <hyp/debug-sr.h>
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/debug-monitors.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_hyp.h>
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#include <asm/kvm_mmu.h>
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static void __debug_save_spe(u64 *pmscr_el1)
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{
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u64 reg;
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/* Clear pmscr in case of early return */
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*pmscr_el1 = 0;
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/* SPE present on this CPU? */
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if (!cpuid_feature_extract_unsigned_field(read_sysreg(id_aa64dfr0_el1),
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ID_AA64DFR0_PMSVER_SHIFT))
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return;
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/* Yes; is it owned by EL3? */
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reg = read_sysreg_s(SYS_PMBIDR_EL1);
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if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT))
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return;
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/* No; is the host actually using the thing? */
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reg = read_sysreg_s(SYS_PMBLIMITR_EL1);
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if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT)))
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return;
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/* Yes; save the control register and disable data generation */
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*pmscr_el1 = read_sysreg_s(SYS_PMSCR_EL1);
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write_sysreg_s(0, SYS_PMSCR_EL1);
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isb();
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/* Now drain all buffered data to memory */
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psb_csync();
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dsb(nsh);
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}
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static void __debug_restore_spe(u64 pmscr_el1)
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{
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if (!pmscr_el1)
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return;
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/* The host page table is installed, but not yet synchronised */
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isb();
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/* Re-enable data generation */
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write_sysreg_s(pmscr_el1, SYS_PMSCR_EL1);
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}
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void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu)
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{
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/* Disable and flush SPE data generation */
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__debug_save_spe(&vcpu->arch.host_debug_state.pmscr_el1);
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}
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void __debug_switch_to_guest(struct kvm_vcpu *vcpu)
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{
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__debug_switch_to_guest_common(vcpu);
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}
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void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu)
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{
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__debug_restore_spe(vcpu->arch.host_debug_state.pmscr_el1);
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}
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void __debug_switch_to_host(struct kvm_vcpu *vcpu)
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{
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__debug_switch_to_host_common(vcpu);
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}
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u32 __kvm_get_mdcr_el2(void)
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{
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return read_sysreg(mdcr_el2);
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}
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