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ff3cfcb0d4
The decision to allow parallel bringup of secondary CPUs checks
CC_ATTR_GUEST_STATE_ENCRYPT to detect encrypted guests. Those cannot use
parallel bootup because accessing the local APIC is intercepted and raises
a #VC or #VE, which cannot be handled at that point.
The check works correctly, but only for AMD encrypted guests. TDX does not
set that flag.
As there is no real connection between CC attributes and the inability to
support parallel bringup, replace this with a generic control flag in
x86_cpuinit and let SEV-ES and TDX init code disable it.
Fixes: 0c7ffa32db ("x86/smpboot/64: Implement arch_cpuhp_init_parallel_bringup() and enable it")
Reported-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky@amd.com>
Tested-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: https://lore.kernel.org/r/87ilc9gd2d.ffs@tglx
170 lines
4.8 KiB
C
170 lines
4.8 KiB
C
/*
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* Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <asm/acpi.h>
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#include <asm/bios_ebda.h>
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#include <asm/paravirt.h>
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#include <asm/pci_x86.h>
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#include <asm/mpspec.h>
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#include <asm/setup.h>
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#include <asm/apic.h>
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#include <asm/e820/api.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/io_apic.h>
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#include <asm/hpet.h>
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#include <asm/memtype.h>
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#include <asm/tsc.h>
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#include <asm/iommu.h>
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#include <asm/mach_traps.h>
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#include <asm/irqdomain.h>
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#include <asm/realmode.h>
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void x86_init_noop(void) { }
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void __init x86_init_uint_noop(unsigned int unused) { }
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static int __init iommu_init_noop(void) { return 0; }
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static void iommu_shutdown_noop(void) { }
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bool __init bool_x86_init_noop(void) { return false; }
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void x86_op_int_noop(int cpu) { }
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int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
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void get_rtc_noop(struct timespec64 *now) { }
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static __initconst const struct of_device_id of_cmos_match[] = {
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{ .compatible = "motorola,mc146818" },
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{}
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};
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/*
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* Allow devicetree configured systems to disable the RTC by setting the
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* corresponding DT node's status property to disabled. Code is optimized
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* out for CONFIG_OF=n builds.
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*/
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static __init void x86_wallclock_init(void)
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{
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struct device_node *node = of_find_matching_node(NULL, of_cmos_match);
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if (node && !of_device_is_available(node)) {
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x86_platform.get_wallclock = get_rtc_noop;
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x86_platform.set_wallclock = set_rtc_noop;
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}
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}
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/*
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* The platform setup functions are preset with the default functions
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* for standard PC hardware.
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*/
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struct x86_init_ops x86_init __initdata = {
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.resources = {
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.probe_roms = probe_roms,
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.reserve_resources = reserve_standard_io_resources,
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.memory_setup = e820__memory_setup_default,
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},
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.mpparse = {
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.setup_ioapic_ids = x86_init_noop,
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.find_smp_config = default_find_smp_config,
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.get_smp_config = default_get_smp_config,
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},
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.irqs = {
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.pre_vector_init = init_ISA_irqs,
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.intr_init = native_init_IRQ,
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.intr_mode_select = apic_intr_mode_select,
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.intr_mode_init = apic_intr_mode_init,
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.create_pci_msi_domain = native_create_pci_msi_domain,
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},
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.oem = {
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.arch_setup = x86_init_noop,
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.banner = default_banner,
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},
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.paging = {
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.pagetable_init = native_pagetable_init,
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},
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.timers = {
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.setup_percpu_clockev = setup_boot_APIC_clock,
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.timer_init = hpet_time_init,
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.wallclock_init = x86_wallclock_init,
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},
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.iommu = {
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.iommu_init = iommu_init_noop,
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},
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.pci = {
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.init = x86_default_pci_init,
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.init_irq = x86_default_pci_init_irq,
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.fixup_irqs = x86_default_pci_fixup_irqs,
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},
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.hyper = {
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.init_platform = x86_init_noop,
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.guest_late_init = x86_init_noop,
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.x2apic_available = bool_x86_init_noop,
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.msi_ext_dest_id = bool_x86_init_noop,
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.init_mem_mapping = x86_init_noop,
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.init_after_bootmem = x86_init_noop,
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},
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.acpi = {
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.set_root_pointer = x86_default_set_root_pointer,
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.get_root_pointer = x86_default_get_root_pointer,
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.reduced_hw_early_init = acpi_generic_reduced_hw_init,
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},
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};
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struct x86_cpuinit_ops x86_cpuinit = {
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.early_percpu_clock_init = x86_init_noop,
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.setup_percpu_clockev = setup_secondary_APIC_clock,
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.parallel_bringup = true,
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};
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static void default_nmi_init(void) { };
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static void enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { }
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static bool enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return false; }
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static bool enc_tlb_flush_required_noop(bool enc) { return false; }
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static bool enc_cache_flush_required_noop(void) { return false; }
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static bool is_private_mmio_noop(u64 addr) {return false; }
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struct x86_platform_ops x86_platform __ro_after_init = {
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.calibrate_cpu = native_calibrate_cpu_early,
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.calibrate_tsc = native_calibrate_tsc,
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.get_wallclock = mach_get_cmos_time,
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.set_wallclock = mach_set_cmos_time,
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.iommu_shutdown = iommu_shutdown_noop,
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.is_untracked_pat_range = is_ISA_range,
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.nmi_init = default_nmi_init,
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.get_nmi_reason = default_get_nmi_reason,
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.save_sched_clock_state = tsc_save_sched_clock_state,
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.restore_sched_clock_state = tsc_restore_sched_clock_state,
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.realmode_reserve = reserve_real_mode,
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.realmode_init = init_real_mode,
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.hyper.pin_vcpu = x86_op_int_noop,
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.hyper.is_private_mmio = is_private_mmio_noop,
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.guest = {
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.enc_status_change_prepare = enc_status_change_prepare_noop,
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.enc_status_change_finish = enc_status_change_finish_noop,
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.enc_tlb_flush_required = enc_tlb_flush_required_noop,
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.enc_cache_flush_required = enc_cache_flush_required_noop,
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},
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};
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EXPORT_SYMBOL_GPL(x86_platform);
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struct x86_apic_ops x86_apic_ops __ro_after_init = {
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.io_apic_read = native_io_apic_read,
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.restore = native_restore_boot_irq_mode,
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};
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