mirror of
https://github.com/tbsdtv/linux_media.git
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86 lines
2.2 KiB
C
86 lines
2.2 KiB
C
/*
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TurboSight TBS PCIE HDMI/SDI capture driver
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Copyright (C) 2017 www.tbsdtv.com
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*/
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#ifndef _TBS_PCIE_REG_H
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#define _TBS_PCIE_REG_H
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#define TBS_GPIO_BASE 0x0000
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#define TBS_GPIO_DATA(i) ((i) *4 )
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#define TBS_GPIO_DATA_0 0x00 /* adapter 0 */
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#define TBS_GPIO_DATA_1 0x04 /* adapter 1 */
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#define TBS_GPIO_DATA_2 0x08 /* adapter 2 */
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#define TBS_GPIO_DATA_3 0x0c /* adapter 3 */
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#define TBS_I2C_BASE_0 0x4000
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#define TBS_I2C_BASE_1 0x5000
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#define TBS_I2C_BASE_2 0x6000
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#define TBS_I2C_BASE_3 0x7000
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#define TBS_I2C_CTRL 0x00
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#define TBS_I2C_DATA 0x04
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#define TBS_I2C_START_BIT (0x00000001 << 7)
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#define TBS_I2C_STOP_BIT (0x00000001 << 6)
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#define TBS_I2C_SADDR_2BYTE (0x00000001 << 5)
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#define TBS_I2C_SADDR_1BYTE (0x00000001 << 4)
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#define TBS_I2C_WRITE_BIT (0x00000001 << 8)
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#define TBS_INT_BASE 0xc000
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#define TBS_INT_STATUS 0x00
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#define TBS_INT_ENABLE 0x04
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#define TBS_I2C_MASK_0 0x08
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#define TBS_I2C_MASK_1 0x0c
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#define TBS_I2C_MASK_2 0x10
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#define TBS_I2C_MASK_3 0x14
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#define TBS_DMA_MASK(i) (0x18 + ((i) * 0x04))
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#define TBS_DMA_MASK_0 0x18
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#define TBS_DMA_MASK_1 0x1C
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#define TBS_DMA_MASK_2 0x20
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#define TBS_DMA_MASK_3 0x24
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#define TBS_DMA_BASE(i) (0x8000 + ((i) * 0x1000))
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#define TBS_DMA_BASE_0 0x8000 //audio
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#define TBS_DMA_BASE_1 0x9000 // video
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#define TBS_DMA_BASE_2 0xa000
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#define TBS_DMA_BASE_3 0xb000
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#define TBS_DMA_START 0x00
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#define TBS_DMA_STATUS 0x00
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#define TBS_DMA_SIZE 0x04
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#define TBS_DMA_ADDR_HIGH 0x08
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#define TBS_DMA_ADDR_LOW 0x0c
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#define TBS_DMA_CELL_SIZE 0x10
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//#define TBS_AUDIO_CELL_SIZE 2944 //44.1k
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#define TBS_AUDIO_CELL_SIZE 4096 //48k
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#define DMA_VIDEO_CELL ( (videodev->Interlaced==1) ? (videodev->width*videodev->height) : (videodev->width*videodev->height*2) )
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//undefine in fpga now
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#define RISC_INT_BIT 0x08000000
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#define RISC_SYNCO 0xC0000000
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#define RISC_SYNCE 0xD0000000
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#define RISC_JUMP 0xB0000000
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#define RISC_LINESTART 0x90000000
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#define RISC_INLINE 0xA0000000
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/* ASI == SDI excep baseaddress */
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#define ASI0_BASEADDRESS 0x5000
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#define ASI_CHIP_RST 0x00
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#define ASI_SPI_CONFIG 0x04
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#define ASI_SPI_CMD 0x08
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#define ASI_SPI_WT_32 0x0c
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#define ASI_SPI_ENABLE 0x10
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#define ASI_STATUS 0x00
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#define ASI_SPI_RD_32 0x04
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#endif
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