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9b7c13b83c
The check for 'qcom,ice' property is wrong. Fix it by checking using
if-required clause and expand the clocks minItems and maxItems for
platforms where 'qcom,ice' is not required so that it includes platforms
with single reg entry and clocks that do not provide an ICE one.
Fixes: 29a6d1215b ("scsi: ufs: dt-bindings: qcom: Add ICE phandle")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230623113009.2512206-2-abel.vesa@linaro.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
279 lines
6.7 KiB
YAML
279 lines
6.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Universal Flash Storage (UFS) Controller
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Andy Gross <agross@kernel.org>
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# Select only our matches, not all jedec,ufs-2.0
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select:
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properties:
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compatible:
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contains:
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const: qcom,ufshc
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- qcom,msm8994-ufshc
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- qcom,msm8996-ufshc
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- qcom,msm8998-ufshc
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- qcom,sa8775p-ufshc
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- qcom,sc8280xp-ufshc
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- qcom,sdm845-ufshc
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- qcom,sm6350-ufshc
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- qcom,sm8150-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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- qcom,sm8550-ufshc
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- const: qcom,ufshc
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- const: jedec,ufs-2.0
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clocks:
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minItems: 8
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maxItems: 11
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clock-names:
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minItems: 8
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maxItems: 11
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dma-coherent: true
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interconnects:
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minItems: 2
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maxItems: 2
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interconnect-names:
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items:
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- const: ufs-ddr
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- const: cpu-ufs
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iommus:
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minItems: 1
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maxItems: 2
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: ufsphy
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power-domains:
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maxItems: 1
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qcom,ice:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the Inline Crypto Engine node
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reg:
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minItems: 1
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maxItems: 2
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required-opps:
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maxItems: 1
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resets:
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maxItems: 1
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'#reset-cells':
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const: 1
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reset-names:
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items:
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- const: rst
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reset-gpios:
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maxItems: 1
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description:
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GPIO connected to the RESET pin of the UFS memory device.
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required:
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- compatible
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- reg
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allOf:
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- $ref: ufs-common.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-ufshc
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- qcom,sa8775p-ufshc
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- qcom,sc8280xp-ufshc
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- qcom,sm8250-ufshc
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- qcom,sm8350-ufshc
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- qcom,sm8450-ufshc
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- qcom,sm8550-ufshc
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then:
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properties:
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clocks:
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minItems: 8
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maxItems: 8
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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reg:
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minItems: 1
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sdm845-ufshc
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- qcom,sm6350-ufshc
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- qcom,sm8150-ufshc
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then:
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properties:
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clocks:
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minItems: 9
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maxItems: 9
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clock-names:
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items:
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- const: core_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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- const: rx_lane1_sync_clk
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- const: ice_core_clk
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reg:
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minItems: 2
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8996-ufshc
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then:
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properties:
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clocks:
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minItems: 11
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maxItems: 11
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clock-names:
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items:
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- const: core_clk_src
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- const: core_clk
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- const: bus_clk
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- const: bus_aggr_clk
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- const: iface_clk
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- const: core_clk_unipro_src
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- const: core_clk_unipro
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- const: core_clk_ice
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- const: ref_clk
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- const: tx_lane0_sync_clk
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- const: rx_lane0_sync_clk
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reg:
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minItems: 1
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maxItems: 1
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# TODO: define clock bindings for qcom,msm8994-ufshc
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- if:
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required:
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- qcom,ice
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then:
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properties:
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reg:
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maxItems: 1
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clocks:
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minItems: 8
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maxItems: 8
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else:
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properties:
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reg:
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minItems: 1
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maxItems: 2
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clocks:
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minItems: 8
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maxItems: 11
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interconnect/qcom,sm8450.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@1d84000 {
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compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
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"jedec,ufs-2.0";
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reg = <0 0x01d84000 0 0x3000>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufs_mem_phy_lanes>;
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phy-names = "ufsphy";
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lanes-per-direction = <2>;
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#reset-cells = <1>;
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resets = <&gcc GCC_UFS_PHY_BCR>;
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reset-names = "rst";
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reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
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vcc-supply = <&vreg_l7b_2p5>;
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vcc-max-microamp = <1100000>;
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vccq-supply = <&vreg_l9b_1p2>;
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vccq-max-microamp = <1200000>;
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power-domains = <&gcc UFS_PHY_GDSC>;
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iommus = <&apps_smmu 0xe0 0x0>;
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interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
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interconnect-names = "ufs-ddr", "cpu-ufs";
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clock-names = "core_clk",
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"bus_aggr_clk",
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"iface_clk",
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"core_clk_unipro",
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"ref_clk",
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"tx_lane0_sync_clk",
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"rx_lane0_sync_clk",
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"rx_lane1_sync_clk";
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clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&gcc GCC_UFS_PHY_AHB_CLK>,
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<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
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<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
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freq-table-hz = <75000000 300000000>,
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<0 0>,
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<0 0>,
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<75000000 300000000>,
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<75000000 300000000>,
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<0 0>,
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<0 0>,
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<0 0>;
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};
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};
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